The 1.8V power rail bounces during power-up. Try to reduce that.

This is needed to pass the empty string.

On the VC707 default is feedback enabled and it breaks phase control if
you disable it. On the VCU118 the default is disabled and it breaks RX
phase compensation if you don't need it.

Paths from this clock should be analyzed. Instead, cut the false
path from the PowerOnResetFPGAOnly.

When there is a name conflict for a register and a pin, the pin
is no longer accessible by it's name in [get_pins X].