Commits · spec_benchmarking · github.com / Phantom1003 / fpga-shells

Feb 09, 2019
- slower clocks · f9fa651e
  Erik Danie authored Feb 08, 2019
  
  f9fa651e
Jan 30, 2019
- Merge pull request #51 from sifive/new_arty_shell · e21092d8
  Erik Danie authored Jan 29, 2019
```
New Arty 100T Shell
```
  e21092d8
Jan 23, 2019
- adding back another file · 96aca44c
  Erik Danie authored Jan 22, 2019
  
  96aca44c
Jan 19, 2019
- added back necessary file · ed9f70e5
  Erik Danie authored Jan 18, 2019
  
  ed9f70e5
Jan 15, 2019
- lint fix · 9aee712c
  Erik Danie authored Jan 14, 2019
  
  9aee712c
Jan 12, 2019
- Merge branch 'master' into new_arty_shell · 38d85244
  Erik Danie authored Jan 11, 2019
  
  38d85244
Jan 11, 2019
- Merge pull request #52 from sifive/vcu118BasicOverlays · fa65748a
  Henry Styles authored Jan 10, 2019
```
Layer VCU118 shell above VCU118ShellBasicOverlays
```
  fa65748a
Jan 09, 2019
- Layer VCU118 shell above VCU118ShellBasicOverlays · 4fc77b1f
  Henry Styles authored Nov 14, 2018
  
  4fc77b1f
Dec 21, 2018
- removed extraneous comment · fc3bc198
  Erik Danie authored Dec 20, 2018
  
  fc3bc198
- removed extraneous comment · 833c8e2e
  Erik Danie authored Dec 20, 2018
  
  833c8e2e
Dec 20, 2018
- changed transfersizes to work in federation · f2a8e202
  Erik Danie authored Dec 14, 2018
  
  f2a8e202
- arty shell checkpoint w/ working mig · 78f4167a
  Erik Danie authored Dec 12, 2018
  
  78f4167a
- arty 100t shell (unfinished) · 921a4f7c
  Erik Danie authored Nov 07, 2018
  
  921a4f7c
- Arty new shell (unfinished) · 9a01ccc0
  Erik Danie authored Nov 07, 2018
  
  9a01ccc0
Dec 13, 2018
- connectSPI and connectUART no longer require entire dut (#50) · 3d473854
  Henry Cook authored Dec 12, 2018
  
  3d473854
Dec 02, 2018
- Merge pull request #49 from sifive/dma-ecam-base · e8c6b3a5
  Wesley W. Terpstra authored Dec 01, 2018
```
XDMA: support ECAM at any legal multiple
```
  e8c6b3a5
- xdma: support ECAM at non-4G boundaries · f90f4b63
  Wesley W. Terpstra authored Dec 01, 2018
  
  f90f4b63
- vivado tcl: don't fail to run post-impl debug · f3f274c0
  Wesley W. Terpstra authored Dec 01, 2018
  
  f3f274c0
Nov 29, 2018
- Merge pull request #48 from sifive/10g-ether · c9ec7aac
  Wesley W. Terpstra authored Nov 28, 2018
```
10G Ethernet
```
  c9ec7aac
Nov 23, 2018
- nfmac10g: fix a power-0 bug · ffc39fdd
  Wesley W. Terpstra authored Nov 23, 2018
  
  ffc39fdd
- nfmac10g: work around 'byte' keyword conflict · e8dbab01
  Wesley W. Terpstra authored Nov 22, 2018
  
  e8dbab01
- xxv_ethernet: clean up parameters · c58e585c
  Wesley W. Terpstra authored Nov 22, 2018
  
  c58e585c
- ethernet: fix clock of tx/rx-enable · 85cbd679
  Wesley W. Terpstra authored Nov 13, 2018
  
  85cbd679
- ethernet: tie a few choice status pins and allow packet sizes · f2117257
  Wesley W. Terpstra authored Oct 03, 2018
  
  f2117257
- ethernet: close timing · 03fd3741
  Wesley W. Terpstra authored Sep 27, 2018
  
  03fd3741
- ethernet: split mac/pcs between design/shell · 19defc03
  Wesley W. Terpstra authored Sep 27, 2018
  
  19defc03
- ethernet: connect the clocks! · 4a60f109
  Wesley W. Terpstra authored Sep 27, 2018
  
  4a60f109
- ethernet: a bit more visibility into reset · ca5cf7b5
  Wesley W. Terpstra authored Sep 25, 2018
  
  ca5cf7b5
- ethernet: add QSFP2 as well · 886435e1
  Wesley W. Terpstra authored Sep 25, 2018
  
  886435e1
- ethernet: supply a legit dclk · 380835fb
  Wesley W. Terpstra authored Sep 25, 2018
  
  380835fb
- xxv_ethernet: assign pins => no need for location/group · 2d95f7d1
  Wesley W. Terpstra authored Sep 25, 2018
  
  2d95f7d1
- ethernet: compiles to verilog · f3b7144e
  Wesley W. Terpstra authored Sep 24, 2018
  
  f3b7144e
- xxv_ethernet: add support for 10G transceiver · fbcaccc3
  Wesley W. Terpstra authored Sep 24, 2018
  
  fbcaccc3
Nov 20, 2018
- Fpga spi speedup2 (#47) · a7a22f7a
  Mohit Wani authored Nov 19, 2018
```
FPGA changes for SPI speedup
```
  a7a22f7a
Oct 24, 2018
- Merge pull request #45 from sifive/revert-43-fpga-spi_speedup · 2f29efc1
  Megan Wachs authored Oct 23, 2018
```
Revert "Fpga spi speedup"
```
  2f29efc1
- Revert "SPI speedup related FPGA changes" · a0cc85e0
  Megan Wachs authored Oct 23, 2018
```
This reverts commit 9eb56625.
```
  a0cc85e0
Oct 16, 2018

SPI speedup related FPGA changes · 9eb56625

Mohit Wani authored Oct 15, 2018

* spi related changes

* fpga timing related fixes

* added defaulSampleDel as the default sync stage delay.

* updatd the review

9eb56625

Oct 15, 2018
- mbus: switch to multi-bank API (#44) · a45fb1f3
  Wesley W. Terpstra authored Oct 14, 2018
  
  a45fb1f3
Oct 02, 2018
- Xilinx: Add KEEPER primitive (#42) · 39cb995a
  Megan Wachs authored Oct 01, 2018
  
  39cb995a
Aug 28, 2018
- VC707Shell: default to 1GB of RAM (what the board ships with) (#40) · fea03f64
  Wesley W. Terpstra authored Aug 27, 2018
  
  fea03f64