Commits · new-shell-updates-masterbump · github.com / Phantom1003 / fpga-shells · GitLab

Aug 09, 2018
- replace HasCrossing with CrossesToOnlyOneClockDomain · 3ca67e21
  Sagar Karandikar authored Aug 08, 2018
  
  3ca67e21
Aug 08, 2018
- wip bump · d5d37076
  Sagar Karandikar authored Aug 07, 2018
  
  d5d37076
Aug 04, 2018
- Merge branch 'master' into new-shell-updates-masterbump · 8a2c3daf
  Sagar Karandikar authored Aug 03, 2018
  
  8a2c3daf
Aug 03, 2018
- VCU118NewShell: New-style shell for VCU118 · b1185641
  Sagar Karandikar authored Aug 02, 2018
  
  b1185641
- xdma: Add new Xilinx XDMA PCIe IP · d9e8623e
  Sagar Karandikar authored Aug 02, 2018
  
  d9e8623e
- VC707NewShell: Update ChipLinkOverlay, use new UART/SDIO/JTAG overlays · 2f6b1750
  Sagar Karandikar authored Aug 02, 2018
  
  2f6b1750
- ChipLinkOverlay: take phase/margin arguments · 6fd968f0
  Sagar Karandikar authored Aug 02, 2018
  
  6fd968f0
- JTAGOverlay: New JTAGOverlay. Has not been tested on FPGA · 664b33b2
  Sagar Karandikar authored Aug 02, 2018
  
  664b33b2
- UARTOverlay: New UARTOverlay · 678ce547
  Sagar Karandikar authored Aug 02, 2018
  
  678ce547
- SDIOOverlay: New SDIO Overlay · ab49ba76
  Sagar Karandikar authored Aug 02, 2018
  
  ab49ba76
- xilinx: Various infrastructure updates: PowerOnResetFPGAOnly names, · e498a53b
  Sagar Karandikar authored Aug 02, 2018
```
support USE_PHASE_ALIGNMENT, new constraints for Series7Shell, keep
projects around for GUI use
```
  e498a53b
- shell: ClockOverlay api supply clock · a0f43819
  Sagar Karandikar authored Aug 02, 2018
  
  a0f43819
- ioshell: Fix ordering of bundle contents, add ability to specify false · d123c0c6
  Sagar Karandikar authored Aug 02, 2018
```
paths
```
  d123c0c6
Aug 01, 2018
- deal with desugared bundle bridge (#33) · b586d677
  Henry Cook authored Jul 31, 2018
  
  b586d677
Jul 28, 2018
- ClockCrossingType: fix bad merge (#32) · 1496b1bb
  Henry Cook authored Jul 27, 2018
  
  1496b1bb
- crossinghelper: minimal compliance with new API (#31) · 0d173dca
  Henry Cook authored Jul 27, 2018
  
  0d173dca
Jul 06, 2018
- Merge pull request #30 from sifive/fix-legacy · 650b45db
  Wesley W. Terpstra authored Jul 06, 2018
```
VC707: fix legacy Shell
```
  650b45db
- vc707: fix legacy PCIe clock constraint · 964e810c
  Wesley W. Terpstra authored Jul 05, 2018
  
  964e810c
- vc707: fix old shell IO constraints · 6104eda6
  Wesley W. Terpstra authored Jul 05, 2018
```
The hierarchy was changed by rocket-chip
```
  6104eda6
- vc707shell: fix old shell tcl hooks · c0d24c07
  Wesley W. Terpstra authored Jul 05, 2018
```
We need to add these legacy TCL scripts as resource files, not invoke them.
```
  c0d24c07
- Merge pull request #28 from sifive/shell-design-split · 52556662
  Wesley W. Terpstra authored Jul 05, 2018
```
Shell-Design Split
```
  52556662
- libero: adjust to rocket-chip path changes · e6f53b49
  Wesley W. Terpstra authored Jul 05, 2018
  
  e6f53b49
Jul 04, 2018
- Make 2.12 type checker happy (#29) · 3f453188
  Jack Koenig authored Jul 03, 2018
  
  3f453188
Jul 01, 2018
- shell: fix-up reset to the point IOFGPA works · 63e09049
  Wesley W. Terpstra authored Jun 29, 2018
  
  63e09049
Jun 30, 2018
- VC707Shell: make old-style constraints conditional on old shell · e0b9c286
  Wesley W. Terpstra authored Jun 24, 2018
  
  e0b9c286
- chiplink: allow enough margin for 200MHz on Xilinx · 83a1ee04
  Wesley W. Terpstra authored Jun 24, 2018
  
  83a1ee04
- shell: refactor sdc/xdc generation · d42ec602
  Wesley W. Terpstra authored Jun 22, 2018
  
  d42ec602
- shell: refactor the code into smaller pieces · fa9a15eb
  Wesley W. Terpstra authored Jun 20, 2018
  
  fa9a15eb
Jun 21, 2018
- shell: leverage new chisel3 programmatic IO API · 3d560822
  Wesley W. Terpstra authored Jun 15, 2018
  
  3d560822
- shell: split the top-level shell from the contained design · f04e70bd
  Wesley W. Terpstra authored Jun 04, 2018
  
  f04e70bd
- clocks: add diplomatic PLL + clock infrastructure · f2b8965e
  Wesley W. Terpstra authored Jun 08, 2018
  
  f2b8965e
Jun 20, 2018
- prologue.tcl: load tcl files in alphabetical order · 10875365
  Wesley W. Terpstra authored Jun 14, 2018
  
  10875365
- xilinx MMCM: add TCL to confirm PLL outputs are within range · 37e07d41
  Wesley W. Terpstra authored Jun 15, 2018
  
  37e07d41
- xilinx ip: make the crossing type configurable · 4851f7b2
  Wesley W. Terpstra authored Jun 15, 2018
  
  4851f7b2
- IBUFDS: blackbox uses Clock · 442c69f0
  Wesley W. Terpstra authored Jun 20, 2018
  
  442c69f0
Jun 12, 2018
- xilinx: add IBUF primitive · c948fd41
  Wesley W. Terpstra authored Jun 11, 2018
  
  c948fd41
Jun 11, 2018
- xilinxvc707pciex1: set clock+reset inside the island · 41285f54
  Wesley W. Terpstra authored Jun 11, 2018
  
  41285f54
Jun 08, 2018
- Merge pull request #27 from sifive/bump-apis · fba94960
  Wesley W. Terpstra authored Jun 08, 2018
```
Make MIG clocking internal and clean-up MMCM code style
```
  fba94960
- mig: shove Island clock internally · 62b632db
  Wesley W. Terpstra authored Jun 04, 2018
  
  62b632db
- Xilinx MMCM: beautify the scala code · 4abb5bd6
  Wesley W. Terpstra authored Jun 08, 2018
  
  4abb5bd6