Revert "Fpga spi speedup"

This reverts commit 9eb56625.

* spi related changes

* fpga timing related fixes

* added defaulSampleDel as the default sync stage delay.

* updatd the review

Renamed arty-a7-100 to arty_a7_100. 

Added arty-a7-100 board

VCU118 PCIe gen3 x4 + x8

This reverts commit 7d09b423.

The 1.8V power rail bounces during power-up. Try to reduce that.

This is needed to pass the empty string.

Shell Design Refactoring Enhancements