* SDIO: Refactor overlay classes to be more generic for SPI IO

* Update shells to use new SDIO/SPI classes

* Rename SDIOOverlay.scala -> SPIOverlay.scala

add clock divider support

refactor tcl code that wasn't executing correctly

CI: add a scala compilation check

rocket-chip already pulls in newer versions of these.

This fixes up a bunch of wake 0.18 issues.

fix bscan again

Use the :<> operator instead.

This is necessary to support PCIe controllers without access to physical
addresses below 4GiB. The kernel appears to happily map even 32-bit device
BARs to high 64-bit base-addresses for the RC BARs.

Add padPlace: LazyScope value

Renamed from "padPlace" to "sinkScope"

background: At the request of the physical implementation & design team,
            we needed a space to put the pad in one place.
            So I created a value called sinkScope.
            sinkScope default value is shell.

Add def sinkScope: LazyScope = shell in IOPlacedOverlay trait

Changed the existing sink scope from shell to sinkScope.
     in GPIOPlacedOverlay, I2CPlacedOverlay, JTAGDebugPlacedOverlay,
        PWMPlacedOverlay, SPIFlashPlacedOverlay, UARTPlacedOverlay

background: At the request of the physical implementation & design team,
 	    we needed a space to put the pad in one place.
	    So I created a value called padPlace.
            padPlace default value is shell.

Add def padPlace: LazyScope = shell in IOPlacedOverlay trait

Changed the existing sink scope from shell to padPlace.
  in GPIOPlacedOverlay, I2CPlacedOverlay, JTAGDebugPlacedOverlay,
     PWMPlacedOverlay, SPIFlashPlacedOverlay, UARTPlacedOverlay

wake: add variable for package location

Locate IO srst_n to proper pin on LCD connector

add tcl script to only do synth.tcl

bug fix for #103

port bscan to chisel3

move cjtag to vcu118 fmc

cjtag on vcu118

separate baremetal shell and linux shell

IntSyncCrossingSink -> IntSyncAsyncCrossingSink