Commits · 9e71feabda900fbbebdfe7a1e2c95cd0acd8eb8a · github.com / Phantom1003 / fpga-shells

Jul 26, 2018
- Revert "VCU1189 pins updated" · 9e71feab
  Sagar Karandikar authored Jul 25, 2018
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This reverts commit 0cc695c0.
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  9e71feab
- Merge branch 'new-shell-uart' of https://github.com/sifive/fpga-shells into new-shell-uart · 7888f334
  Sagar Karandikar authored Jul 25, 2018
  
  7888f334
- some cleanup · 8bb12801
  Sagar Karandikar authored Jul 25, 2018
  
  8bb12801
- VCU1189 pins updated · 0cc695c0
  Behzad Boroujerdian authored Jul 25, 2018
  
  0cc695c0
Jul 25, 2018
- fix board pin name · f8f7b3df
  Sagar Karandikar authored Jul 24, 2018
  
  f8f7b3df
- vcu118 pins wip · 311f46ad
  Sagar Karandikar authored Jul 24, 2018
  
  311f46ad
- VCU118NewShell that builds · 205bb962
  Sagar Karandikar authored Jul 24, 2018
  
  205bb962
- start VCU118NewShell, copy of VC707NewShell · 4286507c
  Sagar Karandikar authored Jul 24, 2018
  
  4286507c
Jul 23, 2018
- wip jtag · 5b2ddf59
  Sagar Karandikar authored Jul 22, 2018
  
  5b2ddf59
Jul 21, 2018
- wip fix uart clock in shell · 59d74cd9
  Sagar Karandikar authored Jul 20, 2018
  
  59d74cd9
Jul 19, 2018
- fix comment · 71b4669c
  Sagar Karandikar authored Jul 18, 2018
  
  71b4669c
- take SPIParams from the Design in SDIOOverlay · 1cdc02f0
  Sagar Karandikar authored Jul 18, 2018
  
  1cdc02f0
- take UARTParams from the Design in UARTOverlay · ae62b238
  Sagar Karandikar authored Jul 18, 2018
  
  ae62b238
Jul 18, 2018
- need to use get_ports only in some cases · a01c03d5
  Sagar Karandikar authored Jul 17, 2018
  
  a01c03d5
- spi/sdio constraints · 679c2784
  Sagar Karandikar authored Jul 17, 2018
  
  679c2784
- first pass SDIOOverlay · 865dea13
  Sagar Karandikar authored Jul 17, 2018
  
  865dea13
- cleanup uartoverlay · 77aadbb8
  Sagar Karandikar authored Jul 17, 2018
  
  77aadbb8
Jul 17, 2018
- more wip · bd7adeec
  Sagar Karandikar authored Jul 16, 2018
  
  bd7adeec
- wip · ff7fc94a
  Sagar Karandikar authored Jul 16, 2018
  
  ff7fc94a
Jul 13, 2018
- UARTOverlay: add missing SyncResetSynchronizerShiftReg for VC707 · 61a01e20
  Sagar Karandikar authored Jul 12, 2018
  
  61a01e20
- UARTOverlay for new shell · 50b0236e
  Sagar Karandikar authored Jul 12, 2018
  
  50b0236e
Jul 06, 2018
- Merge pull request #30 from sifive/fix-legacy · 650b45db
  Wesley W. Terpstra authored Jul 06, 2018
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VC707: fix legacy Shell
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  650b45db
- vc707: fix legacy PCIe clock constraint · 964e810c
  Wesley W. Terpstra authored Jul 05, 2018
  
  964e810c
- vc707: fix old shell IO constraints · 6104eda6
  Wesley W. Terpstra authored Jul 05, 2018
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The hierarchy was changed by rocket-chip
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  6104eda6
- vc707shell: fix old shell tcl hooks · c0d24c07
  Wesley W. Terpstra authored Jul 05, 2018
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We need to add these legacy TCL scripts as resource files, not invoke them.
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  c0d24c07
- Merge pull request #28 from sifive/shell-design-split · 52556662
  Wesley W. Terpstra authored Jul 05, 2018
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Shell-Design Split
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  52556662
- libero: adjust to rocket-chip path changes · e6f53b49
  Wesley W. Terpstra authored Jul 05, 2018
  
  e6f53b49
Jul 04, 2018
- Make 2.12 type checker happy (#29) · 3f453188
  Jack Koenig authored Jul 03, 2018
  
  3f453188
Jul 01, 2018
- shell: fix-up reset to the point IOFGPA works · 63e09049
  Wesley W. Terpstra authored Jun 29, 2018
  
  63e09049
Jun 30, 2018
- VC707Shell: make old-style constraints conditional on old shell · e0b9c286
  Wesley W. Terpstra authored Jun 24, 2018
  
  e0b9c286
- chiplink: allow enough margin for 200MHz on Xilinx · 83a1ee04
  Wesley W. Terpstra authored Jun 24, 2018
  
  83a1ee04
- shell: refactor sdc/xdc generation · d42ec602
  Wesley W. Terpstra authored Jun 22, 2018
  
  d42ec602
- shell: refactor the code into smaller pieces · fa9a15eb
  Wesley W. Terpstra authored Jun 20, 2018
  
  fa9a15eb
Jun 21, 2018
- shell: leverage new chisel3 programmatic IO API · 3d560822
  Wesley W. Terpstra authored Jun 15, 2018
  
  3d560822
- shell: split the top-level shell from the contained design · f04e70bd
  Wesley W. Terpstra authored Jun 04, 2018
  
  f04e70bd
- clocks: add diplomatic PLL + clock infrastructure · f2b8965e
  Wesley W. Terpstra authored Jun 08, 2018
  
  f2b8965e
Jun 20, 2018
- prologue.tcl: load tcl files in alphabetical order · 10875365
  Wesley W. Terpstra authored Jun 14, 2018
  
  10875365
- xilinx MMCM: add TCL to confirm PLL outputs are within range · 37e07d41
  Wesley W. Terpstra authored Jun 15, 2018
  
  37e07d41
- xilinx ip: make the crossing type configurable · 4851f7b2
  Wesley W. Terpstra authored Jun 15, 2018
  
  4851f7b2
- IBUFDS: blackbox uses Clock · 442c69f0
  Wesley W. Terpstra authored Jun 20, 2018
  
  442c69f0