Skip to content
GitLab
Commit 240cb6e8 authored by Michael Geszkiewicz's avatar Michael Geszkiewicz
Browse files

lbp16: remove reading registers from space 4 in verbose mode becouse it will... 


lbp16: remove reading registers from space 4 in verbose mode becouse it will cause start up DPLL on FPGA
show error flags register on space 6 in verbose

Signed-off-by: default avatarMichael Geszkiewicz <micges@wp.pl>
parent f35164e2
Hide whitespace changes
Inline Side-by-side
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment