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core/stdarch/crates/core_arch/src/aarch64/neon/
generated.rs

1// This code is automatically generated. DO NOT MODIFY.
2//
3// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file:
4//
5// ```
6// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
7// ```
8#![allow(improper_ctypes)]
9
10#[cfg(test)]
11use stdarch_test::assert_instr;
12
13use super::*;
14
15#[doc = "CRC32-C single round checksum for quad words (64 bits)."]
16#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
17#[inline]
18#[target_feature(enable = "crc")]
19#[cfg_attr(test, assert_instr(crc32cx))]
20#[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
21pub fn __crc32cd(crc: u32, data: u64) -> u32 {
22    unsafe extern "unadjusted" {
23        #[cfg_attr(
24            any(target_arch = "aarch64", target_arch = "arm64ec"),
25            link_name = "llvm.aarch64.crc32cx"
26        )]
27        fn ___crc32cd(crc: u32, data: u64) -> u32;
28    }
29    unsafe { ___crc32cd(crc, data) }
30}
31#[doc = "CRC32 single round checksum for quad words (64 bits)."]
32#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
33#[inline]
34#[target_feature(enable = "crc")]
35#[cfg_attr(test, assert_instr(crc32x))]
36#[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
37pub fn __crc32d(crc: u32, data: u64) -> u32 {
38    unsafe extern "unadjusted" {
39        #[cfg_attr(
40            any(target_arch = "aarch64", target_arch = "arm64ec"),
41            link_name = "llvm.aarch64.crc32x"
42        )]
43        fn ___crc32d(crc: u32, data: u64) -> u32;
44    }
45    unsafe { ___crc32d(crc, data) }
46}
47#[doc = "Floating-point JavaScript convert to signed fixed-point, rounding toward zero"]
48#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__jcvt)"]
49#[inline]
50#[target_feature(enable = "jsconv")]
51#[cfg_attr(test, assert_instr(fjcvtzs))]
52#[stable(feature = "stdarch_aarch64_jscvt", since = "1.95.0")]
53pub fn __jcvt(a: f64) -> i32 {
54    unsafe extern "unadjusted" {
55        #[cfg_attr(
56            any(target_arch = "aarch64", target_arch = "arm64ec"),
57            link_name = "llvm.aarch64.fjcvtzs"
58        )]
59        fn ___jcvt(a: f64) -> i32;
60    }
61    unsafe { ___jcvt(a) }
62}
63#[doc = "Signed Absolute difference and Accumulate Long"]
64#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8)"]
65#[inline]
66#[target_feature(enable = "neon")]
67#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68#[cfg_attr(
69    all(test, not(target_env = "msvc"), target_endian = "little"),
70    assert_instr(sabal2)
71)]
72pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
73    let d = vget_high_s8(b);
74    let e = vget_high_s8(c);
75    let f = vabd_s8(d, e);
76    unsafe {
77        let f: uint8x8_t = simd_cast(f);
78        simd_add(a, simd_cast(f))
79    }
80}
81#[doc = "Signed Absolute difference and Accumulate Long"]
82#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)"]
83#[inline]
84#[target_feature(enable = "neon")]
85#[stable(feature = "neon_intrinsics", since = "1.59.0")]
86#[cfg_attr(
87    all(test, not(target_env = "msvc"), target_endian = "little"),
88    assert_instr(sabal2)
89)]
90pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
91    let d = vget_high_s16(b);
92    let e = vget_high_s16(c);
93    let f = vabd_s16(d, e);
94    unsafe {
95        let f: uint16x4_t = simd_cast(f);
96        simd_add(a, simd_cast(f))
97    }
98}
99#[doc = "Signed Absolute difference and Accumulate Long"]
100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)"]
101#[inline]
102#[target_feature(enable = "neon")]
103#[stable(feature = "neon_intrinsics", since = "1.59.0")]
104#[cfg_attr(
105    all(test, not(target_env = "msvc"), target_endian = "little"),
106    assert_instr(sabal2)
107)]
108pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
109    let d = vget_high_s32(b);
110    let e = vget_high_s32(c);
111    let f = vabd_s32(d, e);
112    unsafe {
113        let f: uint32x2_t = simd_cast(f);
114        simd_add(a, simd_cast(f))
115    }
116}
117#[doc = "Unsigned Absolute difference and Accumulate Long"]
118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)"]
119#[inline]
120#[target_feature(enable = "neon")]
121#[stable(feature = "neon_intrinsics", since = "1.59.0")]
122#[cfg_attr(
123    all(test, not(target_env = "msvc"), target_endian = "little"),
124    assert_instr(uabal2)
125)]
126pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
127    let d = vget_high_u8(b);
128    let e = vget_high_u8(c);
129    let f = vabd_u8(d, e);
130    unsafe { simd_add(a, simd_cast(f)) }
131}
132#[doc = "Unsigned Absolute difference and Accumulate Long"]
133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"]
134#[inline]
135#[target_feature(enable = "neon")]
136#[stable(feature = "neon_intrinsics", since = "1.59.0")]
137#[cfg_attr(
138    all(test, not(target_env = "msvc"), target_endian = "little"),
139    assert_instr(uabal2)
140)]
141pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
142    let d = vget_high_u16(b);
143    let e = vget_high_u16(c);
144    let f = vabd_u16(d, e);
145    unsafe { simd_add(a, simd_cast(f)) }
146}
147#[doc = "Unsigned Absolute difference and Accumulate Long"]
148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"]
149#[inline]
150#[target_feature(enable = "neon")]
151#[stable(feature = "neon_intrinsics", since = "1.59.0")]
152#[cfg_attr(
153    all(test, not(target_env = "msvc"), target_endian = "little"),
154    assert_instr(uabal2)
155)]
156pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
157    let d = vget_high_u32(b);
158    let e = vget_high_u32(c);
159    let f = vabd_u32(d, e);
160    unsafe { simd_add(a, simd_cast(f)) }
161}
162#[doc = "Absolute difference between the arguments of Floating"]
163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"]
164#[inline]
165#[target_feature(enable = "neon")]
166#[stable(feature = "neon_intrinsics", since = "1.59.0")]
167#[cfg_attr(test, assert_instr(fabd))]
168pub fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
169    unsafe extern "unadjusted" {
170        #[cfg_attr(
171            any(target_arch = "aarch64", target_arch = "arm64ec"),
172            link_name = "llvm.aarch64.neon.fabd.v1f64"
173        )]
174        fn _vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
175    }
176    unsafe { _vabd_f64(a, b) }
177}
178#[doc = "Absolute difference between the arguments of Floating"]
179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)"]
180#[inline]
181#[target_feature(enable = "neon")]
182#[stable(feature = "neon_intrinsics", since = "1.59.0")]
183#[cfg_attr(test, assert_instr(fabd))]
184pub fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
185    unsafe extern "unadjusted" {
186        #[cfg_attr(
187            any(target_arch = "aarch64", target_arch = "arm64ec"),
188            link_name = "llvm.aarch64.neon.fabd.v2f64"
189        )]
190        fn _vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
191    }
192    unsafe { _vabdq_f64(a, b) }
193}
194#[doc = "Floating-point absolute difference"]
195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64)"]
196#[inline]
197#[target_feature(enable = "neon")]
198#[stable(feature = "neon_intrinsics", since = "1.59.0")]
199#[cfg_attr(test, assert_instr(fabd))]
200pub fn vabdd_f64(a: f64, b: f64) -> f64 {
201    vget_lane_f64::<0>(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)))
202}
203#[doc = "Floating-point absolute difference"]
204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"]
205#[inline]
206#[target_feature(enable = "neon")]
207#[stable(feature = "neon_intrinsics", since = "1.59.0")]
208#[cfg_attr(test, assert_instr(fabd))]
209pub fn vabds_f32(a: f32, b: f32) -> f32 {
210    vget_lane_f32::<0>(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)))
211}
212#[doc = "Floating-point absolute difference"]
213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdh_f16)"]
214#[inline]
215#[target_feature(enable = "neon,fp16")]
216#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
217#[cfg(not(target_arch = "arm64ec"))]
218#[cfg_attr(test, assert_instr(fabd))]
219pub fn vabdh_f16(a: f16, b: f16) -> f16 {
220    vget_lane_f16::<0>(vabd_f16(vdup_n_f16(a), vdup_n_f16(b)))
221}
222#[doc = "Signed Absolute difference Long"]
223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"]
224#[inline]
225#[target_feature(enable = "neon")]
226#[stable(feature = "neon_intrinsics", since = "1.59.0")]
227#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
228pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
229    let c = vget_high_s8(a);
230    let d = vget_high_s8(b);
231    unsafe {
232        let e: uint8x8_t = simd_cast(vabd_s8(c, d));
233        simd_cast(e)
234    }
235}
236#[doc = "Signed Absolute difference Long"]
237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"]
238#[inline]
239#[target_feature(enable = "neon")]
240#[stable(feature = "neon_intrinsics", since = "1.59.0")]
241#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
242pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
243    let c = vget_high_s16(a);
244    let d = vget_high_s16(b);
245    unsafe {
246        let e: uint16x4_t = simd_cast(vabd_s16(c, d));
247        simd_cast(e)
248    }
249}
250#[doc = "Signed Absolute difference Long"]
251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"]
252#[inline]
253#[target_feature(enable = "neon")]
254#[stable(feature = "neon_intrinsics", since = "1.59.0")]
255#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
256pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
257    let c = vget_high_s32(a);
258    let d = vget_high_s32(b);
259    unsafe {
260        let e: uint32x2_t = simd_cast(vabd_s32(c, d));
261        simd_cast(e)
262    }
263}
264#[doc = "Unsigned Absolute difference Long"]
265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
266#[inline]
267#[target_feature(enable = "neon")]
268#[stable(feature = "neon_intrinsics", since = "1.59.0")]
269#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
270pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
271    let c = vget_high_u8(a);
272    let d = vget_high_u8(b);
273    unsafe { simd_cast(vabd_u8(c, d)) }
274}
275#[doc = "Unsigned Absolute difference Long"]
276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
277#[inline]
278#[target_feature(enable = "neon")]
279#[stable(feature = "neon_intrinsics", since = "1.59.0")]
280#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
281pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
282    let c = vget_high_u16(a);
283    let d = vget_high_u16(b);
284    unsafe { simd_cast(vabd_u16(c, d)) }
285}
286#[doc = "Unsigned Absolute difference Long"]
287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
288#[inline]
289#[target_feature(enable = "neon")]
290#[stable(feature = "neon_intrinsics", since = "1.59.0")]
291#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
292pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
293    let c = vget_high_u32(a);
294    let d = vget_high_u32(b);
295    unsafe { simd_cast(vabd_u32(c, d)) }
296}
297#[doc = "Floating-point absolute value"]
298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"]
299#[inline]
300#[target_feature(enable = "neon")]
301#[cfg_attr(test, assert_instr(fabs))]
302#[stable(feature = "neon_intrinsics", since = "1.59.0")]
303pub fn vabs_f64(a: float64x1_t) -> float64x1_t {
304    unsafe { simd_fabs(a) }
305}
306#[doc = "Floating-point absolute value"]
307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)"]
308#[inline]
309#[target_feature(enable = "neon")]
310#[cfg_attr(test, assert_instr(fabs))]
311#[stable(feature = "neon_intrinsics", since = "1.59.0")]
312pub fn vabsq_f64(a: float64x2_t) -> float64x2_t {
313    unsafe { simd_fabs(a) }
314}
315#[doc = "Absolute Value (wrapping)."]
316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s64)"]
317#[inline]
318#[target_feature(enable = "neon")]
319#[stable(feature = "neon_intrinsics", since = "1.59.0")]
320#[cfg_attr(test, assert_instr(abs))]
321pub fn vabs_s64(a: int64x1_t) -> int64x1_t {
322    unsafe {
323        let neg: int64x1_t = simd_neg(a);
324        let mask: int64x1_t = simd_ge(a, neg);
325        simd_select(mask, a, neg)
326    }
327}
328#[doc = "Absolute Value (wrapping)."]
329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)"]
330#[inline]
331#[target_feature(enable = "neon")]
332#[stable(feature = "neon_intrinsics", since = "1.59.0")]
333#[cfg_attr(test, assert_instr(abs))]
334pub fn vabsq_s64(a: int64x2_t) -> int64x2_t {
335    unsafe {
336        let neg: int64x2_t = simd_neg(a);
337        let mask: int64x2_t = simd_ge(a, neg);
338        simd_select(mask, a, neg)
339    }
340}
341#[doc = "Absolute Value (wrapping)."]
342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsd_s64)"]
343#[inline]
344#[target_feature(enable = "neon")]
345#[stable(feature = "neon_intrinsics", since = "1.59.0")]
346#[cfg_attr(test, assert_instr(abs))]
347pub fn vabsd_s64(a: i64) -> i64 {
348    unsafe extern "unadjusted" {
349        #[cfg_attr(
350            any(target_arch = "aarch64", target_arch = "arm64ec"),
351            link_name = "llvm.aarch64.neon.abs.i64"
352        )]
353        fn _vabsd_s64(a: i64) -> i64;
354    }
355    unsafe { _vabsd_s64(a) }
356}
357#[doc = "Add"]
358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"]
359#[inline]
360#[target_feature(enable = "neon")]
361#[stable(feature = "neon_intrinsics", since = "1.59.0")]
362#[cfg_attr(test, assert_instr(nop))]
363pub fn vaddd_s64(a: i64, b: i64) -> i64 {
364    a.wrapping_add(b)
365}
366#[doc = "Add"]
367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64)"]
368#[inline]
369#[target_feature(enable = "neon")]
370#[stable(feature = "neon_intrinsics", since = "1.59.0")]
371#[cfg_attr(test, assert_instr(nop))]
372pub fn vaddd_u64(a: u64, b: u64) -> u64 {
373    a.wrapping_add(b)
374}
375#[doc = "Signed Add Long across Vector"]
376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)"]
377#[inline]
378#[target_feature(enable = "neon")]
379#[stable(feature = "neon_intrinsics", since = "1.59.0")]
380#[cfg_attr(test, assert_instr(saddlv))]
381pub fn vaddlv_s16(a: int16x4_t) -> i32 {
382    unsafe extern "unadjusted" {
383        #[cfg_attr(
384            any(target_arch = "aarch64", target_arch = "arm64ec"),
385            link_name = "llvm.aarch64.neon.saddlv.i32.v4i16"
386        )]
387        fn _vaddlv_s16(a: int16x4_t) -> i32;
388    }
389    unsafe { _vaddlv_s16(a) }
390}
391#[doc = "Signed Add Long across Vector"]
392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)"]
393#[inline]
394#[target_feature(enable = "neon")]
395#[stable(feature = "neon_intrinsics", since = "1.59.0")]
396#[cfg_attr(test, assert_instr(saddlv))]
397pub fn vaddlvq_s16(a: int16x8_t) -> i32 {
398    unsafe extern "unadjusted" {
399        #[cfg_attr(
400            any(target_arch = "aarch64", target_arch = "arm64ec"),
401            link_name = "llvm.aarch64.neon.saddlv.i32.v8i16"
402        )]
403        fn _vaddlvq_s16(a: int16x8_t) -> i32;
404    }
405    unsafe { _vaddlvq_s16(a) }
406}
407#[doc = "Signed Add Long across Vector"]
408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)"]
409#[inline]
410#[target_feature(enable = "neon")]
411#[stable(feature = "neon_intrinsics", since = "1.59.0")]
412#[cfg_attr(test, assert_instr(saddlv))]
413pub fn vaddlvq_s32(a: int32x4_t) -> i64 {
414    unsafe extern "unadjusted" {
415        #[cfg_attr(
416            any(target_arch = "aarch64", target_arch = "arm64ec"),
417            link_name = "llvm.aarch64.neon.saddlv.i64.v4i32"
418        )]
419        fn _vaddlvq_s32(a: int32x4_t) -> i64;
420    }
421    unsafe { _vaddlvq_s32(a) }
422}
423#[doc = "Signed Add Long across Vector"]
424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32)"]
425#[inline]
426#[target_feature(enable = "neon")]
427#[stable(feature = "neon_intrinsics", since = "1.59.0")]
428#[cfg_attr(test, assert_instr(saddlp))]
429pub fn vaddlv_s32(a: int32x2_t) -> i64 {
430    unsafe extern "unadjusted" {
431        #[cfg_attr(
432            any(target_arch = "aarch64", target_arch = "arm64ec"),
433            link_name = "llvm.aarch64.neon.saddlv.i64.v2i32"
434        )]
435        fn _vaddlv_s32(a: int32x2_t) -> i64;
436    }
437    unsafe { _vaddlv_s32(a) }
438}
439#[doc = "Signed Add Long across Vector"]
440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s8)"]
441#[inline]
442#[target_feature(enable = "neon")]
443#[stable(feature = "neon_intrinsics", since = "1.59.0")]
444#[cfg_attr(test, assert_instr(saddlv))]
445pub fn vaddlv_s8(a: int8x8_t) -> i16 {
446    unsafe extern "unadjusted" {
447        #[cfg_attr(
448            any(target_arch = "aarch64", target_arch = "arm64ec"),
449            link_name = "llvm.aarch64.neon.saddlv.i32.v8i8"
450        )]
451        fn _vaddlv_s8(a: int8x8_t) -> i32;
452    }
453    unsafe { _vaddlv_s8(a) as i16 }
454}
455#[doc = "Signed Add Long across Vector"]
456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s8)"]
457#[inline]
458#[target_feature(enable = "neon")]
459#[stable(feature = "neon_intrinsics", since = "1.59.0")]
460#[cfg_attr(test, assert_instr(saddlv))]
461pub fn vaddlvq_s8(a: int8x16_t) -> i16 {
462    unsafe extern "unadjusted" {
463        #[cfg_attr(
464            any(target_arch = "aarch64", target_arch = "arm64ec"),
465            link_name = "llvm.aarch64.neon.saddlv.i32.v16i8"
466        )]
467        fn _vaddlvq_s8(a: int8x16_t) -> i32;
468    }
469    unsafe { _vaddlvq_s8(a) as i16 }
470}
471#[doc = "Unsigned Add Long across Vector"]
472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)"]
473#[inline]
474#[target_feature(enable = "neon")]
475#[stable(feature = "neon_intrinsics", since = "1.59.0")]
476#[cfg_attr(test, assert_instr(uaddlv))]
477pub fn vaddlv_u16(a: uint16x4_t) -> u32 {
478    unsafe extern "unadjusted" {
479        #[cfg_attr(
480            any(target_arch = "aarch64", target_arch = "arm64ec"),
481            link_name = "llvm.aarch64.neon.uaddlv.i32.v4i16"
482        )]
483        fn _vaddlv_u16(a: uint16x4_t) -> u32;
484    }
485    unsafe { _vaddlv_u16(a) }
486}
487#[doc = "Unsigned Add Long across Vector"]
488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)"]
489#[inline]
490#[target_feature(enable = "neon")]
491#[stable(feature = "neon_intrinsics", since = "1.59.0")]
492#[cfg_attr(test, assert_instr(uaddlv))]
493pub fn vaddlvq_u16(a: uint16x8_t) -> u32 {
494    unsafe extern "unadjusted" {
495        #[cfg_attr(
496            any(target_arch = "aarch64", target_arch = "arm64ec"),
497            link_name = "llvm.aarch64.neon.uaddlv.i32.v8i16"
498        )]
499        fn _vaddlvq_u16(a: uint16x8_t) -> u32;
500    }
501    unsafe { _vaddlvq_u16(a) }
502}
503#[doc = "Unsigned Add Long across Vector"]
504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)"]
505#[inline]
506#[target_feature(enable = "neon")]
507#[stable(feature = "neon_intrinsics", since = "1.59.0")]
508#[cfg_attr(test, assert_instr(uaddlv))]
509pub fn vaddlvq_u32(a: uint32x4_t) -> u64 {
510    unsafe extern "unadjusted" {
511        #[cfg_attr(
512            any(target_arch = "aarch64", target_arch = "arm64ec"),
513            link_name = "llvm.aarch64.neon.uaddlv.i64.v4i32"
514        )]
515        fn _vaddlvq_u32(a: uint32x4_t) -> u64;
516    }
517    unsafe { _vaddlvq_u32(a) }
518}
519#[doc = "Unsigned Add Long across Vector"]
520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32)"]
521#[inline]
522#[target_feature(enable = "neon")]
523#[stable(feature = "neon_intrinsics", since = "1.59.0")]
524#[cfg_attr(test, assert_instr(uaddlp))]
525pub fn vaddlv_u32(a: uint32x2_t) -> u64 {
526    unsafe extern "unadjusted" {
527        #[cfg_attr(
528            any(target_arch = "aarch64", target_arch = "arm64ec"),
529            link_name = "llvm.aarch64.neon.uaddlv.i64.v2i32"
530        )]
531        fn _vaddlv_u32(a: uint32x2_t) -> u64;
532    }
533    unsafe { _vaddlv_u32(a) }
534}
535#[doc = "Unsigned Add Long across Vector"]
536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u8)"]
537#[inline]
538#[target_feature(enable = "neon")]
539#[stable(feature = "neon_intrinsics", since = "1.59.0")]
540#[cfg_attr(test, assert_instr(uaddlv))]
541pub fn vaddlv_u8(a: uint8x8_t) -> u16 {
542    unsafe extern "unadjusted" {
543        #[cfg_attr(
544            any(target_arch = "aarch64", target_arch = "arm64ec"),
545            link_name = "llvm.aarch64.neon.uaddlv.i32.v8i8"
546        )]
547        fn _vaddlv_u8(a: uint8x8_t) -> i32;
548    }
549    unsafe { _vaddlv_u8(a) as u16 }
550}
551#[doc = "Unsigned Add Long across Vector"]
552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u8)"]
553#[inline]
554#[target_feature(enable = "neon")]
555#[stable(feature = "neon_intrinsics", since = "1.59.0")]
556#[cfg_attr(test, assert_instr(uaddlv))]
557pub fn vaddlvq_u8(a: uint8x16_t) -> u16 {
558    unsafe extern "unadjusted" {
559        #[cfg_attr(
560            any(target_arch = "aarch64", target_arch = "arm64ec"),
561            link_name = "llvm.aarch64.neon.uaddlv.i32.v16i8"
562        )]
563        fn _vaddlvq_u8(a: uint8x16_t) -> i32;
564    }
565    unsafe { _vaddlvq_u8(a) as u16 }
566}
567#[doc = "Floating-point add across vector"]
568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32)"]
569#[inline]
570#[target_feature(enable = "neon")]
571#[stable(feature = "neon_intrinsics", since = "1.59.0")]
572#[cfg_attr(test, assert_instr(faddp))]
573pub fn vaddv_f32(a: float32x2_t) -> f32 {
574    unsafe extern "unadjusted" {
575        #[cfg_attr(
576            any(target_arch = "aarch64", target_arch = "arm64ec"),
577            link_name = "llvm.aarch64.neon.faddv.f32.v2f32"
578        )]
579        fn _vaddv_f32(a: float32x2_t) -> f32;
580    }
581    unsafe { _vaddv_f32(a) }
582}
583#[doc = "Floating-point add across vector"]
584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32)"]
585#[inline]
586#[target_feature(enable = "neon")]
587#[stable(feature = "neon_intrinsics", since = "1.59.0")]
588#[cfg_attr(test, assert_instr(faddp))]
589pub fn vaddvq_f32(a: float32x4_t) -> f32 {
590    unsafe extern "unadjusted" {
591        #[cfg_attr(
592            any(target_arch = "aarch64", target_arch = "arm64ec"),
593            link_name = "llvm.aarch64.neon.faddv.f32.v4f32"
594        )]
595        fn _vaddvq_f32(a: float32x4_t) -> f32;
596    }
597    unsafe { _vaddvq_f32(a) }
598}
599#[doc = "Floating-point add across vector"]
600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64)"]
601#[inline]
602#[target_feature(enable = "neon")]
603#[stable(feature = "neon_intrinsics", since = "1.59.0")]
604#[cfg_attr(test, assert_instr(faddp))]
605pub fn vaddvq_f64(a: float64x2_t) -> f64 {
606    unsafe extern "unadjusted" {
607        #[cfg_attr(
608            any(target_arch = "aarch64", target_arch = "arm64ec"),
609            link_name = "llvm.aarch64.neon.faddv.f64.v2f64"
610        )]
611        fn _vaddvq_f64(a: float64x2_t) -> f64;
612    }
613    unsafe { _vaddvq_f64(a) }
614}
615#[doc = "Add across vector"]
616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s32)"]
617#[inline]
618#[target_feature(enable = "neon")]
619#[stable(feature = "neon_intrinsics", since = "1.59.0")]
620#[cfg_attr(test, assert_instr(addp))]
621pub fn vaddv_s32(a: int32x2_t) -> i32 {
622    unsafe { simd_reduce_add_ordered(a, 0) }
623}
624#[doc = "Add across vector"]
625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)"]
626#[inline]
627#[target_feature(enable = "neon")]
628#[stable(feature = "neon_intrinsics", since = "1.59.0")]
629#[cfg_attr(test, assert_instr(addv))]
630pub fn vaddv_s8(a: int8x8_t) -> i8 {
631    unsafe { simd_reduce_add_ordered(a, 0) }
632}
633#[doc = "Add across vector"]
634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)"]
635#[inline]
636#[target_feature(enable = "neon")]
637#[stable(feature = "neon_intrinsics", since = "1.59.0")]
638#[cfg_attr(test, assert_instr(addv))]
639pub fn vaddvq_s8(a: int8x16_t) -> i8 {
640    unsafe { simd_reduce_add_ordered(a, 0) }
641}
642#[doc = "Add across vector"]
643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)"]
644#[inline]
645#[target_feature(enable = "neon")]
646#[stable(feature = "neon_intrinsics", since = "1.59.0")]
647#[cfg_attr(test, assert_instr(addv))]
648pub fn vaddv_s16(a: int16x4_t) -> i16 {
649    unsafe { simd_reduce_add_ordered(a, 0) }
650}
651#[doc = "Add across vector"]
652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)"]
653#[inline]
654#[target_feature(enable = "neon")]
655#[stable(feature = "neon_intrinsics", since = "1.59.0")]
656#[cfg_attr(test, assert_instr(addv))]
657pub fn vaddvq_s16(a: int16x8_t) -> i16 {
658    unsafe { simd_reduce_add_ordered(a, 0) }
659}
660#[doc = "Add across vector"]
661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)"]
662#[inline]
663#[target_feature(enable = "neon")]
664#[stable(feature = "neon_intrinsics", since = "1.59.0")]
665#[cfg_attr(test, assert_instr(addv))]
666pub fn vaddvq_s32(a: int32x4_t) -> i32 {
667    unsafe { simd_reduce_add_ordered(a, 0) }
668}
669#[doc = "Add across vector"]
670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u32)"]
671#[inline]
672#[target_feature(enable = "neon")]
673#[stable(feature = "neon_intrinsics", since = "1.59.0")]
674#[cfg_attr(test, assert_instr(addp))]
675pub fn vaddv_u32(a: uint32x2_t) -> u32 {
676    unsafe { simd_reduce_add_ordered(a, 0) }
677}
678#[doc = "Add across vector"]
679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)"]
680#[inline]
681#[target_feature(enable = "neon")]
682#[stable(feature = "neon_intrinsics", since = "1.59.0")]
683#[cfg_attr(test, assert_instr(addv))]
684pub fn vaddv_u8(a: uint8x8_t) -> u8 {
685    unsafe { simd_reduce_add_ordered(a, 0) }
686}
687#[doc = "Add across vector"]
688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)"]
689#[inline]
690#[target_feature(enable = "neon")]
691#[stable(feature = "neon_intrinsics", since = "1.59.0")]
692#[cfg_attr(test, assert_instr(addv))]
693pub fn vaddvq_u8(a: uint8x16_t) -> u8 {
694    unsafe { simd_reduce_add_ordered(a, 0) }
695}
696#[doc = "Add across vector"]
697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)"]
698#[inline]
699#[target_feature(enable = "neon")]
700#[stable(feature = "neon_intrinsics", since = "1.59.0")]
701#[cfg_attr(test, assert_instr(addv))]
702pub fn vaddv_u16(a: uint16x4_t) -> u16 {
703    unsafe { simd_reduce_add_ordered(a, 0) }
704}
705#[doc = "Add across vector"]
706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)"]
707#[inline]
708#[target_feature(enable = "neon")]
709#[stable(feature = "neon_intrinsics", since = "1.59.0")]
710#[cfg_attr(test, assert_instr(addv))]
711pub fn vaddvq_u16(a: uint16x8_t) -> u16 {
712    unsafe { simd_reduce_add_ordered(a, 0) }
713}
714#[doc = "Add across vector"]
715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)"]
716#[inline]
717#[target_feature(enable = "neon")]
718#[stable(feature = "neon_intrinsics", since = "1.59.0")]
719#[cfg_attr(test, assert_instr(addv))]
720pub fn vaddvq_u32(a: uint32x4_t) -> u32 {
721    unsafe { simd_reduce_add_ordered(a, 0) }
722}
723#[doc = "Add across vector"]
724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s64)"]
725#[inline]
726#[target_feature(enable = "neon")]
727#[stable(feature = "neon_intrinsics", since = "1.59.0")]
728#[cfg_attr(test, assert_instr(addp))]
729pub fn vaddvq_s64(a: int64x2_t) -> i64 {
730    unsafe { simd_reduce_add_ordered(a, 0) }
731}
732#[doc = "Add across vector"]
733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u64)"]
734#[inline]
735#[target_feature(enable = "neon")]
736#[stable(feature = "neon_intrinsics", since = "1.59.0")]
737#[cfg_attr(test, assert_instr(addp))]
738pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
739    unsafe { simd_reduce_add_ordered(a, 0) }
740}
741#[doc = "Multi-vector floating-point absolute maximum"]
742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"]
743#[inline]
744#[target_feature(enable = "neon,faminmax")]
745#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
746#[unstable(feature = "faminmax", issue = "137933")]
747pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
748    unsafe extern "unadjusted" {
749        #[cfg_attr(
750            any(target_arch = "aarch64", target_arch = "arm64ec"),
751            link_name = "llvm.aarch64.neon.famax.v4f16"
752        )]
753        fn _vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
754    }
755    unsafe { _vamax_f16(a, b) }
756}
757#[doc = "Multi-vector floating-point absolute maximum"]
758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"]
759#[inline]
760#[target_feature(enable = "neon,faminmax")]
761#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
762#[unstable(feature = "faminmax", issue = "137933")]
763pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
764    unsafe extern "unadjusted" {
765        #[cfg_attr(
766            any(target_arch = "aarch64", target_arch = "arm64ec"),
767            link_name = "llvm.aarch64.neon.famax.v8f16"
768        )]
769        fn _vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
770    }
771    unsafe { _vamaxq_f16(a, b) }
772}
773#[doc = "Multi-vector floating-point absolute maximum"]
774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
775#[inline]
776#[target_feature(enable = "neon,faminmax")]
777#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
778#[unstable(feature = "faminmax", issue = "137933")]
779pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
780    unsafe extern "unadjusted" {
781        #[cfg_attr(
782            any(target_arch = "aarch64", target_arch = "arm64ec"),
783            link_name = "llvm.aarch64.neon.famax.v2f32"
784        )]
785        fn _vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
786    }
787    unsafe { _vamax_f32(a, b) }
788}
789#[doc = "Multi-vector floating-point absolute maximum"]
790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"]
791#[inline]
792#[target_feature(enable = "neon,faminmax")]
793#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
794#[unstable(feature = "faminmax", issue = "137933")]
795pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
796    unsafe extern "unadjusted" {
797        #[cfg_attr(
798            any(target_arch = "aarch64", target_arch = "arm64ec"),
799            link_name = "llvm.aarch64.neon.famax.v4f32"
800        )]
801        fn _vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
802    }
803    unsafe { _vamaxq_f32(a, b) }
804}
805#[doc = "Multi-vector floating-point absolute maximum"]
806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"]
807#[inline]
808#[target_feature(enable = "neon,faminmax")]
809#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
810#[unstable(feature = "faminmax", issue = "137933")]
811pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
812    unsafe extern "unadjusted" {
813        #[cfg_attr(
814            any(target_arch = "aarch64", target_arch = "arm64ec"),
815            link_name = "llvm.aarch64.neon.famax.v2f64"
816        )]
817        fn _vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
818    }
819    unsafe { _vamaxq_f64(a, b) }
820}
821#[doc = "Multi-vector floating-point absolute minimum"]
822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"]
823#[inline]
824#[target_feature(enable = "neon,faminmax")]
825#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
826#[unstable(feature = "faminmax", issue = "137933")]
827pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
828    unsafe extern "unadjusted" {
829        #[cfg_attr(
830            any(target_arch = "aarch64", target_arch = "arm64ec"),
831            link_name = "llvm.aarch64.neon.famin.v4f16"
832        )]
833        fn _vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
834    }
835    unsafe { _vamin_f16(a, b) }
836}
837#[doc = "Multi-vector floating-point absolute minimum"]
838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"]
839#[inline]
840#[target_feature(enable = "neon,faminmax")]
841#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
842#[unstable(feature = "faminmax", issue = "137933")]
843pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
844    unsafe extern "unadjusted" {
845        #[cfg_attr(
846            any(target_arch = "aarch64", target_arch = "arm64ec"),
847            link_name = "llvm.aarch64.neon.famin.v8f16"
848        )]
849        fn _vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
850    }
851    unsafe { _vaminq_f16(a, b) }
852}
853#[doc = "Multi-vector floating-point absolute minimum"]
854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"]
855#[inline]
856#[target_feature(enable = "neon,faminmax")]
857#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
858#[unstable(feature = "faminmax", issue = "137933")]
859pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
860    unsafe extern "unadjusted" {
861        #[cfg_attr(
862            any(target_arch = "aarch64", target_arch = "arm64ec"),
863            link_name = "llvm.aarch64.neon.famin.v2f32"
864        )]
865        fn _vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
866    }
867    unsafe { _vamin_f32(a, b) }
868}
869#[doc = "Multi-vector floating-point absolute minimum"]
870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"]
871#[inline]
872#[target_feature(enable = "neon,faminmax")]
873#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
874#[unstable(feature = "faminmax", issue = "137933")]
875pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
876    unsafe extern "unadjusted" {
877        #[cfg_attr(
878            any(target_arch = "aarch64", target_arch = "arm64ec"),
879            link_name = "llvm.aarch64.neon.famin.v4f32"
880        )]
881        fn _vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
882    }
883    unsafe { _vaminq_f32(a, b) }
884}
885#[doc = "Multi-vector floating-point absolute minimum"]
886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"]
887#[inline]
888#[target_feature(enable = "neon,faminmax")]
889#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
890#[unstable(feature = "faminmax", issue = "137933")]
891pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
892    unsafe extern "unadjusted" {
893        #[cfg_attr(
894            any(target_arch = "aarch64", target_arch = "arm64ec"),
895            link_name = "llvm.aarch64.neon.famin.v2f64"
896        )]
897        fn _vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
898    }
899    unsafe { _vaminq_f64(a, b) }
900}
901#[doc = "Bit clear and exclusive OR"]
902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8)"]
903#[inline]
904#[target_feature(enable = "neon,sha3")]
905#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
906#[cfg_attr(test, assert_instr(bcax))]
907pub fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
908    unsafe extern "unadjusted" {
909        #[cfg_attr(
910            any(target_arch = "aarch64", target_arch = "arm64ec"),
911            link_name = "llvm.aarch64.crypto.bcaxs.v16i8"
912        )]
913        fn _vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
914    }
915    unsafe { _vbcaxq_s8(a, b, c) }
916}
917#[doc = "Bit clear and exclusive OR"]
918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16)"]
919#[inline]
920#[target_feature(enable = "neon,sha3")]
921#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
922#[cfg_attr(test, assert_instr(bcax))]
923pub fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
924    unsafe extern "unadjusted" {
925        #[cfg_attr(
926            any(target_arch = "aarch64", target_arch = "arm64ec"),
927            link_name = "llvm.aarch64.crypto.bcaxs.v8i16"
928        )]
929        fn _vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
930    }
931    unsafe { _vbcaxq_s16(a, b, c) }
932}
933#[doc = "Bit clear and exclusive OR"]
934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32)"]
935#[inline]
936#[target_feature(enable = "neon,sha3")]
937#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
938#[cfg_attr(test, assert_instr(bcax))]
939pub fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
940    unsafe extern "unadjusted" {
941        #[cfg_attr(
942            any(target_arch = "aarch64", target_arch = "arm64ec"),
943            link_name = "llvm.aarch64.crypto.bcaxs.v4i32"
944        )]
945        fn _vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
946    }
947    unsafe { _vbcaxq_s32(a, b, c) }
948}
949#[doc = "Bit clear and exclusive OR"]
950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64)"]
951#[inline]
952#[target_feature(enable = "neon,sha3")]
953#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
954#[cfg_attr(test, assert_instr(bcax))]
955pub fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
956    unsafe extern "unadjusted" {
957        #[cfg_attr(
958            any(target_arch = "aarch64", target_arch = "arm64ec"),
959            link_name = "llvm.aarch64.crypto.bcaxs.v2i64"
960        )]
961        fn _vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
962    }
963    unsafe { _vbcaxq_s64(a, b, c) }
964}
965#[doc = "Bit clear and exclusive OR"]
966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8)"]
967#[inline]
968#[target_feature(enable = "neon,sha3")]
969#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
970#[cfg_attr(test, assert_instr(bcax))]
971pub fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
972    unsafe extern "unadjusted" {
973        #[cfg_attr(
974            any(target_arch = "aarch64", target_arch = "arm64ec"),
975            link_name = "llvm.aarch64.crypto.bcaxu.v16i8"
976        )]
977        fn _vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t;
978    }
979    unsafe { _vbcaxq_u8(a, b, c) }
980}
981#[doc = "Bit clear and exclusive OR"]
982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16)"]
983#[inline]
984#[target_feature(enable = "neon,sha3")]
985#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
986#[cfg_attr(test, assert_instr(bcax))]
987pub fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
988    unsafe extern "unadjusted" {
989        #[cfg_attr(
990            any(target_arch = "aarch64", target_arch = "arm64ec"),
991            link_name = "llvm.aarch64.crypto.bcaxu.v8i16"
992        )]
993        fn _vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t;
994    }
995    unsafe { _vbcaxq_u16(a, b, c) }
996}
997#[doc = "Bit clear and exclusive OR"]
998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32)"]
999#[inline]
1000#[target_feature(enable = "neon,sha3")]
1001#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
1002#[cfg_attr(test, assert_instr(bcax))]
1003pub fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
1004    unsafe extern "unadjusted" {
1005        #[cfg_attr(
1006            any(target_arch = "aarch64", target_arch = "arm64ec"),
1007            link_name = "llvm.aarch64.crypto.bcaxu.v4i32"
1008        )]
1009        fn _vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t;
1010    }
1011    unsafe { _vbcaxq_u32(a, b, c) }
1012}
1013#[doc = "Bit clear and exclusive OR"]
1014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64)"]
1015#[inline]
1016#[target_feature(enable = "neon,sha3")]
1017#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
1018#[cfg_attr(test, assert_instr(bcax))]
1019pub fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
1020    unsafe extern "unadjusted" {
1021        #[cfg_attr(
1022            any(target_arch = "aarch64", target_arch = "arm64ec"),
1023            link_name = "llvm.aarch64.crypto.bcaxu.v2i64"
1024        )]
1025        fn _vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t;
1026    }
1027    unsafe { _vbcaxq_u64(a, b, c) }
1028}
1029#[doc = "Floating-point complex add"]
1030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"]
1031#[inline]
1032#[cfg(target_endian = "little")]
1033#[target_feature(enable = "neon,fp16")]
1034#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
1035#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1036#[cfg(not(target_arch = "arm64ec"))]
1037#[cfg_attr(test, assert_instr(fcadd))]
1038pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
1039    unsafe extern "unadjusted" {
1040        #[cfg_attr(
1041            any(target_arch = "aarch64", target_arch = "arm64ec"),
1042            link_name = "llvm.aarch64.neon.vcadd.rot270.v4f16"
1043        )]
1044        fn _vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
1045    }
1046    unsafe { _vcadd_rot270_f16(a, b) }
1047}
1048#[doc = "Floating-point complex add"]
1049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"]
1050#[inline]
1051#[cfg(target_endian = "big")]
1052#[target_feature(enable = "neon,fp16")]
1053#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
1054#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1055#[cfg(not(target_arch = "arm64ec"))]
1056#[cfg_attr(test, assert_instr(fcadd))]
1057pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
1058    unsafe extern "unadjusted" {
1059        #[cfg_attr(
1060            any(target_arch = "aarch64", target_arch = "arm64ec"),
1061            link_name = "llvm.aarch64.neon.vcadd.rot270.v4f16"
1062        )]
1063        fn _vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
1064    }
1065    unsafe {
1066        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
1067        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
1068        let ret_val: float16x4_t = _vcadd_rot270_f16(a, b);
1069        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
1070    }
1071}
1072#[doc = "Floating-point complex add"]
1073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"]
1074#[inline]
1075#[cfg(target_endian = "little")]
1076#[target_feature(enable = "neon,fp16")]
1077#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
1078#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1079#[cfg(not(target_arch = "arm64ec"))]
1080#[cfg_attr(test, assert_instr(fcadd))]
1081pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
1082    unsafe extern "unadjusted" {
1083        #[cfg_attr(
1084            any(target_arch = "aarch64", target_arch = "arm64ec"),
1085            link_name = "llvm.aarch64.neon.vcadd.rot270.v8f16"
1086        )]
1087        fn _vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
1088    }
1089    unsafe { _vcaddq_rot270_f16(a, b) }
1090}
1091#[doc = "Floating-point complex add"]
1092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"]
1093#[inline]
1094#[cfg(target_endian = "big")]
1095#[target_feature(enable = "neon,fp16")]
1096#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
1097#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1098#[cfg(not(target_arch = "arm64ec"))]
1099#[cfg_attr(test, assert_instr(fcadd))]
1100pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
1101    unsafe extern "unadjusted" {
1102        #[cfg_attr(
1103            any(target_arch = "aarch64", target_arch = "arm64ec"),
1104            link_name = "llvm.aarch64.neon.vcadd.rot270.v8f16"
1105        )]
1106        fn _vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
1107    }
1108    unsafe {
1109        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
1110        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
1111        let ret_val: float16x8_t = _vcaddq_rot270_f16(a, b);
1112        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
1113    }
1114}
1115#[doc = "Floating-point complex add"]
1116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"]
1117#[inline]
1118#[cfg(target_endian = "little")]
1119#[target_feature(enable = "neon,fcma")]
1120#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1121#[cfg_attr(test, assert_instr(fcadd))]
1122pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
1123    unsafe extern "unadjusted" {
1124        #[cfg_attr(
1125            any(target_arch = "aarch64", target_arch = "arm64ec"),
1126            link_name = "llvm.aarch64.neon.vcadd.rot270.v2f32"
1127        )]
1128        fn _vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
1129    }
1130    unsafe { _vcadd_rot270_f32(a, b) }
1131}
1132#[doc = "Floating-point complex add"]
1133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"]
1134#[inline]
1135#[cfg(target_endian = "big")]
1136#[target_feature(enable = "neon,fcma")]
1137#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1138#[cfg_attr(test, assert_instr(fcadd))]
1139pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
1140    unsafe extern "unadjusted" {
1141        #[cfg_attr(
1142            any(target_arch = "aarch64", target_arch = "arm64ec"),
1143            link_name = "llvm.aarch64.neon.vcadd.rot270.v2f32"
1144        )]
1145        fn _vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
1146    }
1147    unsafe {
1148        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
1149        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
1150        let ret_val: float32x2_t = _vcadd_rot270_f32(a, b);
1151        simd_shuffle!(ret_val, ret_val, [1, 0])
1152    }
1153}
1154#[doc = "Floating-point complex add"]
1155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"]
1156#[inline]
1157#[cfg(target_endian = "little")]
1158#[target_feature(enable = "neon,fcma")]
1159#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1160#[cfg_attr(test, assert_instr(fcadd))]
1161pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
1162    unsafe extern "unadjusted" {
1163        #[cfg_attr(
1164            any(target_arch = "aarch64", target_arch = "arm64ec"),
1165            link_name = "llvm.aarch64.neon.vcadd.rot270.v4f32"
1166        )]
1167        fn _vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
1168    }
1169    unsafe { _vcaddq_rot270_f32(a, b) }
1170}
1171#[doc = "Floating-point complex add"]
1172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"]
1173#[inline]
1174#[cfg(target_endian = "big")]
1175#[target_feature(enable = "neon,fcma")]
1176#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1177#[cfg_attr(test, assert_instr(fcadd))]
1178pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
1179    unsafe extern "unadjusted" {
1180        #[cfg_attr(
1181            any(target_arch = "aarch64", target_arch = "arm64ec"),
1182            link_name = "llvm.aarch64.neon.vcadd.rot270.v4f32"
1183        )]
1184        fn _vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
1185    }
1186    unsafe {
1187        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
1188        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
1189        let ret_val: float32x4_t = _vcaddq_rot270_f32(a, b);
1190        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
1191    }
1192}
1193#[doc = "Floating-point complex add"]
1194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"]
1195#[inline]
1196#[cfg(target_endian = "little")]
1197#[target_feature(enable = "neon,fcma")]
1198#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1199#[cfg_attr(test, assert_instr(fcadd))]
1200pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
1201    unsafe extern "unadjusted" {
1202        #[cfg_attr(
1203            any(target_arch = "aarch64", target_arch = "arm64ec"),
1204            link_name = "llvm.aarch64.neon.vcadd.rot270.v2f64"
1205        )]
1206        fn _vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
1207    }
1208    unsafe { _vcaddq_rot270_f64(a, b) }
1209}
1210#[doc = "Floating-point complex add"]
1211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"]
1212#[inline]
1213#[cfg(target_endian = "big")]
1214#[target_feature(enable = "neon,fcma")]
1215#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1216#[cfg_attr(test, assert_instr(fcadd))]
1217pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
1218    unsafe extern "unadjusted" {
1219        #[cfg_attr(
1220            any(target_arch = "aarch64", target_arch = "arm64ec"),
1221            link_name = "llvm.aarch64.neon.vcadd.rot270.v2f64"
1222        )]
1223        fn _vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
1224    }
1225    unsafe {
1226        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
1227        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
1228        let ret_val: float64x2_t = _vcaddq_rot270_f64(a, b);
1229        simd_shuffle!(ret_val, ret_val, [1, 0])
1230    }
1231}
1232#[doc = "Floating-point complex add"]
1233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"]
1234#[inline]
1235#[cfg(target_endian = "little")]
1236#[target_feature(enable = "neon,fp16")]
1237#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
1238#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1239#[cfg(not(target_arch = "arm64ec"))]
1240#[cfg_attr(test, assert_instr(fcadd))]
1241pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
1242    unsafe extern "unadjusted" {
1243        #[cfg_attr(
1244            any(target_arch = "aarch64", target_arch = "arm64ec"),
1245            link_name = "llvm.aarch64.neon.vcadd.rot90.v4f16"
1246        )]
1247        fn _vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
1248    }
1249    unsafe { _vcadd_rot90_f16(a, b) }
1250}
1251#[doc = "Floating-point complex add"]
1252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"]
1253#[inline]
1254#[cfg(target_endian = "big")]
1255#[target_feature(enable = "neon,fp16")]
1256#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
1257#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1258#[cfg(not(target_arch = "arm64ec"))]
1259#[cfg_attr(test, assert_instr(fcadd))]
1260pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
1261    unsafe extern "unadjusted" {
1262        #[cfg_attr(
1263            any(target_arch = "aarch64", target_arch = "arm64ec"),
1264            link_name = "llvm.aarch64.neon.vcadd.rot90.v4f16"
1265        )]
1266        fn _vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
1267    }
1268    unsafe {
1269        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
1270        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
1271        let ret_val: float16x4_t = _vcadd_rot90_f16(a, b);
1272        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
1273    }
1274}
1275#[doc = "Floating-point complex add"]
1276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"]
1277#[inline]
1278#[cfg(target_endian = "little")]
1279#[target_feature(enable = "neon,fp16")]
1280#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
1281#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1282#[cfg(not(target_arch = "arm64ec"))]
1283#[cfg_attr(test, assert_instr(fcadd))]
1284pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
1285    unsafe extern "unadjusted" {
1286        #[cfg_attr(
1287            any(target_arch = "aarch64", target_arch = "arm64ec"),
1288            link_name = "llvm.aarch64.neon.vcadd.rot90.v8f16"
1289        )]
1290        fn _vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
1291    }
1292    unsafe { _vcaddq_rot90_f16(a, b) }
1293}
1294#[doc = "Floating-point complex add"]
1295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"]
1296#[inline]
1297#[cfg(target_endian = "big")]
1298#[target_feature(enable = "neon,fp16")]
1299#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
1300#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1301#[cfg(not(target_arch = "arm64ec"))]
1302#[cfg_attr(test, assert_instr(fcadd))]
1303pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
1304    unsafe extern "unadjusted" {
1305        #[cfg_attr(
1306            any(target_arch = "aarch64", target_arch = "arm64ec"),
1307            link_name = "llvm.aarch64.neon.vcadd.rot90.v8f16"
1308        )]
1309        fn _vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
1310    }
1311    unsafe {
1312        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
1313        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
1314        let ret_val: float16x8_t = _vcaddq_rot90_f16(a, b);
1315        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
1316    }
1317}
1318#[doc = "Floating-point complex add"]
1319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"]
1320#[inline]
1321#[cfg(target_endian = "little")]
1322#[target_feature(enable = "neon,fcma")]
1323#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1324#[cfg_attr(test, assert_instr(fcadd))]
1325pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
1326    unsafe extern "unadjusted" {
1327        #[cfg_attr(
1328            any(target_arch = "aarch64", target_arch = "arm64ec"),
1329            link_name = "llvm.aarch64.neon.vcadd.rot90.v2f32"
1330        )]
1331        fn _vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
1332    }
1333    unsafe { _vcadd_rot90_f32(a, b) }
1334}
1335#[doc = "Floating-point complex add"]
1336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"]
1337#[inline]
1338#[cfg(target_endian = "big")]
1339#[target_feature(enable = "neon,fcma")]
1340#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1341#[cfg_attr(test, assert_instr(fcadd))]
1342pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
1343    unsafe extern "unadjusted" {
1344        #[cfg_attr(
1345            any(target_arch = "aarch64", target_arch = "arm64ec"),
1346            link_name = "llvm.aarch64.neon.vcadd.rot90.v2f32"
1347        )]
1348        fn _vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
1349    }
1350    unsafe {
1351        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
1352        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
1353        let ret_val: float32x2_t = _vcadd_rot90_f32(a, b);
1354        simd_shuffle!(ret_val, ret_val, [1, 0])
1355    }
1356}
1357#[doc = "Floating-point complex add"]
1358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"]
1359#[inline]
1360#[cfg(target_endian = "little")]
1361#[target_feature(enable = "neon,fcma")]
1362#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1363#[cfg_attr(test, assert_instr(fcadd))]
1364pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
1365    unsafe extern "unadjusted" {
1366        #[cfg_attr(
1367            any(target_arch = "aarch64", target_arch = "arm64ec"),
1368            link_name = "llvm.aarch64.neon.vcadd.rot90.v4f32"
1369        )]
1370        fn _vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
1371    }
1372    unsafe { _vcaddq_rot90_f32(a, b) }
1373}
1374#[doc = "Floating-point complex add"]
1375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"]
1376#[inline]
1377#[cfg(target_endian = "big")]
1378#[target_feature(enable = "neon,fcma")]
1379#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1380#[cfg_attr(test, assert_instr(fcadd))]
1381pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
1382    unsafe extern "unadjusted" {
1383        #[cfg_attr(
1384            any(target_arch = "aarch64", target_arch = "arm64ec"),
1385            link_name = "llvm.aarch64.neon.vcadd.rot90.v4f32"
1386        )]
1387        fn _vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
1388    }
1389    unsafe {
1390        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
1391        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
1392        let ret_val: float32x4_t = _vcaddq_rot90_f32(a, b);
1393        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
1394    }
1395}
1396#[doc = "Floating-point complex add"]
1397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"]
1398#[inline]
1399#[cfg(target_endian = "little")]
1400#[target_feature(enable = "neon,fcma")]
1401#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1402#[cfg_attr(test, assert_instr(fcadd))]
1403pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
1404    unsafe extern "unadjusted" {
1405        #[cfg_attr(
1406            any(target_arch = "aarch64", target_arch = "arm64ec"),
1407            link_name = "llvm.aarch64.neon.vcadd.rot90.v2f64"
1408        )]
1409        fn _vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
1410    }
1411    unsafe { _vcaddq_rot90_f64(a, b) }
1412}
1413#[doc = "Floating-point complex add"]
1414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"]
1415#[inline]
1416#[cfg(target_endian = "big")]
1417#[target_feature(enable = "neon,fcma")]
1418#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
1419#[cfg_attr(test, assert_instr(fcadd))]
1420pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
1421    unsafe extern "unadjusted" {
1422        #[cfg_attr(
1423            any(target_arch = "aarch64", target_arch = "arm64ec"),
1424            link_name = "llvm.aarch64.neon.vcadd.rot90.v2f64"
1425        )]
1426        fn _vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
1427    }
1428    unsafe {
1429        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
1430        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
1431        let ret_val: float64x2_t = _vcaddq_rot90_f64(a, b);
1432        simd_shuffle!(ret_val, ret_val, [1, 0])
1433    }
1434}
1435#[doc = "Floating-point absolute compare greater than or equal"]
1436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)"]
1437#[inline]
1438#[target_feature(enable = "neon")]
1439#[cfg_attr(test, assert_instr(facge))]
1440#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1441pub fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
1442    unsafe extern "unadjusted" {
1443        #[cfg_attr(
1444            any(target_arch = "aarch64", target_arch = "arm64ec"),
1445            link_name = "llvm.aarch64.neon.facge.v1i64.v1f64"
1446        )]
1447        fn _vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t;
1448    }
1449    unsafe { _vcage_f64(a, b) }
1450}
1451#[doc = "Floating-point absolute compare greater than or equal"]
1452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)"]
1453#[inline]
1454#[target_feature(enable = "neon")]
1455#[cfg_attr(test, assert_instr(facge))]
1456#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1457pub fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
1458    unsafe extern "unadjusted" {
1459        #[cfg_attr(
1460            any(target_arch = "aarch64", target_arch = "arm64ec"),
1461            link_name = "llvm.aarch64.neon.facge.v2i64.v2f64"
1462        )]
1463        fn _vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t;
1464    }
1465    unsafe { _vcageq_f64(a, b) }
1466}
1467#[doc = "Floating-point absolute compare greater than or equal"]
1468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64)"]
1469#[inline]
1470#[target_feature(enable = "neon")]
1471#[cfg_attr(test, assert_instr(facge))]
1472#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1473pub fn vcaged_f64(a: f64, b: f64) -> u64 {
1474    unsafe extern "unadjusted" {
1475        #[cfg_attr(
1476            any(target_arch = "aarch64", target_arch = "arm64ec"),
1477            link_name = "llvm.aarch64.neon.facge.i64.f64"
1478        )]
1479        fn _vcaged_f64(a: f64, b: f64) -> u64;
1480    }
1481    unsafe { _vcaged_f64(a, b) }
1482}
1483#[doc = "Floating-point absolute compare greater than or equal"]
1484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)"]
1485#[inline]
1486#[target_feature(enable = "neon")]
1487#[cfg_attr(test, assert_instr(facge))]
1488#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1489pub fn vcages_f32(a: f32, b: f32) -> u32 {
1490    unsafe extern "unadjusted" {
1491        #[cfg_attr(
1492            any(target_arch = "aarch64", target_arch = "arm64ec"),
1493            link_name = "llvm.aarch64.neon.facge.i32.f32"
1494        )]
1495        fn _vcages_f32(a: f32, b: f32) -> u32;
1496    }
1497    unsafe { _vcages_f32(a, b) }
1498}
1499#[doc = "Floating-point absolute compare greater than or equal"]
1500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageh_f16)"]
1501#[inline]
1502#[cfg_attr(test, assert_instr(facge))]
1503#[target_feature(enable = "neon,fp16")]
1504#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1505#[cfg(not(target_arch = "arm64ec"))]
1506pub fn vcageh_f16(a: f16, b: f16) -> u16 {
1507    unsafe extern "unadjusted" {
1508        #[cfg_attr(
1509            any(target_arch = "aarch64", target_arch = "arm64ec"),
1510            link_name = "llvm.aarch64.neon.facge.i32.f16"
1511        )]
1512        fn _vcageh_f16(a: f16, b: f16) -> i32;
1513    }
1514    unsafe { _vcageh_f16(a, b) as u16 }
1515}
1516#[doc = "Floating-point absolute compare greater than"]
1517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)"]
1518#[inline]
1519#[target_feature(enable = "neon")]
1520#[cfg_attr(test, assert_instr(facgt))]
1521#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1522pub fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
1523    unsafe extern "unadjusted" {
1524        #[cfg_attr(
1525            any(target_arch = "aarch64", target_arch = "arm64ec"),
1526            link_name = "llvm.aarch64.neon.facgt.v1i64.v1f64"
1527        )]
1528        fn _vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t;
1529    }
1530    unsafe { _vcagt_f64(a, b) }
1531}
1532#[doc = "Floating-point absolute compare greater than"]
1533#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)"]
1534#[inline]
1535#[target_feature(enable = "neon")]
1536#[cfg_attr(test, assert_instr(facgt))]
1537#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1538pub fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
1539    unsafe extern "unadjusted" {
1540        #[cfg_attr(
1541            any(target_arch = "aarch64", target_arch = "arm64ec"),
1542            link_name = "llvm.aarch64.neon.facgt.v2i64.v2f64"
1543        )]
1544        fn _vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t;
1545    }
1546    unsafe { _vcagtq_f64(a, b) }
1547}
1548#[doc = "Floating-point absolute compare greater than"]
1549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64)"]
1550#[inline]
1551#[target_feature(enable = "neon")]
1552#[cfg_attr(test, assert_instr(facgt))]
1553#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1554pub fn vcagtd_f64(a: f64, b: f64) -> u64 {
1555    unsafe extern "unadjusted" {
1556        #[cfg_attr(
1557            any(target_arch = "aarch64", target_arch = "arm64ec"),
1558            link_name = "llvm.aarch64.neon.facgt.i64.f64"
1559        )]
1560        fn _vcagtd_f64(a: f64, b: f64) -> u64;
1561    }
1562    unsafe { _vcagtd_f64(a, b) }
1563}
1564#[doc = "Floating-point absolute compare greater than"]
1565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)"]
1566#[inline]
1567#[target_feature(enable = "neon")]
1568#[cfg_attr(test, assert_instr(facgt))]
1569#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1570pub fn vcagts_f32(a: f32, b: f32) -> u32 {
1571    unsafe extern "unadjusted" {
1572        #[cfg_attr(
1573            any(target_arch = "aarch64", target_arch = "arm64ec"),
1574            link_name = "llvm.aarch64.neon.facgt.i32.f32"
1575        )]
1576        fn _vcagts_f32(a: f32, b: f32) -> u32;
1577    }
1578    unsafe { _vcagts_f32(a, b) }
1579}
1580#[doc = "Floating-point absolute compare greater than"]
1581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagth_f16)"]
1582#[inline]
1583#[cfg_attr(test, assert_instr(facgt))]
1584#[target_feature(enable = "neon,fp16")]
1585#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1586#[cfg(not(target_arch = "arm64ec"))]
1587pub fn vcagth_f16(a: f16, b: f16) -> u16 {
1588    unsafe extern "unadjusted" {
1589        #[cfg_attr(
1590            any(target_arch = "aarch64", target_arch = "arm64ec"),
1591            link_name = "llvm.aarch64.neon.facgt.i32.f16"
1592        )]
1593        fn _vcagth_f16(a: f16, b: f16) -> i32;
1594    }
1595    unsafe { _vcagth_f16(a, b) as u16 }
1596}
1597#[doc = "Floating-point absolute compare less than or equal"]
1598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)"]
1599#[inline]
1600#[target_feature(enable = "neon")]
1601#[cfg_attr(test, assert_instr(facge))]
1602#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1603pub fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
1604    vcage_f64(b, a)
1605}
1606#[doc = "Floating-point absolute compare less than or equal"]
1607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)"]
1608#[inline]
1609#[target_feature(enable = "neon")]
1610#[cfg_attr(test, assert_instr(facge))]
1611#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1612pub fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
1613    vcageq_f64(b, a)
1614}
1615#[doc = "Floating-point absolute compare less than or equal"]
1616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64)"]
1617#[inline]
1618#[target_feature(enable = "neon")]
1619#[cfg_attr(test, assert_instr(facge))]
1620#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1621pub fn vcaled_f64(a: f64, b: f64) -> u64 {
1622    vcaged_f64(b, a)
1623}
1624#[doc = "Floating-point absolute compare less than or equal"]
1625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)"]
1626#[inline]
1627#[target_feature(enable = "neon")]
1628#[cfg_attr(test, assert_instr(facge))]
1629#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1630pub fn vcales_f32(a: f32, b: f32) -> u32 {
1631    vcages_f32(b, a)
1632}
1633#[doc = "Floating-point absolute compare less than or equal"]
1634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleh_f16)"]
1635#[inline]
1636#[cfg_attr(test, assert_instr(facge))]
1637#[target_feature(enable = "neon,fp16")]
1638#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1639#[cfg(not(target_arch = "arm64ec"))]
1640pub fn vcaleh_f16(a: f16, b: f16) -> u16 {
1641    vcageh_f16(b, a)
1642}
1643#[doc = "Floating-point absolute compare less than"]
1644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)"]
1645#[inline]
1646#[target_feature(enable = "neon")]
1647#[cfg_attr(test, assert_instr(facgt))]
1648#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1649pub fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
1650    vcagt_f64(b, a)
1651}
1652#[doc = "Floating-point absolute compare less than"]
1653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)"]
1654#[inline]
1655#[target_feature(enable = "neon")]
1656#[cfg_attr(test, assert_instr(facgt))]
1657#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1658pub fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
1659    vcagtq_f64(b, a)
1660}
1661#[doc = "Floating-point absolute compare less than"]
1662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64)"]
1663#[inline]
1664#[target_feature(enable = "neon")]
1665#[cfg_attr(test, assert_instr(facgt))]
1666#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1667pub fn vcaltd_f64(a: f64, b: f64) -> u64 {
1668    vcagtd_f64(b, a)
1669}
1670#[doc = "Floating-point absolute compare less than"]
1671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)"]
1672#[inline]
1673#[target_feature(enable = "neon")]
1674#[cfg_attr(test, assert_instr(facgt))]
1675#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1676pub fn vcalts_f32(a: f32, b: f32) -> u32 {
1677    vcagts_f32(b, a)
1678}
1679#[doc = "Floating-point absolute compare less than"]
1680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalth_f16)"]
1681#[inline]
1682#[cfg_attr(test, assert_instr(facgt))]
1683#[target_feature(enable = "neon,fp16")]
1684#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1685#[cfg(not(target_arch = "arm64ec"))]
1686pub fn vcalth_f16(a: f16, b: f16) -> u16 {
1687    vcagth_f16(b, a)
1688}
1689#[doc = "Floating-point compare equal"]
1690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)"]
1691#[inline]
1692#[target_feature(enable = "neon")]
1693#[cfg_attr(test, assert_instr(fcmeq))]
1694#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1695pub fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
1696    unsafe { simd_eq(a, b) }
1697}
1698#[doc = "Floating-point compare equal"]
1699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)"]
1700#[inline]
1701#[target_feature(enable = "neon")]
1702#[cfg_attr(test, assert_instr(fcmeq))]
1703#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1704pub fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
1705    unsafe { simd_eq(a, b) }
1706}
1707#[doc = "Compare bitwise Equal (vector)"]
1708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)"]
1709#[inline]
1710#[target_feature(enable = "neon")]
1711#[cfg_attr(test, assert_instr(cmeq))]
1712#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1713pub fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
1714    unsafe { simd_eq(a, b) }
1715}
1716#[doc = "Compare bitwise Equal (vector)"]
1717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)"]
1718#[inline]
1719#[target_feature(enable = "neon")]
1720#[cfg_attr(test, assert_instr(cmeq))]
1721#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1722pub fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
1723    unsafe { simd_eq(a, b) }
1724}
1725#[doc = "Compare bitwise Equal (vector)"]
1726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)"]
1727#[inline]
1728#[target_feature(enable = "neon")]
1729#[cfg_attr(test, assert_instr(cmeq))]
1730#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1731pub fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
1732    unsafe { simd_eq(a, b) }
1733}
1734#[doc = "Compare bitwise Equal (vector)"]
1735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)"]
1736#[inline]
1737#[target_feature(enable = "neon")]
1738#[cfg_attr(test, assert_instr(cmeq))]
1739#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1740pub fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
1741    unsafe { simd_eq(a, b) }
1742}
1743#[doc = "Compare bitwise Equal (vector)"]
1744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64)"]
1745#[inline]
1746#[target_feature(enable = "neon")]
1747#[cfg_attr(test, assert_instr(cmeq))]
1748#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1749pub fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t {
1750    unsafe { simd_eq(a, b) }
1751}
1752#[doc = "Compare bitwise Equal (vector)"]
1753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64)"]
1754#[inline]
1755#[target_feature(enable = "neon")]
1756#[cfg_attr(test, assert_instr(cmeq))]
1757#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1758pub fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
1759    unsafe { simd_eq(a, b) }
1760}
1761#[doc = "Floating-point compare equal"]
1762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64)"]
1763#[inline]
1764#[target_feature(enable = "neon")]
1765#[cfg_attr(test, assert_instr(fcmp))]
1766#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1767pub fn vceqd_f64(a: f64, b: f64) -> u64 {
1768    vget_lane_u64::<0>(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)))
1769}
1770#[doc = "Floating-point compare equal"]
1771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"]
1772#[inline]
1773#[target_feature(enable = "neon")]
1774#[cfg_attr(test, assert_instr(fcmp))]
1775#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1776pub fn vceqs_f32(a: f32, b: f32) -> u32 {
1777    vget_lane_u32::<0>(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)))
1778}
1779#[doc = "Compare bitwise equal"]
1780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"]
1781#[inline]
1782#[target_feature(enable = "neon")]
1783#[cfg_attr(test, assert_instr(cmp))]
1784#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1785pub fn vceqd_s64(a: i64, b: i64) -> u64 {
1786    unsafe { transmute(vceq_s64(transmute(a), transmute(b))) }
1787}
1788#[doc = "Compare bitwise equal"]
1789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64)"]
1790#[inline]
1791#[target_feature(enable = "neon")]
1792#[cfg_attr(test, assert_instr(cmp))]
1793#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1794pub fn vceqd_u64(a: u64, b: u64) -> u64 {
1795    unsafe { transmute(vceq_u64(transmute(a), transmute(b))) }
1796}
1797#[doc = "Floating-point compare equal"]
1798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqh_f16)"]
1799#[inline]
1800#[cfg_attr(test, assert_instr(fcmp))]
1801#[target_feature(enable = "neon,fp16")]
1802#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1803#[cfg(not(target_arch = "arm64ec"))]
1804pub fn vceqh_f16(a: f16, b: f16) -> u16 {
1805    vget_lane_u16::<0>(vceq_f16(vdup_n_f16(a), vdup_n_f16(b)))
1806}
1807#[doc = "Floating-point compare bitwise equal to zero"]
1808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f16)"]
1809#[inline]
1810#[cfg_attr(test, assert_instr(fcmeq))]
1811#[target_feature(enable = "neon,fp16")]
1812#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
1813#[cfg(not(target_arch = "arm64ec"))]
1814pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t {
1815    let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
1816    unsafe { simd_eq(a, transmute(b)) }
1817}
1818#[doc = "Floating-point compare bitwise equal to zero"]
1819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f16)"]
1820#[inline]
1821#[cfg_attr(test, assert_instr(fcmeq))]
1822#[target_feature(enable = "neon,fp16")]
1823#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
1824#[cfg(not(target_arch = "arm64ec"))]
1825pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t {
1826    let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
1827    unsafe { simd_eq(a, transmute(b)) }
1828}
1829#[doc = "Floating-point compare bitwise equal to zero"]
1830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32)"]
1831#[inline]
1832#[target_feature(enable = "neon")]
1833#[cfg_attr(test, assert_instr(fcmeq))]
1834#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1835pub fn vceqz_f32(a: float32x2_t) -> uint32x2_t {
1836    let b: f32x2 = f32x2::new(0.0, 0.0);
1837    unsafe { simd_eq(a, transmute(b)) }
1838}
1839#[doc = "Floating-point compare bitwise equal to zero"]
1840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32)"]
1841#[inline]
1842#[target_feature(enable = "neon")]
1843#[cfg_attr(test, assert_instr(fcmeq))]
1844#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1845pub fn vceqzq_f32(a: float32x4_t) -> uint32x4_t {
1846    let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0);
1847    unsafe { simd_eq(a, transmute(b)) }
1848}
1849#[doc = "Floating-point compare bitwise equal to zero"]
1850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64)"]
1851#[inline]
1852#[target_feature(enable = "neon")]
1853#[cfg_attr(test, assert_instr(fcmeq))]
1854#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1855pub fn vceqz_f64(a: float64x1_t) -> uint64x1_t {
1856    let b: f64 = 0.0;
1857    unsafe { simd_eq(a, transmute(b)) }
1858}
1859#[doc = "Floating-point compare bitwise equal to zero"]
1860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64)"]
1861#[inline]
1862#[target_feature(enable = "neon")]
1863#[cfg_attr(test, assert_instr(fcmeq))]
1864#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1865pub fn vceqzq_f64(a: float64x2_t) -> uint64x2_t {
1866    let b: f64x2 = f64x2::new(0.0, 0.0);
1867    unsafe { simd_eq(a, transmute(b)) }
1868}
1869#[doc = "Signed compare bitwise equal to zero"]
1870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8)"]
1871#[inline]
1872#[target_feature(enable = "neon")]
1873#[cfg_attr(test, assert_instr(cmeq))]
1874#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1875pub fn vceqz_s8(a: int8x8_t) -> uint8x8_t {
1876    let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
1877    unsafe { simd_eq(a, transmute(b)) }
1878}
1879#[doc = "Signed compare bitwise equal to zero"]
1880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8)"]
1881#[inline]
1882#[target_feature(enable = "neon")]
1883#[cfg_attr(test, assert_instr(cmeq))]
1884#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1885pub fn vceqzq_s8(a: int8x16_t) -> uint8x16_t {
1886    let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
1887    unsafe { simd_eq(a, transmute(b)) }
1888}
1889#[doc = "Signed compare bitwise equal to zero"]
1890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16)"]
1891#[inline]
1892#[target_feature(enable = "neon")]
1893#[cfg_attr(test, assert_instr(cmeq))]
1894#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1895pub fn vceqz_s16(a: int16x4_t) -> uint16x4_t {
1896    let b: i16x4 = i16x4::new(0, 0, 0, 0);
1897    unsafe { simd_eq(a, transmute(b)) }
1898}
1899#[doc = "Signed compare bitwise equal to zero"]
1900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16)"]
1901#[inline]
1902#[target_feature(enable = "neon")]
1903#[cfg_attr(test, assert_instr(cmeq))]
1904#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1905pub fn vceqzq_s16(a: int16x8_t) -> uint16x8_t {
1906    let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
1907    unsafe { simd_eq(a, transmute(b)) }
1908}
1909#[doc = "Signed compare bitwise equal to zero"]
1910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32)"]
1911#[inline]
1912#[target_feature(enable = "neon")]
1913#[cfg_attr(test, assert_instr(cmeq))]
1914#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1915pub fn vceqz_s32(a: int32x2_t) -> uint32x2_t {
1916    let b: i32x2 = i32x2::new(0, 0);
1917    unsafe { simd_eq(a, transmute(b)) }
1918}
1919#[doc = "Signed compare bitwise equal to zero"]
1920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32)"]
1921#[inline]
1922#[target_feature(enable = "neon")]
1923#[cfg_attr(test, assert_instr(cmeq))]
1924#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1925pub fn vceqzq_s32(a: int32x4_t) -> uint32x4_t {
1926    let b: i32x4 = i32x4::new(0, 0, 0, 0);
1927    unsafe { simd_eq(a, transmute(b)) }
1928}
1929#[doc = "Signed compare bitwise equal to zero"]
1930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64)"]
1931#[inline]
1932#[target_feature(enable = "neon")]
1933#[cfg_attr(test, assert_instr(cmeq))]
1934#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1935pub fn vceqz_s64(a: int64x1_t) -> uint64x1_t {
1936    let b: i64x1 = i64x1::new(0);
1937    unsafe { simd_eq(a, transmute(b)) }
1938}
1939#[doc = "Signed compare bitwise equal to zero"]
1940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64)"]
1941#[inline]
1942#[target_feature(enable = "neon")]
1943#[cfg_attr(test, assert_instr(cmeq))]
1944#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1945pub fn vceqzq_s64(a: int64x2_t) -> uint64x2_t {
1946    let b: i64x2 = i64x2::new(0, 0);
1947    unsafe { simd_eq(a, transmute(b)) }
1948}
1949#[doc = "Signed compare bitwise equal to zero"]
1950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8)"]
1951#[inline]
1952#[target_feature(enable = "neon")]
1953#[cfg_attr(test, assert_instr(cmeq))]
1954#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1955pub fn vceqz_p8(a: poly8x8_t) -> uint8x8_t {
1956    let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
1957    unsafe { simd_eq(a, transmute(b)) }
1958}
1959#[doc = "Signed compare bitwise equal to zero"]
1960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8)"]
1961#[inline]
1962#[target_feature(enable = "neon")]
1963#[cfg_attr(test, assert_instr(cmeq))]
1964#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1965pub fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t {
1966    let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
1967    unsafe { simd_eq(a, transmute(b)) }
1968}
1969#[doc = "Signed compare bitwise equal to zero"]
1970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64)"]
1971#[inline]
1972#[target_feature(enable = "neon")]
1973#[cfg_attr(test, assert_instr(cmeq))]
1974#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1975pub fn vceqz_p64(a: poly64x1_t) -> uint64x1_t {
1976    let b: i64x1 = i64x1::new(0);
1977    unsafe { simd_eq(a, transmute(b)) }
1978}
1979#[doc = "Signed compare bitwise equal to zero"]
1980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64)"]
1981#[inline]
1982#[target_feature(enable = "neon")]
1983#[cfg_attr(test, assert_instr(cmeq))]
1984#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1985pub fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t {
1986    let b: i64x2 = i64x2::new(0, 0);
1987    unsafe { simd_eq(a, transmute(b)) }
1988}
1989#[doc = "Unsigned compare bitwise equal to zero"]
1990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8)"]
1991#[inline]
1992#[target_feature(enable = "neon")]
1993#[cfg_attr(test, assert_instr(cmeq))]
1994#[stable(feature = "neon_intrinsics", since = "1.59.0")]
1995pub fn vceqz_u8(a: uint8x8_t) -> uint8x8_t {
1996    let b: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
1997    unsafe { simd_eq(a, transmute(b)) }
1998}
1999#[doc = "Unsigned compare bitwise equal to zero"]
2000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8)"]
2001#[inline]
2002#[target_feature(enable = "neon")]
2003#[cfg_attr(test, assert_instr(cmeq))]
2004#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2005pub fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t {
2006    let b: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
2007    unsafe { simd_eq(a, transmute(b)) }
2008}
2009#[doc = "Unsigned compare bitwise equal to zero"]
2010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16)"]
2011#[inline]
2012#[target_feature(enable = "neon")]
2013#[cfg_attr(test, assert_instr(cmeq))]
2014#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2015pub fn vceqz_u16(a: uint16x4_t) -> uint16x4_t {
2016    let b: u16x4 = u16x4::new(0, 0, 0, 0);
2017    unsafe { simd_eq(a, transmute(b)) }
2018}
2019#[doc = "Unsigned compare bitwise equal to zero"]
2020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16)"]
2021#[inline]
2022#[target_feature(enable = "neon")]
2023#[cfg_attr(test, assert_instr(cmeq))]
2024#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2025pub fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t {
2026    let b: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
2027    unsafe { simd_eq(a, transmute(b)) }
2028}
2029#[doc = "Unsigned compare bitwise equal to zero"]
2030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32)"]
2031#[inline]
2032#[target_feature(enable = "neon")]
2033#[cfg_attr(test, assert_instr(cmeq))]
2034#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2035pub fn vceqz_u32(a: uint32x2_t) -> uint32x2_t {
2036    let b: u32x2 = u32x2::new(0, 0);
2037    unsafe { simd_eq(a, transmute(b)) }
2038}
2039#[doc = "Unsigned compare bitwise equal to zero"]
2040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32)"]
2041#[inline]
2042#[target_feature(enable = "neon")]
2043#[cfg_attr(test, assert_instr(cmeq))]
2044#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2045pub fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t {
2046    let b: u32x4 = u32x4::new(0, 0, 0, 0);
2047    unsafe { simd_eq(a, transmute(b)) }
2048}
2049#[doc = "Unsigned compare bitwise equal to zero"]
2050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64)"]
2051#[inline]
2052#[target_feature(enable = "neon")]
2053#[cfg_attr(test, assert_instr(cmeq))]
2054#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2055pub fn vceqz_u64(a: uint64x1_t) -> uint64x1_t {
2056    let b: u64x1 = u64x1::new(0);
2057    unsafe { simd_eq(a, transmute(b)) }
2058}
2059#[doc = "Unsigned compare bitwise equal to zero"]
2060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64)"]
2061#[inline]
2062#[target_feature(enable = "neon")]
2063#[cfg_attr(test, assert_instr(cmeq))]
2064#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2065pub fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t {
2066    let b: u64x2 = u64x2::new(0, 0);
2067    unsafe { simd_eq(a, transmute(b)) }
2068}
2069#[doc = "Compare bitwise equal to zero"]
2070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64)"]
2071#[inline]
2072#[target_feature(enable = "neon")]
2073#[cfg_attr(test, assert_instr(cmp))]
2074#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2075pub fn vceqzd_s64(a: i64) -> u64 {
2076    unsafe { transmute(vceqz_s64(transmute(a))) }
2077}
2078#[doc = "Compare bitwise equal to zero"]
2079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64)"]
2080#[inline]
2081#[target_feature(enable = "neon")]
2082#[cfg_attr(test, assert_instr(cmp))]
2083#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2084pub fn vceqzd_u64(a: u64) -> u64 {
2085    unsafe { transmute(vceqz_u64(transmute(a))) }
2086}
2087#[doc = "Floating-point compare bitwise equal to zero"]
2088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzh_f16)"]
2089#[inline]
2090#[cfg_attr(test, assert_instr(fcmp))]
2091#[target_feature(enable = "neon,fp16")]
2092#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2093#[cfg(not(target_arch = "arm64ec"))]
2094pub fn vceqzh_f16(a: f16) -> u16 {
2095    vget_lane_u16::<0>(vceqz_f16(vdup_n_f16(a)))
2096}
2097#[doc = "Floating-point compare bitwise equal to zero"]
2098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"]
2099#[inline]
2100#[target_feature(enable = "neon")]
2101#[cfg_attr(test, assert_instr(fcmp))]
2102#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2103pub fn vceqzs_f32(a: f32) -> u32 {
2104    vget_lane_u32::<0>(vceqz_f32(vdup_n_f32(a)))
2105}
2106#[doc = "Floating-point compare bitwise equal to zero"]
2107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"]
2108#[inline]
2109#[target_feature(enable = "neon")]
2110#[cfg_attr(test, assert_instr(fcmp))]
2111#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2112pub fn vceqzd_f64(a: f64) -> u64 {
2113    vget_lane_u64::<0>(vceqz_f64(vdup_n_f64(a)))
2114}
2115#[doc = "Floating-point compare greater than or equal"]
2116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"]
2117#[inline]
2118#[target_feature(enable = "neon")]
2119#[cfg_attr(test, assert_instr(fcmge))]
2120#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2121pub fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
2122    unsafe { simd_ge(a, b) }
2123}
2124#[doc = "Floating-point compare greater than or equal"]
2125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)"]
2126#[inline]
2127#[target_feature(enable = "neon")]
2128#[cfg_attr(test, assert_instr(fcmge))]
2129#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2130pub fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
2131    unsafe { simd_ge(a, b) }
2132}
2133#[doc = "Compare signed greater than or equal"]
2134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)"]
2135#[inline]
2136#[target_feature(enable = "neon")]
2137#[cfg_attr(test, assert_instr(cmge))]
2138#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2139pub fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
2140    unsafe { simd_ge(a, b) }
2141}
2142#[doc = "Compare signed greater than or equal"]
2143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)"]
2144#[inline]
2145#[target_feature(enable = "neon")]
2146#[cfg_attr(test, assert_instr(cmge))]
2147#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2148pub fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
2149    unsafe { simd_ge(a, b) }
2150}
2151#[doc = "Compare unsigned greater than or equal"]
2152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)"]
2153#[inline]
2154#[target_feature(enable = "neon")]
2155#[cfg_attr(test, assert_instr(cmhs))]
2156#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2157pub fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
2158    unsafe { simd_ge(a, b) }
2159}
2160#[doc = "Compare unsigned greater than or equal"]
2161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)"]
2162#[inline]
2163#[target_feature(enable = "neon")]
2164#[cfg_attr(test, assert_instr(cmhs))]
2165#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2166pub fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
2167    unsafe { simd_ge(a, b) }
2168}
2169#[doc = "Floating-point compare greater than or equal"]
2170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64)"]
2171#[inline]
2172#[target_feature(enable = "neon")]
2173#[cfg_attr(test, assert_instr(fcmp))]
2174#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2175pub fn vcged_f64(a: f64, b: f64) -> u64 {
2176    vget_lane_u64::<0>(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)))
2177}
2178#[doc = "Floating-point compare greater than or equal"]
2179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"]
2180#[inline]
2181#[target_feature(enable = "neon")]
2182#[cfg_attr(test, assert_instr(fcmp))]
2183#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2184pub fn vcges_f32(a: f32, b: f32) -> u32 {
2185    vget_lane_u32::<0>(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)))
2186}
2187#[doc = "Compare greater than or equal"]
2188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"]
2189#[inline]
2190#[target_feature(enable = "neon")]
2191#[cfg_attr(test, assert_instr(cmp))]
2192#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2193pub fn vcged_s64(a: i64, b: i64) -> u64 {
2194    unsafe { transmute(vcge_s64(transmute(a), transmute(b))) }
2195}
2196#[doc = "Compare greater than or equal"]
2197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64)"]
2198#[inline]
2199#[target_feature(enable = "neon")]
2200#[cfg_attr(test, assert_instr(cmp))]
2201#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2202pub fn vcged_u64(a: u64, b: u64) -> u64 {
2203    unsafe { transmute(vcge_u64(transmute(a), transmute(b))) }
2204}
2205#[doc = "Floating-point compare greater than or equal"]
2206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeh_f16)"]
2207#[inline]
2208#[cfg_attr(test, assert_instr(fcmp))]
2209#[target_feature(enable = "neon,fp16")]
2210#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2211#[cfg(not(target_arch = "arm64ec"))]
2212pub fn vcgeh_f16(a: f16, b: f16) -> u16 {
2213    vget_lane_u16::<0>(vcge_f16(vdup_n_f16(a), vdup_n_f16(b)))
2214}
2215#[doc = "Floating-point compare greater than or equal to zero"]
2216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"]
2217#[inline]
2218#[target_feature(enable = "neon")]
2219#[cfg_attr(test, assert_instr(fcmge))]
2220#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2221pub fn vcgez_f32(a: float32x2_t) -> uint32x2_t {
2222    let b: f32x2 = f32x2::new(0.0, 0.0);
2223    unsafe { simd_ge(a, transmute(b)) }
2224}
2225#[doc = "Floating-point compare greater than or equal to zero"]
2226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32)"]
2227#[inline]
2228#[target_feature(enable = "neon")]
2229#[cfg_attr(test, assert_instr(fcmge))]
2230#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2231pub fn vcgezq_f32(a: float32x4_t) -> uint32x4_t {
2232    let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0);
2233    unsafe { simd_ge(a, transmute(b)) }
2234}
2235#[doc = "Floating-point compare greater than or equal to zero"]
2236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64)"]
2237#[inline]
2238#[target_feature(enable = "neon")]
2239#[cfg_attr(test, assert_instr(fcmge))]
2240#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2241pub fn vcgez_f64(a: float64x1_t) -> uint64x1_t {
2242    let b: f64 = 0.0;
2243    unsafe { simd_ge(a, transmute(b)) }
2244}
2245#[doc = "Floating-point compare greater than or equal to zero"]
2246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64)"]
2247#[inline]
2248#[target_feature(enable = "neon")]
2249#[cfg_attr(test, assert_instr(fcmge))]
2250#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2251pub fn vcgezq_f64(a: float64x2_t) -> uint64x2_t {
2252    let b: f64x2 = f64x2::new(0.0, 0.0);
2253    unsafe { simd_ge(a, transmute(b)) }
2254}
2255#[doc = "Compare signed greater than or equal to zero"]
2256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)"]
2257#[inline]
2258#[target_feature(enable = "neon")]
2259#[cfg_attr(test, assert_instr(cmge))]
2260#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2261pub fn vcgez_s8(a: int8x8_t) -> uint8x8_t {
2262    let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
2263    unsafe { simd_ge(a, transmute(b)) }
2264}
2265#[doc = "Compare signed greater than or equal to zero"]
2266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)"]
2267#[inline]
2268#[target_feature(enable = "neon")]
2269#[cfg_attr(test, assert_instr(cmge))]
2270#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2271pub fn vcgezq_s8(a: int8x16_t) -> uint8x16_t {
2272    let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
2273    unsafe { simd_ge(a, transmute(b)) }
2274}
2275#[doc = "Compare signed greater than or equal to zero"]
2276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)"]
2277#[inline]
2278#[target_feature(enable = "neon")]
2279#[cfg_attr(test, assert_instr(cmge))]
2280#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2281pub fn vcgez_s16(a: int16x4_t) -> uint16x4_t {
2282    let b: i16x4 = i16x4::new(0, 0, 0, 0);
2283    unsafe { simd_ge(a, transmute(b)) }
2284}
2285#[doc = "Compare signed greater than or equal to zero"]
2286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)"]
2287#[inline]
2288#[target_feature(enable = "neon")]
2289#[cfg_attr(test, assert_instr(cmge))]
2290#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2291pub fn vcgezq_s16(a: int16x8_t) -> uint16x8_t {
2292    let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
2293    unsafe { simd_ge(a, transmute(b)) }
2294}
2295#[doc = "Compare signed greater than or equal to zero"]
2296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)"]
2297#[inline]
2298#[target_feature(enable = "neon")]
2299#[cfg_attr(test, assert_instr(cmge))]
2300#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2301pub fn vcgez_s32(a: int32x2_t) -> uint32x2_t {
2302    let b: i32x2 = i32x2::new(0, 0);
2303    unsafe { simd_ge(a, transmute(b)) }
2304}
2305#[doc = "Compare signed greater than or equal to zero"]
2306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)"]
2307#[inline]
2308#[target_feature(enable = "neon")]
2309#[cfg_attr(test, assert_instr(cmge))]
2310#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2311pub fn vcgezq_s32(a: int32x4_t) -> uint32x4_t {
2312    let b: i32x4 = i32x4::new(0, 0, 0, 0);
2313    unsafe { simd_ge(a, transmute(b)) }
2314}
2315#[doc = "Compare signed greater than or equal to zero"]
2316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)"]
2317#[inline]
2318#[target_feature(enable = "neon")]
2319#[cfg_attr(test, assert_instr(cmge))]
2320#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2321pub fn vcgez_s64(a: int64x1_t) -> uint64x1_t {
2322    let b: i64x1 = i64x1::new(0);
2323    unsafe { simd_ge(a, transmute(b)) }
2324}
2325#[doc = "Compare signed greater than or equal to zero"]
2326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)"]
2327#[inline]
2328#[target_feature(enable = "neon")]
2329#[cfg_attr(test, assert_instr(cmge))]
2330#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2331pub fn vcgezq_s64(a: int64x2_t) -> uint64x2_t {
2332    let b: i64x2 = i64x2::new(0, 0);
2333    unsafe { simd_ge(a, transmute(b)) }
2334}
2335#[doc = "Floating-point compare greater than or equal to zero"]
2336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64)"]
2337#[inline]
2338#[target_feature(enable = "neon")]
2339#[cfg_attr(test, assert_instr(fcmp))]
2340#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2341pub fn vcgezd_f64(a: f64) -> u64 {
2342    vget_lane_u64::<0>(vcgez_f64(vdup_n_f64(a)))
2343}
2344#[doc = "Floating-point compare greater than or equal to zero"]
2345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"]
2346#[inline]
2347#[target_feature(enable = "neon")]
2348#[cfg_attr(test, assert_instr(fcmp))]
2349#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2350pub fn vcgezs_f32(a: f32) -> u32 {
2351    vget_lane_u32::<0>(vcgez_f32(vdup_n_f32(a)))
2352}
2353#[doc = "Compare signed greater than or equal to zero"]
2354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"]
2355#[inline]
2356#[target_feature(enable = "neon")]
2357#[cfg_attr(test, assert_instr(nop))]
2358#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2359pub fn vcgezd_s64(a: i64) -> u64 {
2360    unsafe { transmute(vcgez_s64(transmute(a))) }
2361}
2362#[doc = "Floating-point compare greater than or equal to zero"]
2363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezh_f16)"]
2364#[inline]
2365#[cfg_attr(test, assert_instr(fcmp))]
2366#[target_feature(enable = "neon,fp16")]
2367#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2368#[cfg(not(target_arch = "arm64ec"))]
2369pub fn vcgezh_f16(a: f16) -> u16 {
2370    vget_lane_u16::<0>(vcgez_f16(vdup_n_f16(a)))
2371}
2372#[doc = "Floating-point compare greater than"]
2373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"]
2374#[inline]
2375#[target_feature(enable = "neon")]
2376#[cfg_attr(test, assert_instr(fcmgt))]
2377#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2378pub fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
2379    unsafe { simd_gt(a, b) }
2380}
2381#[doc = "Floating-point compare greater than"]
2382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)"]
2383#[inline]
2384#[target_feature(enable = "neon")]
2385#[cfg_attr(test, assert_instr(fcmgt))]
2386#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2387pub fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
2388    unsafe { simd_gt(a, b) }
2389}
2390#[doc = "Compare signed greater than"]
2391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)"]
2392#[inline]
2393#[target_feature(enable = "neon")]
2394#[cfg_attr(test, assert_instr(cmgt))]
2395#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2396pub fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
2397    unsafe { simd_gt(a, b) }
2398}
2399#[doc = "Compare signed greater than"]
2400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)"]
2401#[inline]
2402#[target_feature(enable = "neon")]
2403#[cfg_attr(test, assert_instr(cmgt))]
2404#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2405pub fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
2406    unsafe { simd_gt(a, b) }
2407}
2408#[doc = "Compare unsigned greater than"]
2409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)"]
2410#[inline]
2411#[target_feature(enable = "neon")]
2412#[cfg_attr(test, assert_instr(cmhi))]
2413#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2414pub fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
2415    unsafe { simd_gt(a, b) }
2416}
2417#[doc = "Compare unsigned greater than"]
2418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)"]
2419#[inline]
2420#[target_feature(enable = "neon")]
2421#[cfg_attr(test, assert_instr(cmhi))]
2422#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2423pub fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
2424    unsafe { simd_gt(a, b) }
2425}
2426#[doc = "Floating-point compare greater than"]
2427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64)"]
2428#[inline]
2429#[target_feature(enable = "neon")]
2430#[cfg_attr(test, assert_instr(fcmp))]
2431#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2432pub fn vcgtd_f64(a: f64, b: f64) -> u64 {
2433    vget_lane_u64::<0>(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)))
2434}
2435#[doc = "Floating-point compare greater than"]
2436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"]
2437#[inline]
2438#[target_feature(enable = "neon")]
2439#[cfg_attr(test, assert_instr(fcmp))]
2440#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2441pub fn vcgts_f32(a: f32, b: f32) -> u32 {
2442    vget_lane_u32::<0>(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)))
2443}
2444#[doc = "Compare greater than"]
2445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"]
2446#[inline]
2447#[target_feature(enable = "neon")]
2448#[cfg_attr(test, assert_instr(cmp))]
2449#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2450pub fn vcgtd_s64(a: i64, b: i64) -> u64 {
2451    unsafe { transmute(vcgt_s64(transmute(a), transmute(b))) }
2452}
2453#[doc = "Compare greater than"]
2454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64)"]
2455#[inline]
2456#[target_feature(enable = "neon")]
2457#[cfg_attr(test, assert_instr(cmp))]
2458#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2459pub fn vcgtd_u64(a: u64, b: u64) -> u64 {
2460    unsafe { transmute(vcgt_u64(transmute(a), transmute(b))) }
2461}
2462#[doc = "Floating-point compare greater than"]
2463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgth_f16)"]
2464#[inline]
2465#[cfg_attr(test, assert_instr(fcmp))]
2466#[target_feature(enable = "neon,fp16")]
2467#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2468#[cfg(not(target_arch = "arm64ec"))]
2469pub fn vcgth_f16(a: f16, b: f16) -> u16 {
2470    vget_lane_u16::<0>(vcgt_f16(vdup_n_f16(a), vdup_n_f16(b)))
2471}
2472#[doc = "Floating-point compare greater than zero"]
2473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"]
2474#[inline]
2475#[target_feature(enable = "neon")]
2476#[cfg_attr(test, assert_instr(fcmgt))]
2477#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2478pub fn vcgtz_f32(a: float32x2_t) -> uint32x2_t {
2479    let b: f32x2 = f32x2::new(0.0, 0.0);
2480    unsafe { simd_gt(a, transmute(b)) }
2481}
2482#[doc = "Floating-point compare greater than zero"]
2483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32)"]
2484#[inline]
2485#[target_feature(enable = "neon")]
2486#[cfg_attr(test, assert_instr(fcmgt))]
2487#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2488pub fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t {
2489    let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0);
2490    unsafe { simd_gt(a, transmute(b)) }
2491}
2492#[doc = "Floating-point compare greater than zero"]
2493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64)"]
2494#[inline]
2495#[target_feature(enable = "neon")]
2496#[cfg_attr(test, assert_instr(fcmgt))]
2497#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2498pub fn vcgtz_f64(a: float64x1_t) -> uint64x1_t {
2499    let b: f64 = 0.0;
2500    unsafe { simd_gt(a, transmute(b)) }
2501}
2502#[doc = "Floating-point compare greater than zero"]
2503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64)"]
2504#[inline]
2505#[target_feature(enable = "neon")]
2506#[cfg_attr(test, assert_instr(fcmgt))]
2507#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2508pub fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t {
2509    let b: f64x2 = f64x2::new(0.0, 0.0);
2510    unsafe { simd_gt(a, transmute(b)) }
2511}
2512#[doc = "Compare signed greater than zero"]
2513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8)"]
2514#[inline]
2515#[target_feature(enable = "neon")]
2516#[cfg_attr(test, assert_instr(cmgt))]
2517#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2518pub fn vcgtz_s8(a: int8x8_t) -> uint8x8_t {
2519    let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
2520    unsafe { simd_gt(a, transmute(b)) }
2521}
2522#[doc = "Compare signed greater than zero"]
2523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8)"]
2524#[inline]
2525#[target_feature(enable = "neon")]
2526#[cfg_attr(test, assert_instr(cmgt))]
2527#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2528pub fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t {
2529    let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
2530    unsafe { simd_gt(a, transmute(b)) }
2531}
2532#[doc = "Compare signed greater than zero"]
2533#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16)"]
2534#[inline]
2535#[target_feature(enable = "neon")]
2536#[cfg_attr(test, assert_instr(cmgt))]
2537#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2538pub fn vcgtz_s16(a: int16x4_t) -> uint16x4_t {
2539    let b: i16x4 = i16x4::new(0, 0, 0, 0);
2540    unsafe { simd_gt(a, transmute(b)) }
2541}
2542#[doc = "Compare signed greater than zero"]
2543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16)"]
2544#[inline]
2545#[target_feature(enable = "neon")]
2546#[cfg_attr(test, assert_instr(cmgt))]
2547#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2548pub fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t {
2549    let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
2550    unsafe { simd_gt(a, transmute(b)) }
2551}
2552#[doc = "Compare signed greater than zero"]
2553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32)"]
2554#[inline]
2555#[target_feature(enable = "neon")]
2556#[cfg_attr(test, assert_instr(cmgt))]
2557#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2558pub fn vcgtz_s32(a: int32x2_t) -> uint32x2_t {
2559    let b: i32x2 = i32x2::new(0, 0);
2560    unsafe { simd_gt(a, transmute(b)) }
2561}
2562#[doc = "Compare signed greater than zero"]
2563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32)"]
2564#[inline]
2565#[target_feature(enable = "neon")]
2566#[cfg_attr(test, assert_instr(cmgt))]
2567#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2568pub fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t {
2569    let b: i32x4 = i32x4::new(0, 0, 0, 0);
2570    unsafe { simd_gt(a, transmute(b)) }
2571}
2572#[doc = "Compare signed greater than zero"]
2573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64)"]
2574#[inline]
2575#[target_feature(enable = "neon")]
2576#[cfg_attr(test, assert_instr(cmgt))]
2577#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2578pub fn vcgtz_s64(a: int64x1_t) -> uint64x1_t {
2579    let b: i64x1 = i64x1::new(0);
2580    unsafe { simd_gt(a, transmute(b)) }
2581}
2582#[doc = "Compare signed greater than zero"]
2583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64)"]
2584#[inline]
2585#[target_feature(enable = "neon")]
2586#[cfg_attr(test, assert_instr(cmgt))]
2587#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2588pub fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t {
2589    let b: i64x2 = i64x2::new(0, 0);
2590    unsafe { simd_gt(a, transmute(b)) }
2591}
2592#[doc = "Floating-point compare greater than zero"]
2593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64)"]
2594#[inline]
2595#[target_feature(enable = "neon")]
2596#[cfg_attr(test, assert_instr(fcmp))]
2597#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2598pub fn vcgtzd_f64(a: f64) -> u64 {
2599    vget_lane_u64::<0>(vcgtz_f64(vdup_n_f64(a)))
2600}
2601#[doc = "Floating-point compare greater than zero"]
2602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"]
2603#[inline]
2604#[target_feature(enable = "neon")]
2605#[cfg_attr(test, assert_instr(fcmp))]
2606#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2607pub fn vcgtzs_f32(a: f32) -> u32 {
2608    vget_lane_u32::<0>(vcgtz_f32(vdup_n_f32(a)))
2609}
2610#[doc = "Compare signed greater than zero"]
2611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"]
2612#[inline]
2613#[target_feature(enable = "neon")]
2614#[cfg_attr(test, assert_instr(cmp))]
2615#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2616pub fn vcgtzd_s64(a: i64) -> u64 {
2617    unsafe { transmute(vcgtz_s64(transmute(a))) }
2618}
2619#[doc = "Floating-point compare greater than zero"]
2620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzh_f16)"]
2621#[inline]
2622#[cfg_attr(test, assert_instr(fcmp))]
2623#[target_feature(enable = "neon,fp16")]
2624#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2625#[cfg(not(target_arch = "arm64ec"))]
2626pub fn vcgtzh_f16(a: f16) -> u16 {
2627    vget_lane_u16::<0>(vcgtz_f16(vdup_n_f16(a)))
2628}
2629#[doc = "Floating-point compare less than or equal"]
2630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"]
2631#[inline]
2632#[target_feature(enable = "neon")]
2633#[cfg_attr(test, assert_instr(fcmge))]
2634#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2635pub fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
2636    unsafe { simd_le(a, b) }
2637}
2638#[doc = "Floating-point compare less than or equal"]
2639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)"]
2640#[inline]
2641#[target_feature(enable = "neon")]
2642#[cfg_attr(test, assert_instr(fcmge))]
2643#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2644pub fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
2645    unsafe { simd_le(a, b) }
2646}
2647#[doc = "Compare signed less than or equal"]
2648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)"]
2649#[inline]
2650#[target_feature(enable = "neon")]
2651#[cfg_attr(test, assert_instr(cmge))]
2652#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2653pub fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
2654    unsafe { simd_le(a, b) }
2655}
2656#[doc = "Compare signed less than or equal"]
2657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)"]
2658#[inline]
2659#[target_feature(enable = "neon")]
2660#[cfg_attr(test, assert_instr(cmge))]
2661#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2662pub fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
2663    unsafe { simd_le(a, b) }
2664}
2665#[doc = "Compare unsigned less than or equal"]
2666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)"]
2667#[inline]
2668#[target_feature(enable = "neon")]
2669#[cfg_attr(test, assert_instr(cmhs))]
2670#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2671pub fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
2672    unsafe { simd_le(a, b) }
2673}
2674#[doc = "Compare unsigned less than or equal"]
2675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)"]
2676#[inline]
2677#[target_feature(enable = "neon")]
2678#[cfg_attr(test, assert_instr(cmhs))]
2679#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2680pub fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
2681    unsafe { simd_le(a, b) }
2682}
2683#[doc = "Floating-point compare less than or equal"]
2684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64)"]
2685#[inline]
2686#[target_feature(enable = "neon")]
2687#[cfg_attr(test, assert_instr(fcmp))]
2688#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2689pub fn vcled_f64(a: f64, b: f64) -> u64 {
2690    vget_lane_u64::<0>(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)))
2691}
2692#[doc = "Floating-point compare less than or equal"]
2693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"]
2694#[inline]
2695#[target_feature(enable = "neon")]
2696#[cfg_attr(test, assert_instr(fcmp))]
2697#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2698pub fn vcles_f32(a: f32, b: f32) -> u32 {
2699    vget_lane_u32::<0>(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)))
2700}
2701#[doc = "Compare less than or equal"]
2702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"]
2703#[inline]
2704#[target_feature(enable = "neon")]
2705#[cfg_attr(test, assert_instr(cmp))]
2706#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2707pub fn vcled_u64(a: u64, b: u64) -> u64 {
2708    unsafe { transmute(vcle_u64(transmute(a), transmute(b))) }
2709}
2710#[doc = "Compare less than or equal"]
2711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64)"]
2712#[inline]
2713#[target_feature(enable = "neon")]
2714#[cfg_attr(test, assert_instr(cmp))]
2715#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2716pub fn vcled_s64(a: i64, b: i64) -> u64 {
2717    unsafe { transmute(vcle_s64(transmute(a), transmute(b))) }
2718}
2719#[doc = "Floating-point compare less than or equal"]
2720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleh_f16)"]
2721#[inline]
2722#[cfg_attr(test, assert_instr(fcmp))]
2723#[target_feature(enable = "neon,fp16")]
2724#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2725#[cfg(not(target_arch = "arm64ec"))]
2726pub fn vcleh_f16(a: f16, b: f16) -> u16 {
2727    vget_lane_u16::<0>(vcle_f16(vdup_n_f16(a), vdup_n_f16(b)))
2728}
2729#[doc = "Floating-point compare less than or equal to zero"]
2730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"]
2731#[inline]
2732#[target_feature(enable = "neon")]
2733#[cfg_attr(test, assert_instr(fcmle))]
2734#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2735pub fn vclez_f32(a: float32x2_t) -> uint32x2_t {
2736    let b: f32x2 = f32x2::new(0.0, 0.0);
2737    unsafe { simd_le(a, transmute(b)) }
2738}
2739#[doc = "Floating-point compare less than or equal to zero"]
2740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32)"]
2741#[inline]
2742#[target_feature(enable = "neon")]
2743#[cfg_attr(test, assert_instr(fcmle))]
2744#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2745pub fn vclezq_f32(a: float32x4_t) -> uint32x4_t {
2746    let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0);
2747    unsafe { simd_le(a, transmute(b)) }
2748}
2749#[doc = "Floating-point compare less than or equal to zero"]
2750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64)"]
2751#[inline]
2752#[target_feature(enable = "neon")]
2753#[cfg_attr(test, assert_instr(fcmle))]
2754#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2755pub fn vclez_f64(a: float64x1_t) -> uint64x1_t {
2756    let b: f64 = 0.0;
2757    unsafe { simd_le(a, transmute(b)) }
2758}
2759#[doc = "Floating-point compare less than or equal to zero"]
2760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64)"]
2761#[inline]
2762#[target_feature(enable = "neon")]
2763#[cfg_attr(test, assert_instr(fcmle))]
2764#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2765pub fn vclezq_f64(a: float64x2_t) -> uint64x2_t {
2766    let b: f64x2 = f64x2::new(0.0, 0.0);
2767    unsafe { simd_le(a, transmute(b)) }
2768}
2769#[doc = "Compare signed less than or equal to zero"]
2770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)"]
2771#[inline]
2772#[target_feature(enable = "neon")]
2773#[cfg_attr(test, assert_instr(cmle))]
2774#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2775pub fn vclez_s8(a: int8x8_t) -> uint8x8_t {
2776    let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
2777    unsafe { simd_le(a, transmute(b)) }
2778}
2779#[doc = "Compare signed less than or equal to zero"]
2780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)"]
2781#[inline]
2782#[target_feature(enable = "neon")]
2783#[cfg_attr(test, assert_instr(cmle))]
2784#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2785pub fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
2786    let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
2787    unsafe { simd_le(a, transmute(b)) }
2788}
2789#[doc = "Compare signed less than or equal to zero"]
2790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)"]
2791#[inline]
2792#[target_feature(enable = "neon")]
2793#[cfg_attr(test, assert_instr(cmle))]
2794#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2795pub fn vclez_s16(a: int16x4_t) -> uint16x4_t {
2796    let b: i16x4 = i16x4::new(0, 0, 0, 0);
2797    unsafe { simd_le(a, transmute(b)) }
2798}
2799#[doc = "Compare signed less than or equal to zero"]
2800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)"]
2801#[inline]
2802#[target_feature(enable = "neon")]
2803#[cfg_attr(test, assert_instr(cmle))]
2804#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2805pub fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
2806    let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
2807    unsafe { simd_le(a, transmute(b)) }
2808}
2809#[doc = "Compare signed less than or equal to zero"]
2810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)"]
2811#[inline]
2812#[target_feature(enable = "neon")]
2813#[cfg_attr(test, assert_instr(cmle))]
2814#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2815pub fn vclez_s32(a: int32x2_t) -> uint32x2_t {
2816    let b: i32x2 = i32x2::new(0, 0);
2817    unsafe { simd_le(a, transmute(b)) }
2818}
2819#[doc = "Compare signed less than or equal to zero"]
2820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)"]
2821#[inline]
2822#[target_feature(enable = "neon")]
2823#[cfg_attr(test, assert_instr(cmle))]
2824#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2825pub fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
2826    let b: i32x4 = i32x4::new(0, 0, 0, 0);
2827    unsafe { simd_le(a, transmute(b)) }
2828}
2829#[doc = "Compare signed less than or equal to zero"]
2830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)"]
2831#[inline]
2832#[target_feature(enable = "neon")]
2833#[cfg_attr(test, assert_instr(cmle))]
2834#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2835pub fn vclez_s64(a: int64x1_t) -> uint64x1_t {
2836    let b: i64x1 = i64x1::new(0);
2837    unsafe { simd_le(a, transmute(b)) }
2838}
2839#[doc = "Compare signed less than or equal to zero"]
2840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)"]
2841#[inline]
2842#[target_feature(enable = "neon")]
2843#[cfg_attr(test, assert_instr(cmle))]
2844#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2845pub fn vclezq_s64(a: int64x2_t) -> uint64x2_t {
2846    let b: i64x2 = i64x2::new(0, 0);
2847    unsafe { simd_le(a, transmute(b)) }
2848}
2849#[doc = "Floating-point compare less than or equal to zero"]
2850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64)"]
2851#[inline]
2852#[target_feature(enable = "neon")]
2853#[cfg_attr(test, assert_instr(fcmp))]
2854#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2855pub fn vclezd_f64(a: f64) -> u64 {
2856    vget_lane_u64::<0>(vclez_f64(vdup_n_f64(a)))
2857}
2858#[doc = "Floating-point compare less than or equal to zero"]
2859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"]
2860#[inline]
2861#[target_feature(enable = "neon")]
2862#[cfg_attr(test, assert_instr(fcmp))]
2863#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2864pub fn vclezs_f32(a: f32) -> u32 {
2865    vget_lane_u32::<0>(vclez_f32(vdup_n_f32(a)))
2866}
2867#[doc = "Compare less than or equal to zero"]
2868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"]
2869#[inline]
2870#[target_feature(enable = "neon")]
2871#[cfg_attr(test, assert_instr(cmp))]
2872#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2873pub fn vclezd_s64(a: i64) -> u64 {
2874    unsafe { transmute(vclez_s64(transmute(a))) }
2875}
2876#[doc = "Floating-point compare less than or equal to zero"]
2877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezh_f16)"]
2878#[inline]
2879#[cfg_attr(test, assert_instr(fcmp))]
2880#[target_feature(enable = "neon,fp16")]
2881#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2882#[cfg(not(target_arch = "arm64ec"))]
2883pub fn vclezh_f16(a: f16) -> u16 {
2884    vget_lane_u16::<0>(vclez_f16(vdup_n_f16(a)))
2885}
2886#[doc = "Floating-point compare less than"]
2887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"]
2888#[inline]
2889#[target_feature(enable = "neon")]
2890#[cfg_attr(test, assert_instr(fcmgt))]
2891#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2892pub fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
2893    unsafe { simd_lt(a, b) }
2894}
2895#[doc = "Floating-point compare less than"]
2896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)"]
2897#[inline]
2898#[target_feature(enable = "neon")]
2899#[cfg_attr(test, assert_instr(fcmgt))]
2900#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2901pub fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
2902    unsafe { simd_lt(a, b) }
2903}
2904#[doc = "Compare signed less than"]
2905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)"]
2906#[inline]
2907#[target_feature(enable = "neon")]
2908#[cfg_attr(test, assert_instr(cmgt))]
2909#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2910pub fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
2911    unsafe { simd_lt(a, b) }
2912}
2913#[doc = "Compare signed less than"]
2914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)"]
2915#[inline]
2916#[target_feature(enable = "neon")]
2917#[cfg_attr(test, assert_instr(cmgt))]
2918#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2919pub fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
2920    unsafe { simd_lt(a, b) }
2921}
2922#[doc = "Compare unsigned less than"]
2923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)"]
2924#[inline]
2925#[target_feature(enable = "neon")]
2926#[cfg_attr(test, assert_instr(cmhi))]
2927#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2928pub fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
2929    unsafe { simd_lt(a, b) }
2930}
2931#[doc = "Compare unsigned less than"]
2932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)"]
2933#[inline]
2934#[target_feature(enable = "neon")]
2935#[cfg_attr(test, assert_instr(cmhi))]
2936#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2937pub fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
2938    unsafe { simd_lt(a, b) }
2939}
2940#[doc = "Compare less than"]
2941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64)"]
2942#[inline]
2943#[target_feature(enable = "neon")]
2944#[cfg_attr(test, assert_instr(cmp))]
2945#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2946pub fn vcltd_u64(a: u64, b: u64) -> u64 {
2947    unsafe { transmute(vclt_u64(transmute(a), transmute(b))) }
2948}
2949#[doc = "Compare less than"]
2950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64)"]
2951#[inline]
2952#[target_feature(enable = "neon")]
2953#[cfg_attr(test, assert_instr(cmp))]
2954#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2955pub fn vcltd_s64(a: i64, b: i64) -> u64 {
2956    unsafe { transmute(vclt_s64(transmute(a), transmute(b))) }
2957}
2958#[doc = "Floating-point compare less than"]
2959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclth_f16)"]
2960#[inline]
2961#[cfg_attr(test, assert_instr(fcmp))]
2962#[target_feature(enable = "neon,fp16")]
2963#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2964#[cfg(not(target_arch = "arm64ec"))]
2965pub fn vclth_f16(a: f16, b: f16) -> u16 {
2966    vget_lane_u16::<0>(vclt_f16(vdup_n_f16(a), vdup_n_f16(b)))
2967}
2968#[doc = "Floating-point compare less than"]
2969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"]
2970#[inline]
2971#[target_feature(enable = "neon")]
2972#[cfg_attr(test, assert_instr(fcmp))]
2973#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2974pub fn vclts_f32(a: f32, b: f32) -> u32 {
2975    vget_lane_u32::<0>(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)))
2976}
2977#[doc = "Floating-point compare less than"]
2978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"]
2979#[inline]
2980#[target_feature(enable = "neon")]
2981#[cfg_attr(test, assert_instr(fcmp))]
2982#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2983pub fn vcltd_f64(a: f64, b: f64) -> u64 {
2984    vget_lane_u64::<0>(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)))
2985}
2986#[doc = "Floating-point compare less than zero"]
2987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"]
2988#[inline]
2989#[target_feature(enable = "neon")]
2990#[cfg_attr(test, assert_instr(fcmlt))]
2991#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2992pub fn vcltz_f32(a: float32x2_t) -> uint32x2_t {
2993    let b: f32x2 = f32x2::new(0.0, 0.0);
2994    unsafe { simd_lt(a, transmute(b)) }
2995}
2996#[doc = "Floating-point compare less than zero"]
2997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32)"]
2998#[inline]
2999#[target_feature(enable = "neon")]
3000#[cfg_attr(test, assert_instr(fcmlt))]
3001#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3002pub fn vcltzq_f32(a: float32x4_t) -> uint32x4_t {
3003    let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0);
3004    unsafe { simd_lt(a, transmute(b)) }
3005}
3006#[doc = "Floating-point compare less than zero"]
3007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64)"]
3008#[inline]
3009#[target_feature(enable = "neon")]
3010#[cfg_attr(test, assert_instr(fcmlt))]
3011#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3012pub fn vcltz_f64(a: float64x1_t) -> uint64x1_t {
3013    let b: f64 = 0.0;
3014    unsafe { simd_lt(a, transmute(b)) }
3015}
3016#[doc = "Floating-point compare less than zero"]
3017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64)"]
3018#[inline]
3019#[target_feature(enable = "neon")]
3020#[cfg_attr(test, assert_instr(fcmlt))]
3021#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3022pub fn vcltzq_f64(a: float64x2_t) -> uint64x2_t {
3023    let b: f64x2 = f64x2::new(0.0, 0.0);
3024    unsafe { simd_lt(a, transmute(b)) }
3025}
3026#[doc = "Compare signed less than zero"]
3027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8)"]
3028#[inline]
3029#[target_feature(enable = "neon")]
3030#[cfg_attr(test, assert_instr(cmlt))]
3031#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3032pub fn vcltz_s8(a: int8x8_t) -> uint8x8_t {
3033    let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
3034    unsafe { simd_lt(a, transmute(b)) }
3035}
3036#[doc = "Compare signed less than zero"]
3037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8)"]
3038#[inline]
3039#[target_feature(enable = "neon")]
3040#[cfg_attr(test, assert_instr(cmlt))]
3041#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3042pub fn vcltzq_s8(a: int8x16_t) -> uint8x16_t {
3043    let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
3044    unsafe { simd_lt(a, transmute(b)) }
3045}
3046#[doc = "Compare signed less than zero"]
3047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16)"]
3048#[inline]
3049#[target_feature(enable = "neon")]
3050#[cfg_attr(test, assert_instr(cmlt))]
3051#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3052pub fn vcltz_s16(a: int16x4_t) -> uint16x4_t {
3053    let b: i16x4 = i16x4::new(0, 0, 0, 0);
3054    unsafe { simd_lt(a, transmute(b)) }
3055}
3056#[doc = "Compare signed less than zero"]
3057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16)"]
3058#[inline]
3059#[target_feature(enable = "neon")]
3060#[cfg_attr(test, assert_instr(cmlt))]
3061#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3062pub fn vcltzq_s16(a: int16x8_t) -> uint16x8_t {
3063    let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
3064    unsafe { simd_lt(a, transmute(b)) }
3065}
3066#[doc = "Compare signed less than zero"]
3067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32)"]
3068#[inline]
3069#[target_feature(enable = "neon")]
3070#[cfg_attr(test, assert_instr(cmlt))]
3071#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3072pub fn vcltz_s32(a: int32x2_t) -> uint32x2_t {
3073    let b: i32x2 = i32x2::new(0, 0);
3074    unsafe { simd_lt(a, transmute(b)) }
3075}
3076#[doc = "Compare signed less than zero"]
3077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32)"]
3078#[inline]
3079#[target_feature(enable = "neon")]
3080#[cfg_attr(test, assert_instr(cmlt))]
3081#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3082pub fn vcltzq_s32(a: int32x4_t) -> uint32x4_t {
3083    let b: i32x4 = i32x4::new(0, 0, 0, 0);
3084    unsafe { simd_lt(a, transmute(b)) }
3085}
3086#[doc = "Compare signed less than zero"]
3087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64)"]
3088#[inline]
3089#[target_feature(enable = "neon")]
3090#[cfg_attr(test, assert_instr(cmlt))]
3091#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3092pub fn vcltz_s64(a: int64x1_t) -> uint64x1_t {
3093    let b: i64x1 = i64x1::new(0);
3094    unsafe { simd_lt(a, transmute(b)) }
3095}
3096#[doc = "Compare signed less than zero"]
3097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64)"]
3098#[inline]
3099#[target_feature(enable = "neon")]
3100#[cfg_attr(test, assert_instr(cmlt))]
3101#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3102pub fn vcltzq_s64(a: int64x2_t) -> uint64x2_t {
3103    let b: i64x2 = i64x2::new(0, 0);
3104    unsafe { simd_lt(a, transmute(b)) }
3105}
3106#[doc = "Floating-point compare less than zero"]
3107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64)"]
3108#[inline]
3109#[target_feature(enable = "neon")]
3110#[cfg_attr(test, assert_instr(fcmp))]
3111#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3112pub fn vcltzd_f64(a: f64) -> u64 {
3113    vget_lane_u64::<0>(vcltz_f64(vdup_n_f64(a)))
3114}
3115#[doc = "Floating-point compare less than zero"]
3116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"]
3117#[inline]
3118#[target_feature(enable = "neon")]
3119#[cfg_attr(test, assert_instr(fcmp))]
3120#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3121pub fn vcltzs_f32(a: f32) -> u32 {
3122    vget_lane_u32::<0>(vcltz_f32(vdup_n_f32(a)))
3123}
3124#[doc = "Compare less than zero"]
3125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"]
3126#[inline]
3127#[target_feature(enable = "neon")]
3128#[cfg_attr(test, assert_instr(asr))]
3129#[stable(feature = "neon_intrinsics", since = "1.59.0")]
3130pub fn vcltzd_s64(a: i64) -> u64 {
3131    unsafe { transmute(vcltz_s64(transmute(a))) }
3132}
3133#[doc = "Floating-point compare less than zero"]
3134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzh_f16)"]
3135#[inline]
3136#[cfg_attr(test, assert_instr(fcmp))]
3137#[target_feature(enable = "neon,fp16")]
3138#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3139#[cfg(not(target_arch = "arm64ec"))]
3140pub fn vcltzh_f16(a: f16) -> u16 {
3141    vget_lane_u16::<0>(vcltz_f16(vdup_n_f16(a)))
3142}
3143#[doc = "Floating-point complex multiply accumulate"]
3144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"]
3145#[inline]
3146#[cfg(target_endian = "little")]
3147#[target_feature(enable = "neon,fcma")]
3148#[target_feature(enable = "neon,fp16")]
3149#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3150#[cfg(not(target_arch = "arm64ec"))]
3151#[cfg_attr(test, assert_instr(fcmla))]
3152pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3153    unsafe extern "unadjusted" {
3154        #[cfg_attr(
3155            any(target_arch = "aarch64", target_arch = "arm64ec"),
3156            link_name = "llvm.aarch64.neon.vcmla.rot0.v4f16"
3157        )]
3158        fn _vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
3159    }
3160    unsafe { _vcmla_f16(a, b, c) }
3161}
3162#[doc = "Floating-point complex multiply accumulate"]
3163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"]
3164#[inline]
3165#[cfg(target_endian = "big")]
3166#[target_feature(enable = "neon,fcma")]
3167#[target_feature(enable = "neon,fp16")]
3168#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3169#[cfg(not(target_arch = "arm64ec"))]
3170#[cfg_attr(test, assert_instr(fcmla))]
3171pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3172    unsafe extern "unadjusted" {
3173        #[cfg_attr(
3174            any(target_arch = "aarch64", target_arch = "arm64ec"),
3175            link_name = "llvm.aarch64.neon.vcmla.rot0.v4f16"
3176        )]
3177        fn _vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
3178    }
3179    unsafe {
3180        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
3181        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
3182        let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
3183        let ret_val: float16x4_t = _vcmla_f16(a, b, c);
3184        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
3185    }
3186}
3187#[doc = "Floating-point complex multiply accumulate"]
3188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"]
3189#[inline]
3190#[cfg(target_endian = "little")]
3191#[target_feature(enable = "neon,fcma")]
3192#[target_feature(enable = "neon,fp16")]
3193#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3194#[cfg(not(target_arch = "arm64ec"))]
3195#[cfg_attr(test, assert_instr(fcmla))]
3196pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3197    unsafe extern "unadjusted" {
3198        #[cfg_attr(
3199            any(target_arch = "aarch64", target_arch = "arm64ec"),
3200            link_name = "llvm.aarch64.neon.vcmla.rot0.v8f16"
3201        )]
3202        fn _vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
3203    }
3204    unsafe { _vcmlaq_f16(a, b, c) }
3205}
3206#[doc = "Floating-point complex multiply accumulate"]
3207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"]
3208#[inline]
3209#[cfg(target_endian = "big")]
3210#[target_feature(enable = "neon,fcma")]
3211#[target_feature(enable = "neon,fp16")]
3212#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3213#[cfg(not(target_arch = "arm64ec"))]
3214#[cfg_attr(test, assert_instr(fcmla))]
3215pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3216    unsafe extern "unadjusted" {
3217        #[cfg_attr(
3218            any(target_arch = "aarch64", target_arch = "arm64ec"),
3219            link_name = "llvm.aarch64.neon.vcmla.rot0.v8f16"
3220        )]
3221        fn _vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
3222    }
3223    unsafe {
3224        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
3225        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
3226        let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
3227        let ret_val: float16x8_t = _vcmlaq_f16(a, b, c);
3228        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
3229    }
3230}
3231#[doc = "Floating-point complex multiply accumulate"]
3232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"]
3233#[inline]
3234#[cfg(target_endian = "little")]
3235#[target_feature(enable = "neon,fcma")]
3236#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3237#[cfg_attr(test, assert_instr(fcmla))]
3238pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3239    unsafe extern "unadjusted" {
3240        #[cfg_attr(
3241            any(target_arch = "aarch64", target_arch = "arm64ec"),
3242            link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32"
3243        )]
3244        fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
3245    }
3246    unsafe { _vcmla_f32(a, b, c) }
3247}
3248#[doc = "Floating-point complex multiply accumulate"]
3249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"]
3250#[inline]
3251#[cfg(target_endian = "big")]
3252#[target_feature(enable = "neon,fcma")]
3253#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3254#[cfg_attr(test, assert_instr(fcmla))]
3255pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3256    unsafe extern "unadjusted" {
3257        #[cfg_attr(
3258            any(target_arch = "aarch64", target_arch = "arm64ec"),
3259            link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32"
3260        )]
3261        fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
3262    }
3263    unsafe {
3264        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
3265        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
3266        let c: float32x2_t = simd_shuffle!(c, c, [1, 0]);
3267        let ret_val: float32x2_t = _vcmla_f32(a, b, c);
3268        simd_shuffle!(ret_val, ret_val, [1, 0])
3269    }
3270}
3271#[doc = "Floating-point complex multiply accumulate"]
3272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"]
3273#[inline]
3274#[cfg(target_endian = "little")]
3275#[target_feature(enable = "neon,fcma")]
3276#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3277#[cfg_attr(test, assert_instr(fcmla))]
3278pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
3279    unsafe extern "unadjusted" {
3280        #[cfg_attr(
3281            any(target_arch = "aarch64", target_arch = "arm64ec"),
3282            link_name = "llvm.aarch64.neon.vcmla.rot0.v4f32"
3283        )]
3284        fn _vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
3285    }
3286    unsafe { _vcmlaq_f32(a, b, c) }
3287}
3288#[doc = "Floating-point complex multiply accumulate"]
3289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"]
3290#[inline]
3291#[cfg(target_endian = "big")]
3292#[target_feature(enable = "neon,fcma")]
3293#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3294#[cfg_attr(test, assert_instr(fcmla))]
3295pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
3296    unsafe extern "unadjusted" {
3297        #[cfg_attr(
3298            any(target_arch = "aarch64", target_arch = "arm64ec"),
3299            link_name = "llvm.aarch64.neon.vcmla.rot0.v4f32"
3300        )]
3301        fn _vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
3302    }
3303    unsafe {
3304        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
3305        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
3306        let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
3307        let ret_val: float32x4_t = _vcmlaq_f32(a, b, c);
3308        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
3309    }
3310}
3311#[doc = "Floating-point complex multiply accumulate"]
3312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"]
3313#[inline]
3314#[cfg(target_endian = "little")]
3315#[target_feature(enable = "neon,fcma")]
3316#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3317#[cfg_attr(test, assert_instr(fcmla))]
3318pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
3319    unsafe extern "unadjusted" {
3320        #[cfg_attr(
3321            any(target_arch = "aarch64", target_arch = "arm64ec"),
3322            link_name = "llvm.aarch64.neon.vcmla.rot0.v2f64"
3323        )]
3324        fn _vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t;
3325    }
3326    unsafe { _vcmlaq_f64(a, b, c) }
3327}
3328#[doc = "Floating-point complex multiply accumulate"]
3329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"]
3330#[inline]
3331#[cfg(target_endian = "big")]
3332#[target_feature(enable = "neon,fcma")]
3333#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3334#[cfg_attr(test, assert_instr(fcmla))]
3335pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
3336    unsafe extern "unadjusted" {
3337        #[cfg_attr(
3338            any(target_arch = "aarch64", target_arch = "arm64ec"),
3339            link_name = "llvm.aarch64.neon.vcmla.rot0.v2f64"
3340        )]
3341        fn _vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t;
3342    }
3343    unsafe {
3344        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
3345        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
3346        let c: float64x2_t = simd_shuffle!(c, c, [1, 0]);
3347        let ret_val: float64x2_t = _vcmlaq_f64(a, b, c);
3348        simd_shuffle!(ret_val, ret_val, [1, 0])
3349    }
3350}
3351#[doc = "Floating-point complex multiply accumulate"]
3352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f16)"]
3353#[inline]
3354#[target_feature(enable = "neon,fcma")]
3355#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3356#[rustc_legacy_const_generics(3)]
3357#[target_feature(enable = "neon,fp16")]
3358#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3359#[cfg(not(target_arch = "arm64ec"))]
3360pub fn vcmla_lane_f16<const LANE: i32>(
3361    a: float16x4_t,
3362    b: float16x4_t,
3363    c: float16x4_t,
3364) -> float16x4_t {
3365    static_assert_uimm_bits!(LANE, 1);
3366    let c = vreinterpret_u32_f16(c);
3367    let c = vdup_lane_u32::<LANE>(c);
3368    let c = vreinterpret_f16_u32(c);
3369    vcmla_f16(a, b, c)
3370}
3371#[doc = "Floating-point complex multiply accumulate"]
3372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f16)"]
3373#[inline]
3374#[target_feature(enable = "neon,fcma")]
3375#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3376#[rustc_legacy_const_generics(3)]
3377#[target_feature(enable = "neon,fp16")]
3378#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3379#[cfg(not(target_arch = "arm64ec"))]
3380pub fn vcmlaq_lane_f16<const LANE: i32>(
3381    a: float16x8_t,
3382    b: float16x8_t,
3383    c: float16x4_t,
3384) -> float16x8_t {
3385    static_assert_uimm_bits!(LANE, 1);
3386    let c = vreinterpret_u32_f16(c);
3387    let c = vdupq_lane_u32::<LANE>(c);
3388    let c = vreinterpretq_f16_u32(c);
3389    vcmlaq_f16(a, b, c)
3390}
3391#[doc = "Floating-point complex multiply accumulate"]
3392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"]
3393#[inline]
3394#[target_feature(enable = "neon,fcma")]
3395#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3396#[rustc_legacy_const_generics(3)]
3397#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3398pub fn vcmla_lane_f32<const LANE: i32>(
3399    a: float32x2_t,
3400    b: float32x2_t,
3401    c: float32x2_t,
3402) -> float32x2_t {
3403    static_assert!(LANE == 0);
3404    let c = vreinterpret_u64_f32(c);
3405    let c = vdup_lane_u64::<LANE>(c);
3406    let c = vreinterpret_f32_u64(c);
3407    vcmla_f32(a, b, c)
3408}
3409#[doc = "Floating-point complex multiply accumulate"]
3410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"]
3411#[inline]
3412#[target_feature(enable = "neon,fcma")]
3413#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3414#[rustc_legacy_const_generics(3)]
3415#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3416pub fn vcmlaq_lane_f32<const LANE: i32>(
3417    a: float32x4_t,
3418    b: float32x4_t,
3419    c: float32x2_t,
3420) -> float32x4_t {
3421    static_assert!(LANE == 0);
3422    let c = vreinterpret_u64_f32(c);
3423    let c = vdupq_lane_u64::<LANE>(c);
3424    let c = vreinterpretq_f32_u64(c);
3425    vcmlaq_f32(a, b, c)
3426}
3427#[doc = "Floating-point complex multiply accumulate"]
3428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f16)"]
3429#[inline]
3430#[target_feature(enable = "neon,fcma")]
3431#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3432#[rustc_legacy_const_generics(3)]
3433#[target_feature(enable = "neon,fp16")]
3434#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3435#[cfg(not(target_arch = "arm64ec"))]
3436pub fn vcmla_laneq_f16<const LANE: i32>(
3437    a: float16x4_t,
3438    b: float16x4_t,
3439    c: float16x8_t,
3440) -> float16x4_t {
3441    static_assert_uimm_bits!(LANE, 2);
3442    let c = vreinterpretq_u32_f16(c);
3443    let c = vdup_laneq_u32::<LANE>(c);
3444    let c = vreinterpret_f16_u32(c);
3445    vcmla_f16(a, b, c)
3446}
3447#[doc = "Floating-point complex multiply accumulate"]
3448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f16)"]
3449#[inline]
3450#[target_feature(enable = "neon,fcma")]
3451#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3452#[rustc_legacy_const_generics(3)]
3453#[target_feature(enable = "neon,fp16")]
3454#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3455#[cfg(not(target_arch = "arm64ec"))]
3456pub fn vcmlaq_laneq_f16<const LANE: i32>(
3457    a: float16x8_t,
3458    b: float16x8_t,
3459    c: float16x8_t,
3460) -> float16x8_t {
3461    static_assert_uimm_bits!(LANE, 2);
3462    let c = vreinterpretq_u32_f16(c);
3463    let c = vdupq_laneq_u32::<LANE>(c);
3464    let c = vreinterpretq_f16_u32(c);
3465    vcmlaq_f16(a, b, c)
3466}
3467#[doc = "Floating-point complex multiply accumulate"]
3468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"]
3469#[inline]
3470#[target_feature(enable = "neon,fcma")]
3471#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3472#[rustc_legacy_const_generics(3)]
3473#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3474pub fn vcmla_laneq_f32<const LANE: i32>(
3475    a: float32x2_t,
3476    b: float32x2_t,
3477    c: float32x4_t,
3478) -> float32x2_t {
3479    static_assert_uimm_bits!(LANE, 1);
3480    let c = vreinterpretq_u64_f32(c);
3481    let c = vdup_laneq_u64::<LANE>(c);
3482    let c = vreinterpret_f32_u64(c);
3483    vcmla_f32(a, b, c)
3484}
3485#[doc = "Floating-point complex multiply accumulate"]
3486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"]
3487#[inline]
3488#[target_feature(enable = "neon,fcma")]
3489#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3490#[rustc_legacy_const_generics(3)]
3491#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3492pub fn vcmlaq_laneq_f32<const LANE: i32>(
3493    a: float32x4_t,
3494    b: float32x4_t,
3495    c: float32x4_t,
3496) -> float32x4_t {
3497    static_assert_uimm_bits!(LANE, 1);
3498    let c = vreinterpretq_u64_f32(c);
3499    let c = vdupq_laneq_u64::<LANE>(c);
3500    let c = vreinterpretq_f32_u64(c);
3501    vcmlaq_f32(a, b, c)
3502}
3503#[doc = "Floating-point complex multiply accumulate"]
3504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"]
3505#[inline]
3506#[cfg(target_endian = "little")]
3507#[target_feature(enable = "neon,fcma")]
3508#[target_feature(enable = "neon,fp16")]
3509#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3510#[cfg(not(target_arch = "arm64ec"))]
3511#[cfg_attr(test, assert_instr(fcmla))]
3512pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3513    unsafe extern "unadjusted" {
3514        #[cfg_attr(
3515            any(target_arch = "aarch64", target_arch = "arm64ec"),
3516            link_name = "llvm.aarch64.neon.vcmla.rot180.v4f16"
3517        )]
3518        fn _vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
3519    }
3520    unsafe { _vcmla_rot180_f16(a, b, c) }
3521}
3522#[doc = "Floating-point complex multiply accumulate"]
3523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"]
3524#[inline]
3525#[cfg(target_endian = "big")]
3526#[target_feature(enable = "neon,fcma")]
3527#[target_feature(enable = "neon,fp16")]
3528#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3529#[cfg(not(target_arch = "arm64ec"))]
3530#[cfg_attr(test, assert_instr(fcmla))]
3531pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3532    unsafe extern "unadjusted" {
3533        #[cfg_attr(
3534            any(target_arch = "aarch64", target_arch = "arm64ec"),
3535            link_name = "llvm.aarch64.neon.vcmla.rot180.v4f16"
3536        )]
3537        fn _vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
3538    }
3539    unsafe {
3540        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
3541        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
3542        let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
3543        let ret_val: float16x4_t = _vcmla_rot180_f16(a, b, c);
3544        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
3545    }
3546}
3547#[doc = "Floating-point complex multiply accumulate"]
3548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"]
3549#[inline]
3550#[cfg(target_endian = "little")]
3551#[target_feature(enable = "neon,fcma")]
3552#[target_feature(enable = "neon,fp16")]
3553#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3554#[cfg(not(target_arch = "arm64ec"))]
3555#[cfg_attr(test, assert_instr(fcmla))]
3556pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3557    unsafe extern "unadjusted" {
3558        #[cfg_attr(
3559            any(target_arch = "aarch64", target_arch = "arm64ec"),
3560            link_name = "llvm.aarch64.neon.vcmla.rot180.v8f16"
3561        )]
3562        fn _vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
3563    }
3564    unsafe { _vcmlaq_rot180_f16(a, b, c) }
3565}
3566#[doc = "Floating-point complex multiply accumulate"]
3567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"]
3568#[inline]
3569#[cfg(target_endian = "big")]
3570#[target_feature(enable = "neon,fcma")]
3571#[target_feature(enable = "neon,fp16")]
3572#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3573#[cfg(not(target_arch = "arm64ec"))]
3574#[cfg_attr(test, assert_instr(fcmla))]
3575pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3576    unsafe extern "unadjusted" {
3577        #[cfg_attr(
3578            any(target_arch = "aarch64", target_arch = "arm64ec"),
3579            link_name = "llvm.aarch64.neon.vcmla.rot180.v8f16"
3580        )]
3581        fn _vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
3582    }
3583    unsafe {
3584        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
3585        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
3586        let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
3587        let ret_val: float16x8_t = _vcmlaq_rot180_f16(a, b, c);
3588        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
3589    }
3590}
3591#[doc = "Floating-point complex multiply accumulate"]
3592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"]
3593#[inline]
3594#[cfg(target_endian = "little")]
3595#[target_feature(enable = "neon,fcma")]
3596#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3597#[cfg_attr(test, assert_instr(fcmla))]
3598pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3599    unsafe extern "unadjusted" {
3600        #[cfg_attr(
3601            any(target_arch = "aarch64", target_arch = "arm64ec"),
3602            link_name = "llvm.aarch64.neon.vcmla.rot180.v2f32"
3603        )]
3604        fn _vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
3605    }
3606    unsafe { _vcmla_rot180_f32(a, b, c) }
3607}
3608#[doc = "Floating-point complex multiply accumulate"]
3609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"]
3610#[inline]
3611#[cfg(target_endian = "big")]
3612#[target_feature(enable = "neon,fcma")]
3613#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3614#[cfg_attr(test, assert_instr(fcmla))]
3615pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3616    unsafe extern "unadjusted" {
3617        #[cfg_attr(
3618            any(target_arch = "aarch64", target_arch = "arm64ec"),
3619            link_name = "llvm.aarch64.neon.vcmla.rot180.v2f32"
3620        )]
3621        fn _vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
3622    }
3623    unsafe {
3624        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
3625        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
3626        let c: float32x2_t = simd_shuffle!(c, c, [1, 0]);
3627        let ret_val: float32x2_t = _vcmla_rot180_f32(a, b, c);
3628        simd_shuffle!(ret_val, ret_val, [1, 0])
3629    }
3630}
3631#[doc = "Floating-point complex multiply accumulate"]
3632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"]
3633#[inline]
3634#[cfg(target_endian = "little")]
3635#[target_feature(enable = "neon,fcma")]
3636#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3637#[cfg_attr(test, assert_instr(fcmla))]
3638pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
3639    unsafe extern "unadjusted" {
3640        #[cfg_attr(
3641            any(target_arch = "aarch64", target_arch = "arm64ec"),
3642            link_name = "llvm.aarch64.neon.vcmla.rot180.v4f32"
3643        )]
3644        fn _vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
3645    }
3646    unsafe { _vcmlaq_rot180_f32(a, b, c) }
3647}
3648#[doc = "Floating-point complex multiply accumulate"]
3649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"]
3650#[inline]
3651#[cfg(target_endian = "big")]
3652#[target_feature(enable = "neon,fcma")]
3653#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3654#[cfg_attr(test, assert_instr(fcmla))]
3655pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
3656    unsafe extern "unadjusted" {
3657        #[cfg_attr(
3658            any(target_arch = "aarch64", target_arch = "arm64ec"),
3659            link_name = "llvm.aarch64.neon.vcmla.rot180.v4f32"
3660        )]
3661        fn _vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
3662    }
3663    unsafe {
3664        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
3665        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
3666        let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
3667        let ret_val: float32x4_t = _vcmlaq_rot180_f32(a, b, c);
3668        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
3669    }
3670}
3671#[doc = "Floating-point complex multiply accumulate"]
3672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"]
3673#[inline]
3674#[cfg(target_endian = "little")]
3675#[target_feature(enable = "neon,fcma")]
3676#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3677#[cfg_attr(test, assert_instr(fcmla))]
3678pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
3679    unsafe extern "unadjusted" {
3680        #[cfg_attr(
3681            any(target_arch = "aarch64", target_arch = "arm64ec"),
3682            link_name = "llvm.aarch64.neon.vcmla.rot180.v2f64"
3683        )]
3684        fn _vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t;
3685    }
3686    unsafe { _vcmlaq_rot180_f64(a, b, c) }
3687}
3688#[doc = "Floating-point complex multiply accumulate"]
3689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"]
3690#[inline]
3691#[cfg(target_endian = "big")]
3692#[target_feature(enable = "neon,fcma")]
3693#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3694#[cfg_attr(test, assert_instr(fcmla))]
3695pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
3696    unsafe extern "unadjusted" {
3697        #[cfg_attr(
3698            any(target_arch = "aarch64", target_arch = "arm64ec"),
3699            link_name = "llvm.aarch64.neon.vcmla.rot180.v2f64"
3700        )]
3701        fn _vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t;
3702    }
3703    unsafe {
3704        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
3705        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
3706        let c: float64x2_t = simd_shuffle!(c, c, [1, 0]);
3707        let ret_val: float64x2_t = _vcmlaq_rot180_f64(a, b, c);
3708        simd_shuffle!(ret_val, ret_val, [1, 0])
3709    }
3710}
3711#[doc = "Floating-point complex multiply accumulate"]
3712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f16)"]
3713#[inline]
3714#[target_feature(enable = "neon,fcma")]
3715#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3716#[rustc_legacy_const_generics(3)]
3717#[target_feature(enable = "neon,fp16")]
3718#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3719#[cfg(not(target_arch = "arm64ec"))]
3720pub fn vcmla_rot180_lane_f16<const LANE: i32>(
3721    a: float16x4_t,
3722    b: float16x4_t,
3723    c: float16x4_t,
3724) -> float16x4_t {
3725    static_assert_uimm_bits!(LANE, 1);
3726    let c = vreinterpret_u32_f16(c);
3727    let c = vdup_lane_u32::<LANE>(c);
3728    let c = vreinterpret_f16_u32(c);
3729    vcmla_rot180_f16(a, b, c)
3730}
3731#[doc = "Floating-point complex multiply accumulate"]
3732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f16)"]
3733#[inline]
3734#[target_feature(enable = "neon,fcma")]
3735#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3736#[rustc_legacy_const_generics(3)]
3737#[target_feature(enable = "neon,fp16")]
3738#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3739#[cfg(not(target_arch = "arm64ec"))]
3740pub fn vcmlaq_rot180_lane_f16<const LANE: i32>(
3741    a: float16x8_t,
3742    b: float16x8_t,
3743    c: float16x4_t,
3744) -> float16x8_t {
3745    static_assert_uimm_bits!(LANE, 1);
3746    let c = vreinterpret_u32_f16(c);
3747    let c = vdupq_lane_u32::<LANE>(c);
3748    let c = vreinterpretq_f16_u32(c);
3749    vcmlaq_rot180_f16(a, b, c)
3750}
3751#[doc = "Floating-point complex multiply accumulate"]
3752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"]
3753#[inline]
3754#[target_feature(enable = "neon,fcma")]
3755#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3756#[rustc_legacy_const_generics(3)]
3757#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3758pub fn vcmla_rot180_lane_f32<const LANE: i32>(
3759    a: float32x2_t,
3760    b: float32x2_t,
3761    c: float32x2_t,
3762) -> float32x2_t {
3763    static_assert!(LANE == 0);
3764    let c = vreinterpret_u64_f32(c);
3765    let c = vdup_lane_u64::<LANE>(c);
3766    let c = vreinterpret_f32_u64(c);
3767    vcmla_rot180_f32(a, b, c)
3768}
3769#[doc = "Floating-point complex multiply accumulate"]
3770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"]
3771#[inline]
3772#[target_feature(enable = "neon,fcma")]
3773#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3774#[rustc_legacy_const_generics(3)]
3775#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3776pub fn vcmlaq_rot180_lane_f32<const LANE: i32>(
3777    a: float32x4_t,
3778    b: float32x4_t,
3779    c: float32x2_t,
3780) -> float32x4_t {
3781    static_assert!(LANE == 0);
3782    let c = vreinterpret_u64_f32(c);
3783    let c = vdupq_lane_u64::<LANE>(c);
3784    let c = vreinterpretq_f32_u64(c);
3785    vcmlaq_rot180_f32(a, b, c)
3786}
3787#[doc = "Floating-point complex multiply accumulate"]
3788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f16)"]
3789#[inline]
3790#[target_feature(enable = "neon,fcma")]
3791#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3792#[rustc_legacy_const_generics(3)]
3793#[target_feature(enable = "neon,fp16")]
3794#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3795#[cfg(not(target_arch = "arm64ec"))]
3796pub fn vcmla_rot180_laneq_f16<const LANE: i32>(
3797    a: float16x4_t,
3798    b: float16x4_t,
3799    c: float16x8_t,
3800) -> float16x4_t {
3801    static_assert_uimm_bits!(LANE, 2);
3802    let c = vreinterpretq_u32_f16(c);
3803    let c = vdup_laneq_u32::<LANE>(c);
3804    let c = vreinterpret_f16_u32(c);
3805    vcmla_rot180_f16(a, b, c)
3806}
3807#[doc = "Floating-point complex multiply accumulate"]
3808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f16)"]
3809#[inline]
3810#[target_feature(enable = "neon,fcma")]
3811#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3812#[rustc_legacy_const_generics(3)]
3813#[target_feature(enable = "neon,fp16")]
3814#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3815#[cfg(not(target_arch = "arm64ec"))]
3816pub fn vcmlaq_rot180_laneq_f16<const LANE: i32>(
3817    a: float16x8_t,
3818    b: float16x8_t,
3819    c: float16x8_t,
3820) -> float16x8_t {
3821    static_assert_uimm_bits!(LANE, 2);
3822    let c = vreinterpretq_u32_f16(c);
3823    let c = vdupq_laneq_u32::<LANE>(c);
3824    let c = vreinterpretq_f16_u32(c);
3825    vcmlaq_rot180_f16(a, b, c)
3826}
3827#[doc = "Floating-point complex multiply accumulate"]
3828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"]
3829#[inline]
3830#[target_feature(enable = "neon,fcma")]
3831#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3832#[rustc_legacy_const_generics(3)]
3833#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3834pub fn vcmla_rot180_laneq_f32<const LANE: i32>(
3835    a: float32x2_t,
3836    b: float32x2_t,
3837    c: float32x4_t,
3838) -> float32x2_t {
3839    static_assert_uimm_bits!(LANE, 1);
3840    let c = vreinterpretq_u64_f32(c);
3841    let c = vdup_laneq_u64::<LANE>(c);
3842    let c = vreinterpret_f32_u64(c);
3843    vcmla_rot180_f32(a, b, c)
3844}
3845#[doc = "Floating-point complex multiply accumulate"]
3846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"]
3847#[inline]
3848#[target_feature(enable = "neon,fcma")]
3849#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
3850#[rustc_legacy_const_generics(3)]
3851#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3852pub fn vcmlaq_rot180_laneq_f32<const LANE: i32>(
3853    a: float32x4_t,
3854    b: float32x4_t,
3855    c: float32x4_t,
3856) -> float32x4_t {
3857    static_assert_uimm_bits!(LANE, 1);
3858    let c = vreinterpretq_u64_f32(c);
3859    let c = vdupq_laneq_u64::<LANE>(c);
3860    let c = vreinterpretq_f32_u64(c);
3861    vcmlaq_rot180_f32(a, b, c)
3862}
3863#[doc = "Floating-point complex multiply accumulate"]
3864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"]
3865#[inline]
3866#[cfg(target_endian = "little")]
3867#[target_feature(enable = "neon,fcma")]
3868#[target_feature(enable = "neon,fp16")]
3869#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3870#[cfg(not(target_arch = "arm64ec"))]
3871#[cfg_attr(test, assert_instr(fcmla))]
3872pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3873    unsafe extern "unadjusted" {
3874        #[cfg_attr(
3875            any(target_arch = "aarch64", target_arch = "arm64ec"),
3876            link_name = "llvm.aarch64.neon.vcmla.rot270.v4f16"
3877        )]
3878        fn _vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
3879    }
3880    unsafe { _vcmla_rot270_f16(a, b, c) }
3881}
3882#[doc = "Floating-point complex multiply accumulate"]
3883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"]
3884#[inline]
3885#[cfg(target_endian = "big")]
3886#[target_feature(enable = "neon,fcma")]
3887#[target_feature(enable = "neon,fp16")]
3888#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3889#[cfg(not(target_arch = "arm64ec"))]
3890#[cfg_attr(test, assert_instr(fcmla))]
3891pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3892    unsafe extern "unadjusted" {
3893        #[cfg_attr(
3894            any(target_arch = "aarch64", target_arch = "arm64ec"),
3895            link_name = "llvm.aarch64.neon.vcmla.rot270.v4f16"
3896        )]
3897        fn _vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
3898    }
3899    unsafe {
3900        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
3901        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
3902        let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
3903        let ret_val: float16x4_t = _vcmla_rot270_f16(a, b, c);
3904        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
3905    }
3906}
3907#[doc = "Floating-point complex multiply accumulate"]
3908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"]
3909#[inline]
3910#[cfg(target_endian = "little")]
3911#[target_feature(enable = "neon,fcma")]
3912#[target_feature(enable = "neon,fp16")]
3913#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3914#[cfg(not(target_arch = "arm64ec"))]
3915#[cfg_attr(test, assert_instr(fcmla))]
3916pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3917    unsafe extern "unadjusted" {
3918        #[cfg_attr(
3919            any(target_arch = "aarch64", target_arch = "arm64ec"),
3920            link_name = "llvm.aarch64.neon.vcmla.rot270.v8f16"
3921        )]
3922        fn _vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
3923    }
3924    unsafe { _vcmlaq_rot270_f16(a, b, c) }
3925}
3926#[doc = "Floating-point complex multiply accumulate"]
3927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"]
3928#[inline]
3929#[cfg(target_endian = "big")]
3930#[target_feature(enable = "neon,fcma")]
3931#[target_feature(enable = "neon,fp16")]
3932#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3933#[cfg(not(target_arch = "arm64ec"))]
3934#[cfg_attr(test, assert_instr(fcmla))]
3935pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3936    unsafe extern "unadjusted" {
3937        #[cfg_attr(
3938            any(target_arch = "aarch64", target_arch = "arm64ec"),
3939            link_name = "llvm.aarch64.neon.vcmla.rot270.v8f16"
3940        )]
3941        fn _vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
3942    }
3943    unsafe {
3944        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
3945        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
3946        let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
3947        let ret_val: float16x8_t = _vcmlaq_rot270_f16(a, b, c);
3948        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
3949    }
3950}
3951#[doc = "Floating-point complex multiply accumulate"]
3952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"]
3953#[inline]
3954#[cfg(target_endian = "little")]
3955#[target_feature(enable = "neon,fcma")]
3956#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3957#[cfg_attr(test, assert_instr(fcmla))]
3958pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3959    unsafe extern "unadjusted" {
3960        #[cfg_attr(
3961            any(target_arch = "aarch64", target_arch = "arm64ec"),
3962            link_name = "llvm.aarch64.neon.vcmla.rot270.v2f32"
3963        )]
3964        fn _vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
3965    }
3966    unsafe { _vcmla_rot270_f32(a, b, c) }
3967}
3968#[doc = "Floating-point complex multiply accumulate"]
3969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"]
3970#[inline]
3971#[cfg(target_endian = "big")]
3972#[target_feature(enable = "neon,fcma")]
3973#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3974#[cfg_attr(test, assert_instr(fcmla))]
3975pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3976    unsafe extern "unadjusted" {
3977        #[cfg_attr(
3978            any(target_arch = "aarch64", target_arch = "arm64ec"),
3979            link_name = "llvm.aarch64.neon.vcmla.rot270.v2f32"
3980        )]
3981        fn _vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
3982    }
3983    unsafe {
3984        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
3985        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
3986        let c: float32x2_t = simd_shuffle!(c, c, [1, 0]);
3987        let ret_val: float32x2_t = _vcmla_rot270_f32(a, b, c);
3988        simd_shuffle!(ret_val, ret_val, [1, 0])
3989    }
3990}
3991#[doc = "Floating-point complex multiply accumulate"]
3992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"]
3993#[inline]
3994#[cfg(target_endian = "little")]
3995#[target_feature(enable = "neon,fcma")]
3996#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
3997#[cfg_attr(test, assert_instr(fcmla))]
3998pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
3999    unsafe extern "unadjusted" {
4000        #[cfg_attr(
4001            any(target_arch = "aarch64", target_arch = "arm64ec"),
4002            link_name = "llvm.aarch64.neon.vcmla.rot270.v4f32"
4003        )]
4004        fn _vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
4005    }
4006    unsafe { _vcmlaq_rot270_f32(a, b, c) }
4007}
4008#[doc = "Floating-point complex multiply accumulate"]
4009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"]
4010#[inline]
4011#[cfg(target_endian = "big")]
4012#[target_feature(enable = "neon,fcma")]
4013#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4014#[cfg_attr(test, assert_instr(fcmla))]
4015pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
4016    unsafe extern "unadjusted" {
4017        #[cfg_attr(
4018            any(target_arch = "aarch64", target_arch = "arm64ec"),
4019            link_name = "llvm.aarch64.neon.vcmla.rot270.v4f32"
4020        )]
4021        fn _vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
4022    }
4023    unsafe {
4024        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
4025        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
4026        let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
4027        let ret_val: float32x4_t = _vcmlaq_rot270_f32(a, b, c);
4028        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
4029    }
4030}
4031#[doc = "Floating-point complex multiply accumulate"]
4032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"]
4033#[inline]
4034#[cfg(target_endian = "little")]
4035#[target_feature(enable = "neon,fcma")]
4036#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4037#[cfg_attr(test, assert_instr(fcmla))]
4038pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
4039    unsafe extern "unadjusted" {
4040        #[cfg_attr(
4041            any(target_arch = "aarch64", target_arch = "arm64ec"),
4042            link_name = "llvm.aarch64.neon.vcmla.rot270.v2f64"
4043        )]
4044        fn _vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t;
4045    }
4046    unsafe { _vcmlaq_rot270_f64(a, b, c) }
4047}
4048#[doc = "Floating-point complex multiply accumulate"]
4049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"]
4050#[inline]
4051#[cfg(target_endian = "big")]
4052#[target_feature(enable = "neon,fcma")]
4053#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4054#[cfg_attr(test, assert_instr(fcmla))]
4055pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
4056    unsafe extern "unadjusted" {
4057        #[cfg_attr(
4058            any(target_arch = "aarch64", target_arch = "arm64ec"),
4059            link_name = "llvm.aarch64.neon.vcmla.rot270.v2f64"
4060        )]
4061        fn _vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t;
4062    }
4063    unsafe {
4064        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
4065        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
4066        let c: float64x2_t = simd_shuffle!(c, c, [1, 0]);
4067        let ret_val: float64x2_t = _vcmlaq_rot270_f64(a, b, c);
4068        simd_shuffle!(ret_val, ret_val, [1, 0])
4069    }
4070}
4071#[doc = "Floating-point complex multiply accumulate"]
4072#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f16)"]
4073#[inline]
4074#[target_feature(enable = "neon,fcma")]
4075#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4076#[rustc_legacy_const_generics(3)]
4077#[target_feature(enable = "neon,fp16")]
4078#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4079#[cfg(not(target_arch = "arm64ec"))]
4080pub fn vcmla_rot270_lane_f16<const LANE: i32>(
4081    a: float16x4_t,
4082    b: float16x4_t,
4083    c: float16x4_t,
4084) -> float16x4_t {
4085    static_assert_uimm_bits!(LANE, 1);
4086    let c = vreinterpret_u32_f16(c);
4087    let c = vdup_lane_u32::<LANE>(c);
4088    let c = vreinterpret_f16_u32(c);
4089    vcmla_rot270_f16(a, b, c)
4090}
4091#[doc = "Floating-point complex multiply accumulate"]
4092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f16)"]
4093#[inline]
4094#[target_feature(enable = "neon,fcma")]
4095#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4096#[rustc_legacy_const_generics(3)]
4097#[target_feature(enable = "neon,fp16")]
4098#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4099#[cfg(not(target_arch = "arm64ec"))]
4100pub fn vcmlaq_rot270_lane_f16<const LANE: i32>(
4101    a: float16x8_t,
4102    b: float16x8_t,
4103    c: float16x4_t,
4104) -> float16x8_t {
4105    static_assert_uimm_bits!(LANE, 1);
4106    let c = vreinterpret_u32_f16(c);
4107    let c = vdupq_lane_u32::<LANE>(c);
4108    let c = vreinterpretq_f16_u32(c);
4109    vcmlaq_rot270_f16(a, b, c)
4110}
4111#[doc = "Floating-point complex multiply accumulate"]
4112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"]
4113#[inline]
4114#[target_feature(enable = "neon,fcma")]
4115#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4116#[rustc_legacy_const_generics(3)]
4117#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4118pub fn vcmla_rot270_lane_f32<const LANE: i32>(
4119    a: float32x2_t,
4120    b: float32x2_t,
4121    c: float32x2_t,
4122) -> float32x2_t {
4123    static_assert!(LANE == 0);
4124    let c = vreinterpret_u64_f32(c);
4125    let c = vdup_lane_u64::<LANE>(c);
4126    let c = vreinterpret_f32_u64(c);
4127    vcmla_rot270_f32(a, b, c)
4128}
4129#[doc = "Floating-point complex multiply accumulate"]
4130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"]
4131#[inline]
4132#[target_feature(enable = "neon,fcma")]
4133#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4134#[rustc_legacy_const_generics(3)]
4135#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4136pub fn vcmlaq_rot270_lane_f32<const LANE: i32>(
4137    a: float32x4_t,
4138    b: float32x4_t,
4139    c: float32x2_t,
4140) -> float32x4_t {
4141    static_assert!(LANE == 0);
4142    let c = vreinterpret_u64_f32(c);
4143    let c = vdupq_lane_u64::<LANE>(c);
4144    let c = vreinterpretq_f32_u64(c);
4145    vcmlaq_rot270_f32(a, b, c)
4146}
4147#[doc = "Floating-point complex multiply accumulate"]
4148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f16)"]
4149#[inline]
4150#[target_feature(enable = "neon,fcma")]
4151#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4152#[rustc_legacy_const_generics(3)]
4153#[target_feature(enable = "neon,fp16")]
4154#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4155#[cfg(not(target_arch = "arm64ec"))]
4156pub fn vcmla_rot270_laneq_f16<const LANE: i32>(
4157    a: float16x4_t,
4158    b: float16x4_t,
4159    c: float16x8_t,
4160) -> float16x4_t {
4161    static_assert_uimm_bits!(LANE, 2);
4162    let c = vreinterpretq_u32_f16(c);
4163    let c = vdup_laneq_u32::<LANE>(c);
4164    let c = vreinterpret_f16_u32(c);
4165    vcmla_rot270_f16(a, b, c)
4166}
4167#[doc = "Floating-point complex multiply accumulate"]
4168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f16)"]
4169#[inline]
4170#[target_feature(enable = "neon,fcma")]
4171#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4172#[rustc_legacy_const_generics(3)]
4173#[target_feature(enable = "neon,fp16")]
4174#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4175#[cfg(not(target_arch = "arm64ec"))]
4176pub fn vcmlaq_rot270_laneq_f16<const LANE: i32>(
4177    a: float16x8_t,
4178    b: float16x8_t,
4179    c: float16x8_t,
4180) -> float16x8_t {
4181    static_assert_uimm_bits!(LANE, 2);
4182    let c = vreinterpretq_u32_f16(c);
4183    let c = vdupq_laneq_u32::<LANE>(c);
4184    let c = vreinterpretq_f16_u32(c);
4185    vcmlaq_rot270_f16(a, b, c)
4186}
4187#[doc = "Floating-point complex multiply accumulate"]
4188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"]
4189#[inline]
4190#[target_feature(enable = "neon,fcma")]
4191#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4192#[rustc_legacy_const_generics(3)]
4193#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4194pub fn vcmla_rot270_laneq_f32<const LANE: i32>(
4195    a: float32x2_t,
4196    b: float32x2_t,
4197    c: float32x4_t,
4198) -> float32x2_t {
4199    static_assert_uimm_bits!(LANE, 1);
4200    let c = vreinterpretq_u64_f32(c);
4201    let c = vdup_laneq_u64::<LANE>(c);
4202    let c = vreinterpret_f32_u64(c);
4203    vcmla_rot270_f32(a, b, c)
4204}
4205#[doc = "Floating-point complex multiply accumulate"]
4206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"]
4207#[inline]
4208#[target_feature(enable = "neon,fcma")]
4209#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4210#[rustc_legacy_const_generics(3)]
4211#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4212pub fn vcmlaq_rot270_laneq_f32<const LANE: i32>(
4213    a: float32x4_t,
4214    b: float32x4_t,
4215    c: float32x4_t,
4216) -> float32x4_t {
4217    static_assert_uimm_bits!(LANE, 1);
4218    let c = vreinterpretq_u64_f32(c);
4219    let c = vdupq_laneq_u64::<LANE>(c);
4220    let c = vreinterpretq_f32_u64(c);
4221    vcmlaq_rot270_f32(a, b, c)
4222}
4223#[doc = "Floating-point complex multiply accumulate"]
4224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"]
4225#[inline]
4226#[cfg(target_endian = "little")]
4227#[target_feature(enable = "neon,fcma")]
4228#[target_feature(enable = "neon,fp16")]
4229#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4230#[cfg(not(target_arch = "arm64ec"))]
4231#[cfg_attr(test, assert_instr(fcmla))]
4232pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
4233    unsafe extern "unadjusted" {
4234        #[cfg_attr(
4235            any(target_arch = "aarch64", target_arch = "arm64ec"),
4236            link_name = "llvm.aarch64.neon.vcmla.rot90.v4f16"
4237        )]
4238        fn _vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
4239    }
4240    unsafe { _vcmla_rot90_f16(a, b, c) }
4241}
4242#[doc = "Floating-point complex multiply accumulate"]
4243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"]
4244#[inline]
4245#[cfg(target_endian = "big")]
4246#[target_feature(enable = "neon,fcma")]
4247#[target_feature(enable = "neon,fp16")]
4248#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4249#[cfg(not(target_arch = "arm64ec"))]
4250#[cfg_attr(test, assert_instr(fcmla))]
4251pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
4252    unsafe extern "unadjusted" {
4253        #[cfg_attr(
4254            any(target_arch = "aarch64", target_arch = "arm64ec"),
4255            link_name = "llvm.aarch64.neon.vcmla.rot90.v4f16"
4256        )]
4257        fn _vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
4258    }
4259    unsafe {
4260        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
4261        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
4262        let c: float16x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
4263        let ret_val: float16x4_t = _vcmla_rot90_f16(a, b, c);
4264        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
4265    }
4266}
4267#[doc = "Floating-point complex multiply accumulate"]
4268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"]
4269#[inline]
4270#[cfg(target_endian = "little")]
4271#[target_feature(enable = "neon,fcma")]
4272#[target_feature(enable = "neon,fp16")]
4273#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4274#[cfg(not(target_arch = "arm64ec"))]
4275#[cfg_attr(test, assert_instr(fcmla))]
4276pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
4277    unsafe extern "unadjusted" {
4278        #[cfg_attr(
4279            any(target_arch = "aarch64", target_arch = "arm64ec"),
4280            link_name = "llvm.aarch64.neon.vcmla.rot90.v8f16"
4281        )]
4282        fn _vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
4283    }
4284    unsafe { _vcmlaq_rot90_f16(a, b, c) }
4285}
4286#[doc = "Floating-point complex multiply accumulate"]
4287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"]
4288#[inline]
4289#[cfg(target_endian = "big")]
4290#[target_feature(enable = "neon,fcma")]
4291#[target_feature(enable = "neon,fp16")]
4292#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4293#[cfg(not(target_arch = "arm64ec"))]
4294#[cfg_attr(test, assert_instr(fcmla))]
4295pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
4296    unsafe extern "unadjusted" {
4297        #[cfg_attr(
4298            any(target_arch = "aarch64", target_arch = "arm64ec"),
4299            link_name = "llvm.aarch64.neon.vcmla.rot90.v8f16"
4300        )]
4301        fn _vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
4302    }
4303    unsafe {
4304        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
4305        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
4306        let c: float16x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
4307        let ret_val: float16x8_t = _vcmlaq_rot90_f16(a, b, c);
4308        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
4309    }
4310}
4311#[doc = "Floating-point complex multiply accumulate"]
4312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"]
4313#[inline]
4314#[cfg(target_endian = "little")]
4315#[target_feature(enable = "neon,fcma")]
4316#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4317#[cfg_attr(test, assert_instr(fcmla))]
4318pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
4319    unsafe extern "unadjusted" {
4320        #[cfg_attr(
4321            any(target_arch = "aarch64", target_arch = "arm64ec"),
4322            link_name = "llvm.aarch64.neon.vcmla.rot90.v2f32"
4323        )]
4324        fn _vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
4325    }
4326    unsafe { _vcmla_rot90_f32(a, b, c) }
4327}
4328#[doc = "Floating-point complex multiply accumulate"]
4329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"]
4330#[inline]
4331#[cfg(target_endian = "big")]
4332#[target_feature(enable = "neon,fcma")]
4333#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4334#[cfg_attr(test, assert_instr(fcmla))]
4335pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
4336    unsafe extern "unadjusted" {
4337        #[cfg_attr(
4338            any(target_arch = "aarch64", target_arch = "arm64ec"),
4339            link_name = "llvm.aarch64.neon.vcmla.rot90.v2f32"
4340        )]
4341        fn _vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
4342    }
4343    unsafe {
4344        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
4345        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
4346        let c: float32x2_t = simd_shuffle!(c, c, [1, 0]);
4347        let ret_val: float32x2_t = _vcmla_rot90_f32(a, b, c);
4348        simd_shuffle!(ret_val, ret_val, [1, 0])
4349    }
4350}
4351#[doc = "Floating-point complex multiply accumulate"]
4352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"]
4353#[inline]
4354#[cfg(target_endian = "little")]
4355#[target_feature(enable = "neon,fcma")]
4356#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4357#[cfg_attr(test, assert_instr(fcmla))]
4358pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
4359    unsafe extern "unadjusted" {
4360        #[cfg_attr(
4361            any(target_arch = "aarch64", target_arch = "arm64ec"),
4362            link_name = "llvm.aarch64.neon.vcmla.rot90.v4f32"
4363        )]
4364        fn _vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
4365    }
4366    unsafe { _vcmlaq_rot90_f32(a, b, c) }
4367}
4368#[doc = "Floating-point complex multiply accumulate"]
4369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"]
4370#[inline]
4371#[cfg(target_endian = "big")]
4372#[target_feature(enable = "neon,fcma")]
4373#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4374#[cfg_attr(test, assert_instr(fcmla))]
4375pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
4376    unsafe extern "unadjusted" {
4377        #[cfg_attr(
4378            any(target_arch = "aarch64", target_arch = "arm64ec"),
4379            link_name = "llvm.aarch64.neon.vcmla.rot90.v4f32"
4380        )]
4381        fn _vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
4382    }
4383    unsafe {
4384        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
4385        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
4386        let c: float32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
4387        let ret_val: float32x4_t = _vcmlaq_rot90_f32(a, b, c);
4388        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
4389    }
4390}
4391#[doc = "Floating-point complex multiply accumulate"]
4392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"]
4393#[inline]
4394#[cfg(target_endian = "little")]
4395#[target_feature(enable = "neon,fcma")]
4396#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4397#[cfg_attr(test, assert_instr(fcmla))]
4398pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
4399    unsafe extern "unadjusted" {
4400        #[cfg_attr(
4401            any(target_arch = "aarch64", target_arch = "arm64ec"),
4402            link_name = "llvm.aarch64.neon.vcmla.rot90.v2f64"
4403        )]
4404        fn _vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t;
4405    }
4406    unsafe { _vcmlaq_rot90_f64(a, b, c) }
4407}
4408#[doc = "Floating-point complex multiply accumulate"]
4409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"]
4410#[inline]
4411#[cfg(target_endian = "big")]
4412#[target_feature(enable = "neon,fcma")]
4413#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4414#[cfg_attr(test, assert_instr(fcmla))]
4415pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
4416    unsafe extern "unadjusted" {
4417        #[cfg_attr(
4418            any(target_arch = "aarch64", target_arch = "arm64ec"),
4419            link_name = "llvm.aarch64.neon.vcmla.rot90.v2f64"
4420        )]
4421        fn _vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t;
4422    }
4423    unsafe {
4424        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
4425        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
4426        let c: float64x2_t = simd_shuffle!(c, c, [1, 0]);
4427        let ret_val: float64x2_t = _vcmlaq_rot90_f64(a, b, c);
4428        simd_shuffle!(ret_val, ret_val, [1, 0])
4429    }
4430}
4431#[doc = "Floating-point complex multiply accumulate"]
4432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f16)"]
4433#[inline]
4434#[target_feature(enable = "neon,fcma")]
4435#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4436#[rustc_legacy_const_generics(3)]
4437#[target_feature(enable = "neon,fp16")]
4438#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4439#[cfg(not(target_arch = "arm64ec"))]
4440pub fn vcmla_rot90_lane_f16<const LANE: i32>(
4441    a: float16x4_t,
4442    b: float16x4_t,
4443    c: float16x4_t,
4444) -> float16x4_t {
4445    static_assert_uimm_bits!(LANE, 1);
4446    let c = vreinterpret_u32_f16(c);
4447    let c = vdup_lane_u32::<LANE>(c);
4448    let c = vreinterpret_f16_u32(c);
4449    vcmla_rot90_f16(a, b, c)
4450}
4451#[doc = "Floating-point complex multiply accumulate"]
4452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f16)"]
4453#[inline]
4454#[target_feature(enable = "neon,fcma")]
4455#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4456#[rustc_legacy_const_generics(3)]
4457#[target_feature(enable = "neon,fp16")]
4458#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4459#[cfg(not(target_arch = "arm64ec"))]
4460pub fn vcmlaq_rot90_lane_f16<const LANE: i32>(
4461    a: float16x8_t,
4462    b: float16x8_t,
4463    c: float16x4_t,
4464) -> float16x8_t {
4465    static_assert_uimm_bits!(LANE, 1);
4466    let c = vreinterpret_u32_f16(c);
4467    let c = vdupq_lane_u32::<LANE>(c);
4468    let c = vreinterpretq_f16_u32(c);
4469    vcmlaq_rot90_f16(a, b, c)
4470}
4471#[doc = "Floating-point complex multiply accumulate"]
4472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"]
4473#[inline]
4474#[target_feature(enable = "neon,fcma")]
4475#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4476#[rustc_legacy_const_generics(3)]
4477#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4478pub fn vcmla_rot90_lane_f32<const LANE: i32>(
4479    a: float32x2_t,
4480    b: float32x2_t,
4481    c: float32x2_t,
4482) -> float32x2_t {
4483    static_assert!(LANE == 0);
4484    let c = vreinterpret_u64_f32(c);
4485    let c = vdup_lane_u64::<LANE>(c);
4486    let c = vreinterpret_f32_u64(c);
4487    vcmla_rot90_f32(a, b, c)
4488}
4489#[doc = "Floating-point complex multiply accumulate"]
4490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"]
4491#[inline]
4492#[target_feature(enable = "neon,fcma")]
4493#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4494#[rustc_legacy_const_generics(3)]
4495#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4496pub fn vcmlaq_rot90_lane_f32<const LANE: i32>(
4497    a: float32x4_t,
4498    b: float32x4_t,
4499    c: float32x2_t,
4500) -> float32x4_t {
4501    static_assert!(LANE == 0);
4502    let c = vreinterpret_u64_f32(c);
4503    let c = vdupq_lane_u64::<LANE>(c);
4504    let c = vreinterpretq_f32_u64(c);
4505    vcmlaq_rot90_f32(a, b, c)
4506}
4507#[doc = "Floating-point complex multiply accumulate"]
4508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f16)"]
4509#[inline]
4510#[target_feature(enable = "neon,fcma")]
4511#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4512#[rustc_legacy_const_generics(3)]
4513#[target_feature(enable = "neon,fp16")]
4514#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4515#[cfg(not(target_arch = "arm64ec"))]
4516pub fn vcmla_rot90_laneq_f16<const LANE: i32>(
4517    a: float16x4_t,
4518    b: float16x4_t,
4519    c: float16x8_t,
4520) -> float16x4_t {
4521    static_assert_uimm_bits!(LANE, 2);
4522    let c = vreinterpretq_u32_f16(c);
4523    let c = vdup_laneq_u32::<LANE>(c);
4524    let c = vreinterpret_f16_u32(c);
4525    vcmla_rot90_f16(a, b, c)
4526}
4527#[doc = "Floating-point complex multiply accumulate"]
4528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f16)"]
4529#[inline]
4530#[target_feature(enable = "neon,fcma")]
4531#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4532#[rustc_legacy_const_generics(3)]
4533#[target_feature(enable = "neon,fp16")]
4534#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4535#[cfg(not(target_arch = "arm64ec"))]
4536pub fn vcmlaq_rot90_laneq_f16<const LANE: i32>(
4537    a: float16x8_t,
4538    b: float16x8_t,
4539    c: float16x8_t,
4540) -> float16x8_t {
4541    static_assert_uimm_bits!(LANE, 2);
4542    let c = vreinterpretq_u32_f16(c);
4543    let c = vdupq_laneq_u32::<LANE>(c);
4544    let c = vreinterpretq_f16_u32(c);
4545    vcmlaq_rot90_f16(a, b, c)
4546}
4547#[doc = "Floating-point complex multiply accumulate"]
4548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"]
4549#[inline]
4550#[target_feature(enable = "neon,fcma")]
4551#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4552#[rustc_legacy_const_generics(3)]
4553#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4554pub fn vcmla_rot90_laneq_f32<const LANE: i32>(
4555    a: float32x2_t,
4556    b: float32x2_t,
4557    c: float32x4_t,
4558) -> float32x2_t {
4559    static_assert_uimm_bits!(LANE, 1);
4560    let c = vreinterpretq_u64_f32(c);
4561    let c = vdup_laneq_u64::<LANE>(c);
4562    let c = vreinterpret_f32_u64(c);
4563    vcmla_rot90_f32(a, b, c)
4564}
4565#[doc = "Floating-point complex multiply accumulate"]
4566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"]
4567#[inline]
4568#[target_feature(enable = "neon,fcma")]
4569#[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
4570#[rustc_legacy_const_generics(3)]
4571#[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
4572pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
4573    a: float32x4_t,
4574    b: float32x4_t,
4575    c: float32x4_t,
4576) -> float32x4_t {
4577    static_assert_uimm_bits!(LANE, 1);
4578    let c = vreinterpretq_u64_f32(c);
4579    let c = vdupq_laneq_u64::<LANE>(c);
4580    let c = vreinterpretq_f32_u64(c);
4581    vcmlaq_rot90_f32(a, b, c)
4582}
4583#[doc = "Join two smaller vectors into a single larger vector"]
4584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f64)"]
4585#[inline]
4586#[cfg(target_endian = "little")]
4587#[target_feature(enable = "neon")]
4588#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4589#[cfg_attr(test, assert_instr(mov))]
4590pub fn vcombine_f64(a: float64x1_t, b: float64x1_t) -> float64x2_t {
4591    unsafe { simd_shuffle!(a, b, [0, 1]) }
4592}
4593#[doc = "Join two smaller vectors into a single larger vector"]
4594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f64)"]
4595#[inline]
4596#[cfg(target_endian = "big")]
4597#[target_feature(enable = "neon")]
4598#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4599#[cfg_attr(test, assert_instr(mov))]
4600pub fn vcombine_f64(a: float64x1_t, b: float64x1_t) -> float64x2_t {
4601    unsafe {
4602        let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 1]);
4603        simd_shuffle!(ret_val, ret_val, [1, 0])
4604    }
4605}
4606#[doc = "Insert vector element from another vector element"]
4607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
4608#[inline]
4609#[target_feature(enable = "neon")]
4610#[cfg_attr(
4611    all(test, target_endian = "little"),
4612    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4613)]
4614#[rustc_legacy_const_generics(1, 3)]
4615#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4616pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
4617    a: float32x2_t,
4618    b: float32x2_t,
4619) -> float32x2_t {
4620    static_assert_uimm_bits!(LANE1, 1);
4621    static_assert_uimm_bits!(LANE2, 1);
4622    vset_lane_f32::<LANE1>(vget_lane_f32::<LANE2>(b), a)
4623}
4624#[doc = "Insert vector element from another vector element"]
4625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"]
4626#[inline]
4627#[target_feature(enable = "neon")]
4628#[cfg_attr(
4629    all(test, target_endian = "little"),
4630    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4631)]
4632#[rustc_legacy_const_generics(1, 3)]
4633#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4634pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
4635    static_assert_uimm_bits!(LANE1, 3);
4636    static_assert_uimm_bits!(LANE2, 3);
4637    vset_lane_s8::<LANE1>(vget_lane_s8::<LANE2>(b), a)
4638}
4639#[doc = "Insert vector element from another vector element"]
4640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"]
4641#[inline]
4642#[target_feature(enable = "neon")]
4643#[cfg_attr(
4644    all(test, target_endian = "little"),
4645    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4646)]
4647#[rustc_legacy_const_generics(1, 3)]
4648#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4649pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
4650    static_assert_uimm_bits!(LANE1, 2);
4651    static_assert_uimm_bits!(LANE2, 2);
4652    vset_lane_s16::<LANE1>(vget_lane_s16::<LANE2>(b), a)
4653}
4654#[doc = "Insert vector element from another vector element"]
4655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"]
4656#[inline]
4657#[target_feature(enable = "neon")]
4658#[cfg_attr(
4659    all(test, target_endian = "little"),
4660    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4661)]
4662#[rustc_legacy_const_generics(1, 3)]
4663#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4664pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
4665    static_assert_uimm_bits!(LANE1, 1);
4666    static_assert_uimm_bits!(LANE2, 1);
4667    vset_lane_s32::<LANE1>(vget_lane_s32::<LANE2>(b), a)
4668}
4669#[doc = "Insert vector element from another vector element"]
4670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"]
4671#[inline]
4672#[target_feature(enable = "neon")]
4673#[cfg_attr(
4674    all(test, target_endian = "little"),
4675    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4676)]
4677#[rustc_legacy_const_generics(1, 3)]
4678#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4679pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
4680    static_assert_uimm_bits!(LANE1, 3);
4681    static_assert_uimm_bits!(LANE2, 3);
4682    vset_lane_u8::<LANE1>(vget_lane_u8::<LANE2>(b), a)
4683}
4684#[doc = "Insert vector element from another vector element"]
4685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"]
4686#[inline]
4687#[target_feature(enable = "neon")]
4688#[cfg_attr(
4689    all(test, target_endian = "little"),
4690    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4691)]
4692#[rustc_legacy_const_generics(1, 3)]
4693#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4694pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
4695    a: uint16x4_t,
4696    b: uint16x4_t,
4697) -> uint16x4_t {
4698    static_assert_uimm_bits!(LANE1, 2);
4699    static_assert_uimm_bits!(LANE2, 2);
4700    vset_lane_u16::<LANE1>(vget_lane_u16::<LANE2>(b), a)
4701}
4702#[doc = "Insert vector element from another vector element"]
4703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"]
4704#[inline]
4705#[target_feature(enable = "neon")]
4706#[cfg_attr(
4707    all(test, target_endian = "little"),
4708    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4709)]
4710#[rustc_legacy_const_generics(1, 3)]
4711#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4712pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
4713    a: uint32x2_t,
4714    b: uint32x2_t,
4715) -> uint32x2_t {
4716    static_assert_uimm_bits!(LANE1, 1);
4717    static_assert_uimm_bits!(LANE2, 1);
4718    vset_lane_u32::<LANE1>(vget_lane_u32::<LANE2>(b), a)
4719}
4720#[doc = "Insert vector element from another vector element"]
4721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"]
4722#[inline]
4723#[target_feature(enable = "neon")]
4724#[cfg_attr(
4725    all(test, target_endian = "little"),
4726    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4727)]
4728#[rustc_legacy_const_generics(1, 3)]
4729#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4730pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
4731    static_assert_uimm_bits!(LANE1, 3);
4732    static_assert_uimm_bits!(LANE2, 3);
4733    vset_lane_p8::<LANE1>(vget_lane_p8::<LANE2>(b), a)
4734}
4735#[doc = "Insert vector element from another vector element"]
4736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"]
4737#[inline]
4738#[target_feature(enable = "neon")]
4739#[cfg_attr(
4740    all(test, target_endian = "little"),
4741    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4742)]
4743#[rustc_legacy_const_generics(1, 3)]
4744#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4745pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
4746    a: poly16x4_t,
4747    b: poly16x4_t,
4748) -> poly16x4_t {
4749    static_assert_uimm_bits!(LANE1, 2);
4750    static_assert_uimm_bits!(LANE2, 2);
4751    vset_lane_p16::<LANE1>(vget_lane_p16::<LANE2>(b), a)
4752}
4753#[doc = "Insert vector element from another vector element"]
4754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f64)"]
4755#[inline]
4756#[target_feature(enable = "neon")]
4757#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
4758#[rustc_legacy_const_generics(1, 3)]
4759#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4760pub fn vcopy_lane_f64<const LANE1: i32, const LANE2: i32>(
4761    _a: float64x1_t,
4762    b: float64x1_t,
4763) -> float64x1_t {
4764    static_assert!(LANE1 == 0);
4765    static_assert!(LANE2 == 0);
4766    b
4767}
4768#[doc = "Insert vector element from another vector element"]
4769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s64)"]
4770#[inline]
4771#[target_feature(enable = "neon")]
4772#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
4773#[rustc_legacy_const_generics(1, 3)]
4774#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4775pub fn vcopy_lane_s64<const LANE1: i32, const LANE2: i32>(
4776    _a: int64x1_t,
4777    b: int64x1_t,
4778) -> int64x1_t {
4779    static_assert!(LANE1 == 0);
4780    static_assert!(LANE2 == 0);
4781    b
4782}
4783#[doc = "Insert vector element from another vector element"]
4784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u64)"]
4785#[inline]
4786#[target_feature(enable = "neon")]
4787#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
4788#[rustc_legacy_const_generics(1, 3)]
4789#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4790pub fn vcopy_lane_u64<const LANE1: i32, const LANE2: i32>(
4791    _a: uint64x1_t,
4792    b: uint64x1_t,
4793) -> uint64x1_t {
4794    static_assert!(LANE1 == 0);
4795    static_assert!(LANE2 == 0);
4796    b
4797}
4798#[doc = "Insert vector element from another vector element"]
4799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p64)"]
4800#[inline]
4801#[target_feature(enable = "neon")]
4802#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 0))]
4803#[rustc_legacy_const_generics(1, 3)]
4804#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4805pub fn vcopy_lane_p64<const LANE1: i32, const LANE2: i32>(
4806    _a: poly64x1_t,
4807    b: poly64x1_t,
4808) -> poly64x1_t {
4809    static_assert!(LANE1 == 0);
4810    static_assert!(LANE2 == 0);
4811    b
4812}
4813#[doc = "Insert vector element from another vector element"]
4814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
4815#[inline]
4816#[target_feature(enable = "neon")]
4817#[cfg_attr(
4818    all(test, target_endian = "little"),
4819    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4820)]
4821#[rustc_legacy_const_generics(1, 3)]
4822#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4823pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
4824    a: float32x2_t,
4825    b: float32x4_t,
4826) -> float32x2_t {
4827    static_assert_uimm_bits!(LANE1, 1);
4828    static_assert_uimm_bits!(LANE2, 2);
4829    vset_lane_f32::<LANE1>(vgetq_lane_f32::<LANE2>(b), a)
4830}
4831#[doc = "Insert vector element from another vector element"]
4832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
4833#[inline]
4834#[target_feature(enable = "neon")]
4835#[cfg_attr(
4836    all(test, target_endian = "little"),
4837    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4838)]
4839#[rustc_legacy_const_generics(1, 3)]
4840#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4841pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t {
4842    static_assert_uimm_bits!(LANE1, 3);
4843    static_assert_uimm_bits!(LANE2, 4);
4844    vset_lane_s8::<LANE1>(vgetq_lane_s8::<LANE2>(b), a)
4845}
4846#[doc = "Insert vector element from another vector element"]
4847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
4848#[inline]
4849#[target_feature(enable = "neon")]
4850#[cfg_attr(
4851    all(test, target_endian = "little"),
4852    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4853)]
4854#[rustc_legacy_const_generics(1, 3)]
4855#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4856pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
4857    a: int16x4_t,
4858    b: int16x8_t,
4859) -> int16x4_t {
4860    static_assert_uimm_bits!(LANE1, 2);
4861    static_assert_uimm_bits!(LANE2, 3);
4862    vset_lane_s16::<LANE1>(vgetq_lane_s16::<LANE2>(b), a)
4863}
4864#[doc = "Insert vector element from another vector element"]
4865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
4866#[inline]
4867#[target_feature(enable = "neon")]
4868#[cfg_attr(
4869    all(test, target_endian = "little"),
4870    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4871)]
4872#[rustc_legacy_const_generics(1, 3)]
4873#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4874pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
4875    a: int32x2_t,
4876    b: int32x4_t,
4877) -> int32x2_t {
4878    static_assert_uimm_bits!(LANE1, 1);
4879    static_assert_uimm_bits!(LANE2, 2);
4880    vset_lane_s32::<LANE1>(vgetq_lane_s32::<LANE2>(b), a)
4881}
4882#[doc = "Insert vector element from another vector element"]
4883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
4884#[inline]
4885#[target_feature(enable = "neon")]
4886#[cfg_attr(
4887    all(test, target_endian = "little"),
4888    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4889)]
4890#[rustc_legacy_const_generics(1, 3)]
4891#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4892pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
4893    a: uint8x8_t,
4894    b: uint8x16_t,
4895) -> uint8x8_t {
4896    static_assert_uimm_bits!(LANE1, 3);
4897    static_assert_uimm_bits!(LANE2, 4);
4898    vset_lane_u8::<LANE1>(vgetq_lane_u8::<LANE2>(b), a)
4899}
4900#[doc = "Insert vector element from another vector element"]
4901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
4902#[inline]
4903#[target_feature(enable = "neon")]
4904#[cfg_attr(
4905    all(test, target_endian = "little"),
4906    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4907)]
4908#[rustc_legacy_const_generics(1, 3)]
4909#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4910pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
4911    a: uint16x4_t,
4912    b: uint16x8_t,
4913) -> uint16x4_t {
4914    static_assert_uimm_bits!(LANE1, 2);
4915    static_assert_uimm_bits!(LANE2, 3);
4916    vset_lane_u16::<LANE1>(vgetq_lane_u16::<LANE2>(b), a)
4917}
4918#[doc = "Insert vector element from another vector element"]
4919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
4920#[inline]
4921#[target_feature(enable = "neon")]
4922#[cfg_attr(
4923    all(test, target_endian = "little"),
4924    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4925)]
4926#[rustc_legacy_const_generics(1, 3)]
4927#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4928pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
4929    a: uint32x2_t,
4930    b: uint32x4_t,
4931) -> uint32x2_t {
4932    static_assert_uimm_bits!(LANE1, 1);
4933    static_assert_uimm_bits!(LANE2, 2);
4934    vset_lane_u32::<LANE1>(vgetq_lane_u32::<LANE2>(b), a)
4935}
4936#[doc = "Insert vector element from another vector element"]
4937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
4938#[inline]
4939#[target_feature(enable = "neon")]
4940#[cfg_attr(
4941    all(test, target_endian = "little"),
4942    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4943)]
4944#[rustc_legacy_const_generics(1, 3)]
4945#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4946pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
4947    a: poly8x8_t,
4948    b: poly8x16_t,
4949) -> poly8x8_t {
4950    static_assert_uimm_bits!(LANE1, 3);
4951    static_assert_uimm_bits!(LANE2, 4);
4952    vset_lane_p8::<LANE1>(vgetq_lane_p8::<LANE2>(b), a)
4953}
4954#[doc = "Insert vector element from another vector element"]
4955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
4956#[inline]
4957#[target_feature(enable = "neon")]
4958#[cfg_attr(
4959    all(test, target_endian = "little"),
4960    assert_instr(mov, LANE1 = 0, LANE2 = 0)
4961)]
4962#[rustc_legacy_const_generics(1, 3)]
4963#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4964pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
4965    a: poly16x4_t,
4966    b: poly16x8_t,
4967) -> poly16x4_t {
4968    static_assert_uimm_bits!(LANE1, 2);
4969    static_assert_uimm_bits!(LANE2, 3);
4970    vset_lane_p16::<LANE1>(vgetq_lane_p16::<LANE2>(b), a)
4971}
4972#[doc = "Insert vector element from another vector element"]
4973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f64)"]
4974#[inline]
4975#[target_feature(enable = "neon")]
4976#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
4977#[rustc_legacy_const_generics(1, 3)]
4978#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4979pub fn vcopy_laneq_f64<const LANE1: i32, const LANE2: i32>(
4980    _a: float64x1_t,
4981    b: float64x2_t,
4982) -> float64x1_t {
4983    static_assert!(LANE1 == 0);
4984    static_assert_uimm_bits!(LANE2, 1);
4985    unsafe { transmute(vgetq_lane_f64::<LANE2>(b)) }
4986}
4987#[doc = "Insert vector element from another vector element"]
4988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s64)"]
4989#[inline]
4990#[target_feature(enable = "neon")]
4991#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
4992#[rustc_legacy_const_generics(1, 3)]
4993#[stable(feature = "neon_intrinsics", since = "1.59.0")]
4994pub fn vcopy_laneq_s64<const LANE1: i32, const LANE2: i32>(
4995    _a: int64x1_t,
4996    b: int64x2_t,
4997) -> int64x1_t {
4998    static_assert!(LANE1 == 0);
4999    static_assert_uimm_bits!(LANE2, 1);
5000    unsafe { transmute(vgetq_lane_s64::<LANE2>(b)) }
5001}
5002#[doc = "Insert vector element from another vector element"]
5003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u64)"]
5004#[inline]
5005#[target_feature(enable = "neon")]
5006#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
5007#[rustc_legacy_const_generics(1, 3)]
5008#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5009pub fn vcopy_laneq_u64<const LANE1: i32, const LANE2: i32>(
5010    _a: uint64x1_t,
5011    b: uint64x2_t,
5012) -> uint64x1_t {
5013    static_assert!(LANE1 == 0);
5014    static_assert_uimm_bits!(LANE2, 1);
5015    unsafe { transmute(vgetq_lane_u64::<LANE2>(b)) }
5016}
5017#[doc = "Insert vector element from another vector element"]
5018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p64)"]
5019#[inline]
5020#[target_feature(enable = "neon")]
5021#[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))]
5022#[rustc_legacy_const_generics(1, 3)]
5023#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5024pub fn vcopy_laneq_p64<const LANE1: i32, const LANE2: i32>(
5025    _a: poly64x1_t,
5026    b: poly64x2_t,
5027) -> poly64x1_t {
5028    static_assert!(LANE1 == 0);
5029    static_assert_uimm_bits!(LANE2, 1);
5030    unsafe { transmute(vgetq_lane_p64::<LANE2>(b)) }
5031}
5032#[doc = "Insert vector element from another vector element"]
5033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"]
5034#[inline]
5035#[target_feature(enable = "neon")]
5036#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
5037#[rustc_legacy_const_generics(1, 3)]
5038#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5039pub fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(
5040    a: float32x4_t,
5041    b: float32x2_t,
5042) -> float32x4_t {
5043    static_assert_uimm_bits!(LANE1, 2);
5044    static_assert_uimm_bits!(LANE2, 1);
5045    vsetq_lane_f32::<LANE1>(vget_lane_f32::<LANE2>(b), a)
5046}
5047#[doc = "Insert vector element from another vector element"]
5048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"]
5049#[inline]
5050#[target_feature(enable = "neon")]
5051#[cfg_attr(
5052    all(test, target_endian = "little"),
5053    assert_instr(mov, LANE1 = 1, LANE2 = 0)
5054)]
5055#[rustc_legacy_const_generics(1, 3)]
5056#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5057pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
5058    a: float64x2_t,
5059    b: float64x1_t,
5060) -> float64x2_t {
5061    static_assert_uimm_bits!(LANE1, 1);
5062    static_assert!(LANE2 == 0);
5063    let b: float64x2_t = vcombine_f64(b, b);
5064    vsetq_lane_f64::<LANE1>(vgetq_lane_f64::<LANE2>(b), a)
5065}
5066#[doc = "Insert vector element from another vector element"]
5067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"]
5068#[inline]
5069#[target_feature(enable = "neon")]
5070#[cfg_attr(
5071    all(test, target_endian = "little"),
5072    assert_instr(mov, LANE1 = 1, LANE2 = 0)
5073)]
5074#[rustc_legacy_const_generics(1, 3)]
5075#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5076pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
5077    a: int64x2_t,
5078    b: int64x1_t,
5079) -> int64x2_t {
5080    static_assert_uimm_bits!(LANE1, 1);
5081    static_assert!(LANE2 == 0);
5082    let b: int64x2_t = vcombine_s64(b, b);
5083    vsetq_lane_s64::<LANE1>(vgetq_lane_s64::<LANE2>(b), a)
5084}
5085#[doc = "Insert vector element from another vector element"]
5086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"]
5087#[inline]
5088#[target_feature(enable = "neon")]
5089#[cfg_attr(
5090    all(test, target_endian = "little"),
5091    assert_instr(mov, LANE1 = 1, LANE2 = 0)
5092)]
5093#[rustc_legacy_const_generics(1, 3)]
5094#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5095pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
5096    a: uint64x2_t,
5097    b: uint64x1_t,
5098) -> uint64x2_t {
5099    static_assert_uimm_bits!(LANE1, 1);
5100    static_assert!(LANE2 == 0);
5101    let b: uint64x2_t = vcombine_u64(b, b);
5102    vsetq_lane_u64::<LANE1>(vgetq_lane_u64::<LANE2>(b), a)
5103}
5104#[doc = "Insert vector element from another vector element"]
5105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
5106#[inline]
5107#[cfg(target_endian = "little")]
5108#[target_feature(enable = "neon")]
5109#[cfg_attr(
5110    all(test, target_endian = "little"),
5111    assert_instr(mov, LANE1 = 1, LANE2 = 0)
5112)]
5113#[rustc_legacy_const_generics(1, 3)]
5114#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5115pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
5116    a: poly64x2_t,
5117    b: poly64x1_t,
5118) -> poly64x2_t {
5119    static_assert_uimm_bits!(LANE1, 1);
5120    static_assert!(LANE2 == 0);
5121    let b: poly64x2_t = vcombine_p64(b, b);
5122    unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) }
5123}
5124#[doc = "Insert vector element from another vector element"]
5125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
5126#[inline]
5127#[cfg(target_endian = "big")]
5128#[target_feature(enable = "neon")]
5129#[cfg_attr(
5130    all(test, target_endian = "little"),
5131    assert_instr(mov, LANE1 = 1, LANE2 = 0)
5132)]
5133#[rustc_legacy_const_generics(1, 3)]
5134#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5135pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
5136    a: poly64x2_t,
5137    b: poly64x1_t,
5138) -> poly64x2_t {
5139    static_assert_uimm_bits!(LANE1, 1);
5140    static_assert!(LANE2 == 0);
5141    unsafe {
5142        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
5143        let b: poly64x2_t = vcombine_p64(b, b);
5144        let ret_val: poly64x2_t =
5145            simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64));
5146        simd_shuffle!(ret_val, ret_val, [1, 0])
5147    }
5148}
5149#[doc = "Insert vector element from another vector element"]
5150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
5151#[inline]
5152#[target_feature(enable = "neon")]
5153#[cfg_attr(
5154    all(test, target_endian = "little"),
5155    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5156)]
5157#[rustc_legacy_const_generics(1, 3)]
5158#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5159pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x8_t) -> int8x16_t {
5160    static_assert_uimm_bits!(LANE1, 4);
5161    static_assert_uimm_bits!(LANE2, 3);
5162    let b: int8x16_t = vcombine_s8(b, b);
5163    vsetq_lane_s8::<LANE1>(vgetq_lane_s8::<LANE2>(b), a)
5164}
5165#[doc = "Insert vector element from another vector element"]
5166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
5167#[inline]
5168#[target_feature(enable = "neon")]
5169#[cfg_attr(
5170    all(test, target_endian = "little"),
5171    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5172)]
5173#[rustc_legacy_const_generics(1, 3)]
5174#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5175pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
5176    a: int16x8_t,
5177    b: int16x4_t,
5178) -> int16x8_t {
5179    static_assert_uimm_bits!(LANE1, 3);
5180    static_assert_uimm_bits!(LANE2, 2);
5181    let b: int16x8_t = vcombine_s16(b, b);
5182    vsetq_lane_s16::<LANE1>(vgetq_lane_s16::<LANE2>(b), a)
5183}
5184#[doc = "Insert vector element from another vector element"]
5185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
5186#[inline]
5187#[target_feature(enable = "neon")]
5188#[cfg_attr(
5189    all(test, target_endian = "little"),
5190    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5191)]
5192#[rustc_legacy_const_generics(1, 3)]
5193#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5194pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
5195    a: int32x4_t,
5196    b: int32x2_t,
5197) -> int32x4_t {
5198    static_assert_uimm_bits!(LANE1, 2);
5199    static_assert_uimm_bits!(LANE2, 1);
5200    let b: int32x4_t = vcombine_s32(b, b);
5201    vsetq_lane_s32::<LANE1>(vgetq_lane_s32::<LANE2>(b), a)
5202}
5203#[doc = "Insert vector element from another vector element"]
5204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
5205#[inline]
5206#[target_feature(enable = "neon")]
5207#[cfg_attr(
5208    all(test, target_endian = "little"),
5209    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5210)]
5211#[rustc_legacy_const_generics(1, 3)]
5212#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5213pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
5214    a: uint8x16_t,
5215    b: uint8x8_t,
5216) -> uint8x16_t {
5217    static_assert_uimm_bits!(LANE1, 4);
5218    static_assert_uimm_bits!(LANE2, 3);
5219    let b: uint8x16_t = vcombine_u8(b, b);
5220    vsetq_lane_u8::<LANE1>(vgetq_lane_u8::<LANE2>(b), a)
5221}
5222#[doc = "Insert vector element from another vector element"]
5223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
5224#[inline]
5225#[target_feature(enable = "neon")]
5226#[cfg_attr(
5227    all(test, target_endian = "little"),
5228    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5229)]
5230#[rustc_legacy_const_generics(1, 3)]
5231#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5232pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
5233    a: uint16x8_t,
5234    b: uint16x4_t,
5235) -> uint16x8_t {
5236    static_assert_uimm_bits!(LANE1, 3);
5237    static_assert_uimm_bits!(LANE2, 2);
5238    let b: uint16x8_t = vcombine_u16(b, b);
5239    vsetq_lane_u16::<LANE1>(vgetq_lane_u16::<LANE2>(b), a)
5240}
5241#[doc = "Insert vector element from another vector element"]
5242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
5243#[inline]
5244#[target_feature(enable = "neon")]
5245#[cfg_attr(
5246    all(test, target_endian = "little"),
5247    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5248)]
5249#[rustc_legacy_const_generics(1, 3)]
5250#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5251pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
5252    a: uint32x4_t,
5253    b: uint32x2_t,
5254) -> uint32x4_t {
5255    static_assert_uimm_bits!(LANE1, 2);
5256    static_assert_uimm_bits!(LANE2, 1);
5257    let b: uint32x4_t = vcombine_u32(b, b);
5258    vsetq_lane_u32::<LANE1>(vgetq_lane_u32::<LANE2>(b), a)
5259}
5260#[doc = "Insert vector element from another vector element"]
5261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
5262#[inline]
5263#[target_feature(enable = "neon")]
5264#[cfg_attr(
5265    all(test, target_endian = "little"),
5266    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5267)]
5268#[rustc_legacy_const_generics(1, 3)]
5269#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5270pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
5271    a: poly8x16_t,
5272    b: poly8x8_t,
5273) -> poly8x16_t {
5274    static_assert_uimm_bits!(LANE1, 4);
5275    static_assert_uimm_bits!(LANE2, 3);
5276    let b: poly8x16_t = vcombine_p8(b, b);
5277    vsetq_lane_p8::<LANE1>(vgetq_lane_p8::<LANE2>(b), a)
5278}
5279#[doc = "Insert vector element from another vector element"]
5280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
5281#[inline]
5282#[target_feature(enable = "neon")]
5283#[cfg_attr(
5284    all(test, target_endian = "little"),
5285    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5286)]
5287#[rustc_legacy_const_generics(1, 3)]
5288#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5289pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
5290    a: poly16x8_t,
5291    b: poly16x4_t,
5292) -> poly16x8_t {
5293    static_assert_uimm_bits!(LANE1, 3);
5294    static_assert_uimm_bits!(LANE2, 2);
5295    let b: poly16x8_t = vcombine_p16(b, b);
5296    vsetq_lane_p16::<LANE1>(vgetq_lane_p16::<LANE2>(b), a)
5297}
5298#[doc = "Insert vector element from another vector element"]
5299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
5300#[inline]
5301#[target_feature(enable = "neon")]
5302#[cfg_attr(
5303    all(test, target_endian = "little"),
5304    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5305)]
5306#[rustc_legacy_const_generics(1, 3)]
5307#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5308pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
5309    a: float32x4_t,
5310    b: float32x4_t,
5311) -> float32x4_t {
5312    static_assert_uimm_bits!(LANE1, 2);
5313    static_assert_uimm_bits!(LANE2, 2);
5314    vsetq_lane_f32::<LANE1>(vgetq_lane_f32::<LANE2>(b), a)
5315}
5316#[doc = "Insert vector element from another vector element"]
5317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
5318#[inline]
5319#[target_feature(enable = "neon")]
5320#[cfg_attr(
5321    all(test, target_endian = "little"),
5322    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5323)]
5324#[rustc_legacy_const_generics(1, 3)]
5325#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5326pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
5327    a: float64x2_t,
5328    b: float64x2_t,
5329) -> float64x2_t {
5330    static_assert_uimm_bits!(LANE1, 1);
5331    static_assert_uimm_bits!(LANE2, 1);
5332    vsetq_lane_f64::<LANE1>(vgetq_lane_f64::<LANE2>(b), a)
5333}
5334#[doc = "Insert vector element from another vector element"]
5335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
5336#[inline]
5337#[target_feature(enable = "neon")]
5338#[cfg_attr(
5339    all(test, target_endian = "little"),
5340    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5341)]
5342#[rustc_legacy_const_generics(1, 3)]
5343#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5344pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
5345    a: int8x16_t,
5346    b: int8x16_t,
5347) -> int8x16_t {
5348    static_assert_uimm_bits!(LANE1, 4);
5349    static_assert_uimm_bits!(LANE2, 4);
5350    vsetq_lane_s8::<LANE1>(vgetq_lane_s8::<LANE2>(b), a)
5351}
5352#[doc = "Insert vector element from another vector element"]
5353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
5354#[inline]
5355#[target_feature(enable = "neon")]
5356#[cfg_attr(
5357    all(test, target_endian = "little"),
5358    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5359)]
5360#[rustc_legacy_const_generics(1, 3)]
5361#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5362pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
5363    a: int16x8_t,
5364    b: int16x8_t,
5365) -> int16x8_t {
5366    static_assert_uimm_bits!(LANE1, 3);
5367    static_assert_uimm_bits!(LANE2, 3);
5368    vsetq_lane_s16::<LANE1>(vgetq_lane_s16::<LANE2>(b), a)
5369}
5370#[doc = "Insert vector element from another vector element"]
5371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
5372#[inline]
5373#[target_feature(enable = "neon")]
5374#[cfg_attr(
5375    all(test, target_endian = "little"),
5376    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5377)]
5378#[rustc_legacy_const_generics(1, 3)]
5379#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5380pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
5381    a: int32x4_t,
5382    b: int32x4_t,
5383) -> int32x4_t {
5384    static_assert_uimm_bits!(LANE1, 2);
5385    static_assert_uimm_bits!(LANE2, 2);
5386    vsetq_lane_s32::<LANE1>(vgetq_lane_s32::<LANE2>(b), a)
5387}
5388#[doc = "Insert vector element from another vector element"]
5389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
5390#[inline]
5391#[target_feature(enable = "neon")]
5392#[cfg_attr(
5393    all(test, target_endian = "little"),
5394    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5395)]
5396#[rustc_legacy_const_generics(1, 3)]
5397#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5398pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
5399    a: int64x2_t,
5400    b: int64x2_t,
5401) -> int64x2_t {
5402    static_assert_uimm_bits!(LANE1, 1);
5403    static_assert_uimm_bits!(LANE2, 1);
5404    vsetq_lane_s64::<LANE1>(vgetq_lane_s64::<LANE2>(b), a)
5405}
5406#[doc = "Insert vector element from another vector element"]
5407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
5408#[inline]
5409#[target_feature(enable = "neon")]
5410#[cfg_attr(
5411    all(test, target_endian = "little"),
5412    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5413)]
5414#[rustc_legacy_const_generics(1, 3)]
5415#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5416pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
5417    a: uint8x16_t,
5418    b: uint8x16_t,
5419) -> uint8x16_t {
5420    static_assert_uimm_bits!(LANE1, 4);
5421    static_assert_uimm_bits!(LANE2, 4);
5422    vsetq_lane_u8::<LANE1>(vgetq_lane_u8::<LANE2>(b), a)
5423}
5424#[doc = "Insert vector element from another vector element"]
5425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
5426#[inline]
5427#[target_feature(enable = "neon")]
5428#[cfg_attr(
5429    all(test, target_endian = "little"),
5430    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5431)]
5432#[rustc_legacy_const_generics(1, 3)]
5433#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5434pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
5435    a: uint16x8_t,
5436    b: uint16x8_t,
5437) -> uint16x8_t {
5438    static_assert_uimm_bits!(LANE1, 3);
5439    static_assert_uimm_bits!(LANE2, 3);
5440    vsetq_lane_u16::<LANE1>(vgetq_lane_u16::<LANE2>(b), a)
5441}
5442#[doc = "Insert vector element from another vector element"]
5443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
5444#[inline]
5445#[target_feature(enable = "neon")]
5446#[cfg_attr(
5447    all(test, target_endian = "little"),
5448    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5449)]
5450#[rustc_legacy_const_generics(1, 3)]
5451#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5452pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
5453    a: uint32x4_t,
5454    b: uint32x4_t,
5455) -> uint32x4_t {
5456    static_assert_uimm_bits!(LANE1, 2);
5457    static_assert_uimm_bits!(LANE2, 2);
5458    vsetq_lane_u32::<LANE1>(vgetq_lane_u32::<LANE2>(b), a)
5459}
5460#[doc = "Insert vector element from another vector element"]
5461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
5462#[inline]
5463#[target_feature(enable = "neon")]
5464#[cfg_attr(
5465    all(test, target_endian = "little"),
5466    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5467)]
5468#[rustc_legacy_const_generics(1, 3)]
5469#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5470pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
5471    a: uint64x2_t,
5472    b: uint64x2_t,
5473) -> uint64x2_t {
5474    static_assert_uimm_bits!(LANE1, 1);
5475    static_assert_uimm_bits!(LANE2, 1);
5476    vsetq_lane_u64::<LANE1>(vgetq_lane_u64::<LANE2>(b), a)
5477}
5478#[doc = "Insert vector element from another vector element"]
5479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
5480#[inline]
5481#[target_feature(enable = "neon")]
5482#[cfg_attr(
5483    all(test, target_endian = "little"),
5484    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5485)]
5486#[rustc_legacy_const_generics(1, 3)]
5487#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5488pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
5489    a: poly8x16_t,
5490    b: poly8x16_t,
5491) -> poly8x16_t {
5492    static_assert_uimm_bits!(LANE1, 4);
5493    static_assert_uimm_bits!(LANE2, 4);
5494    vsetq_lane_p8::<LANE1>(vgetq_lane_p8::<LANE2>(b), a)
5495}
5496#[doc = "Insert vector element from another vector element"]
5497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
5498#[inline]
5499#[target_feature(enable = "neon")]
5500#[cfg_attr(
5501    all(test, target_endian = "little"),
5502    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5503)]
5504#[rustc_legacy_const_generics(1, 3)]
5505#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5506pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
5507    a: poly16x8_t,
5508    b: poly16x8_t,
5509) -> poly16x8_t {
5510    static_assert_uimm_bits!(LANE1, 3);
5511    static_assert_uimm_bits!(LANE2, 3);
5512    vsetq_lane_p16::<LANE1>(vgetq_lane_p16::<LANE2>(b), a)
5513}
5514#[doc = "Insert vector element from another vector element"]
5515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
5516#[inline]
5517#[cfg(target_endian = "little")]
5518#[target_feature(enable = "neon")]
5519#[cfg_attr(
5520    all(test, target_endian = "little"),
5521    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5522)]
5523#[rustc_legacy_const_generics(1, 3)]
5524#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5525pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
5526    a: poly64x2_t,
5527    b: poly64x2_t,
5528) -> poly64x2_t {
5529    static_assert_uimm_bits!(LANE1, 1);
5530    static_assert_uimm_bits!(LANE2, 1);
5531    unsafe { simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64)) }
5532}
5533#[doc = "Insert vector element from another vector element"]
5534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
5535#[inline]
5536#[cfg(target_endian = "big")]
5537#[target_feature(enable = "neon")]
5538#[cfg_attr(
5539    all(test, target_endian = "little"),
5540    assert_instr(mov, LANE1 = 0, LANE2 = 0)
5541)]
5542#[rustc_legacy_const_generics(1, 3)]
5543#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5544pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
5545    a: poly64x2_t,
5546    b: poly64x2_t,
5547) -> poly64x2_t {
5548    static_assert_uimm_bits!(LANE1, 1);
5549    static_assert_uimm_bits!(LANE2, 1);
5550    unsafe {
5551        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
5552        let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]);
5553        let ret_val: poly64x2_t =
5554            simd_insert!(a, LANE1 as u32, simd_extract!(b, LANE2 as u32, p64));
5555        simd_shuffle!(ret_val, ret_val, [1, 0])
5556    }
5557}
5558#[doc = "Insert vector element from another vector element"]
5559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"]
5560#[inline]
5561#[target_feature(enable = "neon")]
5562#[cfg_attr(test, assert_instr(nop))]
5563#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5564pub fn vcreate_f64(a: u64) -> float64x1_t {
5565    unsafe { transmute(a) }
5566}
5567#[doc = "Floating-point convert"]
5568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"]
5569#[inline]
5570#[target_feature(enable = "neon")]
5571#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn))]
5572#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5573pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t {
5574    unsafe { simd_cast(a) }
5575}
5576#[doc = "Floating-point convert to higher precision long"]
5577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"]
5578#[inline]
5579#[target_feature(enable = "neon")]
5580#[cfg_attr(test, assert_instr(fcvtl))]
5581#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5582pub fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t {
5583    unsafe { simd_cast(a) }
5584}
5585#[doc = "Fixed-point convert to floating-point"]
5586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"]
5587#[inline]
5588#[target_feature(enable = "neon")]
5589#[cfg_attr(test, assert_instr(scvtf))]
5590#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5591pub fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t {
5592    unsafe { simd_cast(a) }
5593}
5594#[doc = "Fixed-point convert to floating-point"]
5595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"]
5596#[inline]
5597#[target_feature(enable = "neon")]
5598#[cfg_attr(test, assert_instr(scvtf))]
5599#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5600pub fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t {
5601    unsafe { simd_cast(a) }
5602}
5603#[doc = "Fixed-point convert to floating-point"]
5604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"]
5605#[inline]
5606#[target_feature(enable = "neon")]
5607#[cfg_attr(test, assert_instr(ucvtf))]
5608#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5609pub fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t {
5610    unsafe { simd_cast(a) }
5611}
5612#[doc = "Fixed-point convert to floating-point"]
5613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"]
5614#[inline]
5615#[target_feature(enable = "neon")]
5616#[cfg_attr(test, assert_instr(ucvtf))]
5617#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5618pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
5619    unsafe { simd_cast(a) }
5620}
5621#[doc = "Floating-point convert to lower precision"]
5622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"]
5623#[inline]
5624#[target_feature(enable = "neon")]
5625#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))]
5626#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
5627#[cfg(not(target_arch = "arm64ec"))]
5628pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
5629    vcombine_f16(a, vcvt_f16_f32(b))
5630}
5631#[doc = "Floating-point convert to higher precision"]
5632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"]
5633#[inline]
5634#[target_feature(enable = "neon")]
5635#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))]
5636#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
5637#[cfg(not(target_arch = "arm64ec"))]
5638pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
5639    vcvt_f32_f16(vget_high_f16(a))
5640}
5641#[doc = "Floating-point convert to lower precision narrow"]
5642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"]
5643#[inline]
5644#[target_feature(enable = "neon")]
5645#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))]
5646#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5647pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
5648    vcombine_f32(a, vcvt_f32_f64(b))
5649}
5650#[doc = "Floating-point convert to higher precision long"]
5651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
5652#[inline]
5653#[target_feature(enable = "neon")]
5654#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))]
5655#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5656pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
5657    unsafe { simd_cast(vget_high_f32(a)) }
5658}
5659#[doc = "Fixed-point convert to floating-point"]
5660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"]
5661#[inline]
5662#[target_feature(enable = "neon")]
5663#[cfg_attr(test, assert_instr(scvtf, N = 2))]
5664#[rustc_legacy_const_generics(1)]
5665#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5666pub fn vcvt_n_f64_s64<const N: i32>(a: int64x1_t) -> float64x1_t {
5667    static_assert!(N >= 1 && N <= 64);
5668    unsafe extern "unadjusted" {
5669        #[cfg_attr(
5670            any(target_arch = "aarch64", target_arch = "arm64ec"),
5671            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64"
5672        )]
5673        fn _vcvt_n_f64_s64(a: int64x1_t, n: i32) -> float64x1_t;
5674    }
5675    unsafe { _vcvt_n_f64_s64(a, N) }
5676}
5677#[doc = "Fixed-point convert to floating-point"]
5678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"]
5679#[inline]
5680#[target_feature(enable = "neon")]
5681#[cfg_attr(test, assert_instr(scvtf, N = 2))]
5682#[rustc_legacy_const_generics(1)]
5683#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5684pub fn vcvtq_n_f64_s64<const N: i32>(a: int64x2_t) -> float64x2_t {
5685    static_assert!(N >= 1 && N <= 64);
5686    unsafe extern "unadjusted" {
5687        #[cfg_attr(
5688            any(target_arch = "aarch64", target_arch = "arm64ec"),
5689            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64"
5690        )]
5691        fn _vcvtq_n_f64_s64(a: int64x2_t, n: i32) -> float64x2_t;
5692    }
5693    unsafe { _vcvtq_n_f64_s64(a, N) }
5694}
5695#[doc = "Fixed-point convert to floating-point"]
5696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"]
5697#[inline]
5698#[target_feature(enable = "neon")]
5699#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
5700#[rustc_legacy_const_generics(1)]
5701#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5702pub fn vcvt_n_f64_u64<const N: i32>(a: uint64x1_t) -> float64x1_t {
5703    static_assert!(N >= 1 && N <= 64);
5704    unsafe extern "unadjusted" {
5705        #[cfg_attr(
5706            any(target_arch = "aarch64", target_arch = "arm64ec"),
5707            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64"
5708        )]
5709        fn _vcvt_n_f64_u64(a: uint64x1_t, n: i32) -> float64x1_t;
5710    }
5711    unsafe { _vcvt_n_f64_u64(a, N) }
5712}
5713#[doc = "Fixed-point convert to floating-point"]
5714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"]
5715#[inline]
5716#[target_feature(enable = "neon")]
5717#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
5718#[rustc_legacy_const_generics(1)]
5719#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5720pub fn vcvtq_n_f64_u64<const N: i32>(a: uint64x2_t) -> float64x2_t {
5721    static_assert!(N >= 1 && N <= 64);
5722    unsafe extern "unadjusted" {
5723        #[cfg_attr(
5724            any(target_arch = "aarch64", target_arch = "arm64ec"),
5725            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64"
5726        )]
5727        fn _vcvtq_n_f64_u64(a: uint64x2_t, n: i32) -> float64x2_t;
5728    }
5729    unsafe { _vcvtq_n_f64_u64(a, N) }
5730}
5731#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
5732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"]
5733#[inline]
5734#[target_feature(enable = "neon")]
5735#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
5736#[rustc_legacy_const_generics(1)]
5737#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5738pub fn vcvt_n_s64_f64<const N: i32>(a: float64x1_t) -> int64x1_t {
5739    static_assert!(N >= 1 && N <= 64);
5740    unsafe extern "unadjusted" {
5741        #[cfg_attr(
5742            any(target_arch = "aarch64", target_arch = "arm64ec"),
5743            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64"
5744        )]
5745        fn _vcvt_n_s64_f64(a: float64x1_t, n: i32) -> int64x1_t;
5746    }
5747    unsafe { _vcvt_n_s64_f64(a, N) }
5748}
5749#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
5750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"]
5751#[inline]
5752#[target_feature(enable = "neon")]
5753#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
5754#[rustc_legacy_const_generics(1)]
5755#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5756pub fn vcvtq_n_s64_f64<const N: i32>(a: float64x2_t) -> int64x2_t {
5757    static_assert!(N >= 1 && N <= 64);
5758    unsafe extern "unadjusted" {
5759        #[cfg_attr(
5760            any(target_arch = "aarch64", target_arch = "arm64ec"),
5761            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64"
5762        )]
5763        fn _vcvtq_n_s64_f64(a: float64x2_t, n: i32) -> int64x2_t;
5764    }
5765    unsafe { _vcvtq_n_s64_f64(a, N) }
5766}
5767#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
5768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"]
5769#[inline]
5770#[target_feature(enable = "neon")]
5771#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
5772#[rustc_legacy_const_generics(1)]
5773#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5774pub fn vcvt_n_u64_f64<const N: i32>(a: float64x1_t) -> uint64x1_t {
5775    static_assert!(N >= 1 && N <= 64);
5776    unsafe extern "unadjusted" {
5777        #[cfg_attr(
5778            any(target_arch = "aarch64", target_arch = "arm64ec"),
5779            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64"
5780        )]
5781        fn _vcvt_n_u64_f64(a: float64x1_t, n: i32) -> uint64x1_t;
5782    }
5783    unsafe { _vcvt_n_u64_f64(a, N) }
5784}
5785#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
5786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"]
5787#[inline]
5788#[target_feature(enable = "neon")]
5789#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
5790#[rustc_legacy_const_generics(1)]
5791#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5792pub fn vcvtq_n_u64_f64<const N: i32>(a: float64x2_t) -> uint64x2_t {
5793    static_assert!(N >= 1 && N <= 64);
5794    unsafe extern "unadjusted" {
5795        #[cfg_attr(
5796            any(target_arch = "aarch64", target_arch = "arm64ec"),
5797            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64"
5798        )]
5799        fn _vcvtq_n_u64_f64(a: float64x2_t, n: i32) -> uint64x2_t;
5800    }
5801    unsafe { _vcvtq_n_u64_f64(a, N) }
5802}
5803#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
5804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"]
5805#[inline]
5806#[target_feature(enable = "neon")]
5807#[cfg_attr(test, assert_instr(fcvtzs))]
5808#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5809pub fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t {
5810    unsafe extern "unadjusted" {
5811        #[cfg_attr(
5812            any(target_arch = "aarch64", target_arch = "arm64ec"),
5813            link_name = "llvm.fptosi.sat.v1i64.v1f64"
5814        )]
5815        fn _vcvt_s64_f64(a: float64x1_t) -> int64x1_t;
5816    }
5817    unsafe { _vcvt_s64_f64(a) }
5818}
5819#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
5820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"]
5821#[inline]
5822#[target_feature(enable = "neon")]
5823#[cfg_attr(test, assert_instr(fcvtzs))]
5824#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5825pub fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t {
5826    unsafe extern "unadjusted" {
5827        #[cfg_attr(
5828            any(target_arch = "aarch64", target_arch = "arm64ec"),
5829            link_name = "llvm.fptosi.sat.v2i64.v2f64"
5830        )]
5831        fn _vcvtq_s64_f64(a: float64x2_t) -> int64x2_t;
5832    }
5833    unsafe { _vcvtq_s64_f64(a) }
5834}
5835#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
5836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"]
5837#[inline]
5838#[target_feature(enable = "neon")]
5839#[cfg_attr(test, assert_instr(fcvtzu))]
5840#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5841pub fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t {
5842    unsafe extern "unadjusted" {
5843        #[cfg_attr(
5844            any(target_arch = "aarch64", target_arch = "arm64ec"),
5845            link_name = "llvm.fptoui.sat.v1i64.v1f64"
5846        )]
5847        fn _vcvt_u64_f64(a: float64x1_t) -> uint64x1_t;
5848    }
5849    unsafe { _vcvt_u64_f64(a) }
5850}
5851#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
5852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"]
5853#[inline]
5854#[target_feature(enable = "neon")]
5855#[cfg_attr(test, assert_instr(fcvtzu))]
5856#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5857pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t {
5858    unsafe extern "unadjusted" {
5859        #[cfg_attr(
5860            any(target_arch = "aarch64", target_arch = "arm64ec"),
5861            link_name = "llvm.fptoui.sat.v2i64.v2f64"
5862        )]
5863        fn _vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t;
5864    }
5865    unsafe { _vcvtq_u64_f64(a) }
5866}
5867#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
5868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s16_f16)"]
5869#[inline]
5870#[cfg_attr(test, assert_instr(fcvtas))]
5871#[target_feature(enable = "neon,fp16")]
5872#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
5873#[cfg(not(target_arch = "arm64ec"))]
5874pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t {
5875    unsafe extern "unadjusted" {
5876        #[cfg_attr(
5877            any(target_arch = "aarch64", target_arch = "arm64ec"),
5878            link_name = "llvm.aarch64.neon.fcvtas.v4i16.v4f16"
5879        )]
5880        fn _vcvta_s16_f16(a: float16x4_t) -> int16x4_t;
5881    }
5882    unsafe { _vcvta_s16_f16(a) }
5883}
5884#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
5885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s16_f16)"]
5886#[inline]
5887#[cfg_attr(test, assert_instr(fcvtas))]
5888#[target_feature(enable = "neon,fp16")]
5889#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
5890#[cfg(not(target_arch = "arm64ec"))]
5891pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t {
5892    unsafe extern "unadjusted" {
5893        #[cfg_attr(
5894            any(target_arch = "aarch64", target_arch = "arm64ec"),
5895            link_name = "llvm.aarch64.neon.fcvtas.v8i16.v8f16"
5896        )]
5897        fn _vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t;
5898    }
5899    unsafe { _vcvtaq_s16_f16(a) }
5900}
5901#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
5902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"]
5903#[inline]
5904#[target_feature(enable = "neon")]
5905#[cfg_attr(test, assert_instr(fcvtas))]
5906#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5907pub fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t {
5908    unsafe extern "unadjusted" {
5909        #[cfg_attr(
5910            any(target_arch = "aarch64", target_arch = "arm64ec"),
5911            link_name = "llvm.aarch64.neon.fcvtas.v2i32.v2f32"
5912        )]
5913        fn _vcvta_s32_f32(a: float32x2_t) -> int32x2_t;
5914    }
5915    unsafe { _vcvta_s32_f32(a) }
5916}
5917#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
5918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"]
5919#[inline]
5920#[target_feature(enable = "neon")]
5921#[cfg_attr(test, assert_instr(fcvtas))]
5922#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5923pub fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t {
5924    unsafe extern "unadjusted" {
5925        #[cfg_attr(
5926            any(target_arch = "aarch64", target_arch = "arm64ec"),
5927            link_name = "llvm.aarch64.neon.fcvtas.v4i32.v4f32"
5928        )]
5929        fn _vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t;
5930    }
5931    unsafe { _vcvtaq_s32_f32(a) }
5932}
5933#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
5934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"]
5935#[inline]
5936#[target_feature(enable = "neon")]
5937#[cfg_attr(test, assert_instr(fcvtas))]
5938#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5939pub fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t {
5940    unsafe extern "unadjusted" {
5941        #[cfg_attr(
5942            any(target_arch = "aarch64", target_arch = "arm64ec"),
5943            link_name = "llvm.aarch64.neon.fcvtas.v1i64.v1f64"
5944        )]
5945        fn _vcvta_s64_f64(a: float64x1_t) -> int64x1_t;
5946    }
5947    unsafe { _vcvta_s64_f64(a) }
5948}
5949#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
5950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"]
5951#[inline]
5952#[target_feature(enable = "neon")]
5953#[cfg_attr(test, assert_instr(fcvtas))]
5954#[stable(feature = "neon_intrinsics", since = "1.59.0")]
5955pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t {
5956    unsafe extern "unadjusted" {
5957        #[cfg_attr(
5958            any(target_arch = "aarch64", target_arch = "arm64ec"),
5959            link_name = "llvm.aarch64.neon.fcvtas.v2i64.v2f64"
5960        )]
5961        fn _vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t;
5962    }
5963    unsafe { _vcvtaq_s64_f64(a) }
5964}
5965#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
5966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u16_f16)"]
5967#[inline]
5968#[cfg_attr(test, assert_instr(fcvtau))]
5969#[target_feature(enable = "neon,fp16")]
5970#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
5971#[cfg(not(target_arch = "arm64ec"))]
5972pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t {
5973    unsafe extern "unadjusted" {
5974        #[cfg_attr(
5975            any(target_arch = "aarch64", target_arch = "arm64ec"),
5976            link_name = "llvm.aarch64.neon.fcvtau.v4i16.v4f16"
5977        )]
5978        fn _vcvta_u16_f16(a: float16x4_t) -> uint16x4_t;
5979    }
5980    unsafe { _vcvta_u16_f16(a) }
5981}
5982#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
5983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u16_f16)"]
5984#[inline]
5985#[cfg_attr(test, assert_instr(fcvtau))]
5986#[target_feature(enable = "neon,fp16")]
5987#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
5988#[cfg(not(target_arch = "arm64ec"))]
5989pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t {
5990    unsafe extern "unadjusted" {
5991        #[cfg_attr(
5992            any(target_arch = "aarch64", target_arch = "arm64ec"),
5993            link_name = "llvm.aarch64.neon.fcvtau.v8i16.v8f16"
5994        )]
5995        fn _vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t;
5996    }
5997    unsafe { _vcvtaq_u16_f16(a) }
5998}
5999#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
6000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"]
6001#[inline]
6002#[target_feature(enable = "neon")]
6003#[cfg_attr(test, assert_instr(fcvtau))]
6004#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6005pub fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t {
6006    unsafe extern "unadjusted" {
6007        #[cfg_attr(
6008            any(target_arch = "aarch64", target_arch = "arm64ec"),
6009            link_name = "llvm.aarch64.neon.fcvtau.v2i32.v2f32"
6010        )]
6011        fn _vcvta_u32_f32(a: float32x2_t) -> uint32x2_t;
6012    }
6013    unsafe { _vcvta_u32_f32(a) }
6014}
6015#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
6016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)"]
6017#[inline]
6018#[target_feature(enable = "neon")]
6019#[cfg_attr(test, assert_instr(fcvtau))]
6020#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6021pub fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t {
6022    unsafe extern "unadjusted" {
6023        #[cfg_attr(
6024            any(target_arch = "aarch64", target_arch = "arm64ec"),
6025            link_name = "llvm.aarch64.neon.fcvtau.v4i32.v4f32"
6026        )]
6027        fn _vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t;
6028    }
6029    unsafe { _vcvtaq_u32_f32(a) }
6030}
6031#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
6032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)"]
6033#[inline]
6034#[target_feature(enable = "neon")]
6035#[cfg_attr(test, assert_instr(fcvtau))]
6036#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6037pub fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t {
6038    unsafe extern "unadjusted" {
6039        #[cfg_attr(
6040            any(target_arch = "aarch64", target_arch = "arm64ec"),
6041            link_name = "llvm.aarch64.neon.fcvtau.v1i64.v1f64"
6042        )]
6043        fn _vcvta_u64_f64(a: float64x1_t) -> uint64x1_t;
6044    }
6045    unsafe { _vcvta_u64_f64(a) }
6046}
6047#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
6048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)"]
6049#[inline]
6050#[target_feature(enable = "neon")]
6051#[cfg_attr(test, assert_instr(fcvtau))]
6052#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6053pub fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t {
6054    unsafe extern "unadjusted" {
6055        #[cfg_attr(
6056            any(target_arch = "aarch64", target_arch = "arm64ec"),
6057            link_name = "llvm.aarch64.neon.fcvtau.v2i64.v2f64"
6058        )]
6059        fn _vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t;
6060    }
6061    unsafe { _vcvtaq_u64_f64(a) }
6062}
6063#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s16_f16)"]
6065#[inline]
6066#[cfg_attr(test, assert_instr(fcvtas))]
6067#[target_feature(enable = "neon,fp16")]
6068#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6069#[cfg(not(target_arch = "arm64ec"))]
6070pub fn vcvtah_s16_f16(a: f16) -> i16 {
6071    unsafe extern "unadjusted" {
6072        #[cfg_attr(
6073            any(target_arch = "aarch64", target_arch = "arm64ec"),
6074            link_name = "llvm.aarch64.neon.fcvtas.i16.f16"
6075        )]
6076        fn _vcvtah_s16_f16(a: f16) -> i16;
6077    }
6078    unsafe { _vcvtah_s16_f16(a) }
6079}
6080#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s32_f16)"]
6082#[inline]
6083#[cfg_attr(test, assert_instr(fcvtas))]
6084#[target_feature(enable = "neon,fp16")]
6085#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6086#[cfg(not(target_arch = "arm64ec"))]
6087pub fn vcvtah_s32_f16(a: f16) -> i32 {
6088    unsafe extern "unadjusted" {
6089        #[cfg_attr(
6090            any(target_arch = "aarch64", target_arch = "arm64ec"),
6091            link_name = "llvm.aarch64.neon.fcvtas.i32.f16"
6092        )]
6093        fn _vcvtah_s32_f16(a: f16) -> i32;
6094    }
6095    unsafe { _vcvtah_s32_f16(a) }
6096}
6097#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s64_f16)"]
6099#[inline]
6100#[cfg_attr(test, assert_instr(fcvtas))]
6101#[target_feature(enable = "neon,fp16")]
6102#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6103#[cfg(not(target_arch = "arm64ec"))]
6104pub fn vcvtah_s64_f16(a: f16) -> i64 {
6105    unsafe extern "unadjusted" {
6106        #[cfg_attr(
6107            any(target_arch = "aarch64", target_arch = "arm64ec"),
6108            link_name = "llvm.aarch64.neon.fcvtas.i64.f16"
6109        )]
6110        fn _vcvtah_s64_f16(a: f16) -> i64;
6111    }
6112    unsafe { _vcvtah_s64_f16(a) }
6113}
6114#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u16_f16)"]
6116#[inline]
6117#[cfg_attr(test, assert_instr(fcvtau))]
6118#[target_feature(enable = "neon,fp16")]
6119#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6120#[cfg(not(target_arch = "arm64ec"))]
6121pub fn vcvtah_u16_f16(a: f16) -> u16 {
6122    unsafe extern "unadjusted" {
6123        #[cfg_attr(
6124            any(target_arch = "aarch64", target_arch = "arm64ec"),
6125            link_name = "llvm.aarch64.neon.fcvtau.i16.f16"
6126        )]
6127        fn _vcvtah_u16_f16(a: f16) -> u16;
6128    }
6129    unsafe { _vcvtah_u16_f16(a) }
6130}
6131#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u32_f16)"]
6133#[inline]
6134#[cfg_attr(test, assert_instr(fcvtau))]
6135#[target_feature(enable = "neon,fp16")]
6136#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6137#[cfg(not(target_arch = "arm64ec"))]
6138pub fn vcvtah_u32_f16(a: f16) -> u32 {
6139    unsafe extern "unadjusted" {
6140        #[cfg_attr(
6141            any(target_arch = "aarch64", target_arch = "arm64ec"),
6142            link_name = "llvm.aarch64.neon.fcvtau.i32.f16"
6143        )]
6144        fn _vcvtah_u32_f16(a: f16) -> u32;
6145    }
6146    unsafe { _vcvtah_u32_f16(a) }
6147}
6148#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u64_f16)"]
6150#[inline]
6151#[cfg_attr(test, assert_instr(fcvtau))]
6152#[target_feature(enable = "neon,fp16")]
6153#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6154#[cfg(not(target_arch = "arm64ec"))]
6155pub fn vcvtah_u64_f16(a: f16) -> u64 {
6156    unsafe extern "unadjusted" {
6157        #[cfg_attr(
6158            any(target_arch = "aarch64", target_arch = "arm64ec"),
6159            link_name = "llvm.aarch64.neon.fcvtau.i64.f16"
6160        )]
6161        fn _vcvtah_u64_f16(a: f16) -> u64;
6162    }
6163    unsafe { _vcvtah_u64_f16(a) }
6164}
6165#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)"]
6167#[inline]
6168#[target_feature(enable = "neon")]
6169#[cfg_attr(test, assert_instr(fcvtas))]
6170#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6171pub fn vcvtas_s32_f32(a: f32) -> i32 {
6172    unsafe extern "unadjusted" {
6173        #[cfg_attr(
6174            any(target_arch = "aarch64", target_arch = "arm64ec"),
6175            link_name = "llvm.aarch64.neon.fcvtas.i32.f32"
6176        )]
6177        fn _vcvtas_s32_f32(a: f32) -> i32;
6178    }
6179    unsafe { _vcvtas_s32_f32(a) }
6180}
6181#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64)"]
6183#[inline]
6184#[target_feature(enable = "neon")]
6185#[cfg_attr(test, assert_instr(fcvtas))]
6186#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6187pub fn vcvtad_s64_f64(a: f64) -> i64 {
6188    unsafe extern "unadjusted" {
6189        #[cfg_attr(
6190            any(target_arch = "aarch64", target_arch = "arm64ec"),
6191            link_name = "llvm.aarch64.neon.fcvtas.i64.f64"
6192        )]
6193        fn _vcvtad_s64_f64(a: f64) -> i64;
6194    }
6195    unsafe { _vcvtad_s64_f64(a) }
6196}
6197#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)"]
6199#[inline]
6200#[target_feature(enable = "neon")]
6201#[cfg_attr(test, assert_instr(fcvtau))]
6202#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6203pub fn vcvtas_u32_f32(a: f32) -> u32 {
6204    unsafe extern "unadjusted" {
6205        #[cfg_attr(
6206            any(target_arch = "aarch64", target_arch = "arm64ec"),
6207            link_name = "llvm.aarch64.neon.fcvtau.i32.f32"
6208        )]
6209        fn _vcvtas_u32_f32(a: f32) -> u32;
6210    }
6211    unsafe { _vcvtas_u32_f32(a) }
6212}
6213#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
6214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64)"]
6215#[inline]
6216#[target_feature(enable = "neon")]
6217#[cfg_attr(test, assert_instr(fcvtau))]
6218#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6219pub fn vcvtad_u64_f64(a: f64) -> u64 {
6220    unsafe extern "unadjusted" {
6221        #[cfg_attr(
6222            any(target_arch = "aarch64", target_arch = "arm64ec"),
6223            link_name = "llvm.aarch64.neon.fcvtau.i64.f64"
6224        )]
6225        fn _vcvtad_u64_f64(a: f64) -> u64;
6226    }
6227    unsafe { _vcvtad_u64_f64(a) }
6228}
6229#[doc = "Fixed-point convert to floating-point"]
6230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64)"]
6231#[inline]
6232#[target_feature(enable = "neon")]
6233#[cfg_attr(test, assert_instr(scvtf))]
6234#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6235pub fn vcvtd_f64_s64(a: i64) -> f64 {
6236    a as f64
6237}
6238#[doc = "Fixed-point convert to floating-point"]
6239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)"]
6240#[inline]
6241#[target_feature(enable = "neon")]
6242#[cfg_attr(test, assert_instr(scvtf))]
6243#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6244pub fn vcvts_f32_s32(a: i32) -> f32 {
6245    a as f32
6246}
6247#[doc = "Fixed-point convert to floating-point"]
6248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s16)"]
6249#[inline]
6250#[cfg_attr(test, assert_instr(scvtf))]
6251#[target_feature(enable = "neon,fp16")]
6252#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6253#[cfg(not(target_arch = "arm64ec"))]
6254pub fn vcvth_f16_s16(a: i16) -> f16 {
6255    a as f16
6256}
6257#[doc = "Fixed-point convert to floating-point"]
6258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s32)"]
6259#[inline]
6260#[cfg_attr(test, assert_instr(scvtf))]
6261#[target_feature(enable = "neon,fp16")]
6262#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6263#[cfg(not(target_arch = "arm64ec"))]
6264pub fn vcvth_f16_s32(a: i32) -> f16 {
6265    a as f16
6266}
6267#[doc = "Fixed-point convert to floating-point"]
6268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s64)"]
6269#[inline]
6270#[cfg_attr(test, assert_instr(scvtf))]
6271#[target_feature(enable = "neon,fp16")]
6272#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6273#[cfg(not(target_arch = "arm64ec"))]
6274pub fn vcvth_f16_s64(a: i64) -> f16 {
6275    a as f16
6276}
6277#[doc = "Unsigned fixed-point convert to floating-point"]
6278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u16)"]
6279#[inline]
6280#[cfg_attr(test, assert_instr(ucvtf))]
6281#[target_feature(enable = "neon,fp16")]
6282#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6283#[cfg(not(target_arch = "arm64ec"))]
6284pub fn vcvth_f16_u16(a: u16) -> f16 {
6285    a as f16
6286}
6287#[doc = "Unsigned fixed-point convert to floating-point"]
6288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u32)"]
6289#[inline]
6290#[cfg_attr(test, assert_instr(ucvtf))]
6291#[target_feature(enable = "neon,fp16")]
6292#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6293#[cfg(not(target_arch = "arm64ec"))]
6294pub fn vcvth_f16_u32(a: u32) -> f16 {
6295    a as f16
6296}
6297#[doc = "Unsigned fixed-point convert to floating-point"]
6298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u64)"]
6299#[inline]
6300#[cfg_attr(test, assert_instr(ucvtf))]
6301#[target_feature(enable = "neon,fp16")]
6302#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6303#[cfg(not(target_arch = "arm64ec"))]
6304pub fn vcvth_f16_u64(a: u64) -> f16 {
6305    a as f16
6306}
6307#[doc = "Fixed-point convert to floating-point"]
6308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s16)"]
6309#[inline]
6310#[cfg_attr(test, assert_instr(scvtf, N = 2))]
6311#[rustc_legacy_const_generics(1)]
6312#[target_feature(enable = "neon,fp16")]
6313#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6314#[cfg(not(target_arch = "arm64ec"))]
6315pub fn vcvth_n_f16_s16<const N: i32>(a: i16) -> f16 {
6316    static_assert!(N >= 1 && N <= 16);
6317    vcvth_n_f16_s32::<N>(a as i32)
6318}
6319#[doc = "Fixed-point convert to floating-point"]
6320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32)"]
6321#[inline]
6322#[cfg_attr(test, assert_instr(scvtf, N = 2))]
6323#[rustc_legacy_const_generics(1)]
6324#[target_feature(enable = "neon,fp16")]
6325#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6326#[cfg(not(target_arch = "arm64ec"))]
6327pub fn vcvth_n_f16_s32<const N: i32>(a: i32) -> f16 {
6328    static_assert!(N >= 1 && N <= 16);
6329    unsafe extern "unadjusted" {
6330        #[cfg_attr(
6331            any(target_arch = "aarch64", target_arch = "arm64ec"),
6332            link_name = "llvm.aarch64.neon.vcvtfxs2fp.f16.i32"
6333        )]
6334        fn _vcvth_n_f16_s32(a: i32, n: i32) -> f16;
6335    }
6336    unsafe { _vcvth_n_f16_s32(a, N) }
6337}
6338#[doc = "Fixed-point convert to floating-point"]
6339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s64)"]
6340#[inline]
6341#[cfg_attr(test, assert_instr(scvtf, N = 2))]
6342#[rustc_legacy_const_generics(1)]
6343#[target_feature(enable = "neon,fp16")]
6344#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6345#[cfg(not(target_arch = "arm64ec"))]
6346pub fn vcvth_n_f16_s64<const N: i32>(a: i64) -> f16 {
6347    static_assert!(N >= 1 && N <= 16);
6348    unsafe extern "unadjusted" {
6349        #[cfg_attr(
6350            any(target_arch = "aarch64", target_arch = "arm64ec"),
6351            link_name = "llvm.aarch64.neon.vcvtfxs2fp.f16.i64"
6352        )]
6353        fn _vcvth_n_f16_s64(a: i64, n: i32) -> f16;
6354    }
6355    unsafe { _vcvth_n_f16_s64(a, N) }
6356}
6357#[doc = "Fixed-point convert to floating-point"]
6358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u16)"]
6359#[inline]
6360#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
6361#[rustc_legacy_const_generics(1)]
6362#[target_feature(enable = "neon,fp16")]
6363#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6364#[cfg(not(target_arch = "arm64ec"))]
6365pub fn vcvth_n_f16_u16<const N: i32>(a: u16) -> f16 {
6366    static_assert!(N >= 1 && N <= 16);
6367    vcvth_n_f16_u32::<N>(a as u32)
6368}
6369#[doc = "Fixed-point convert to floating-point"]
6370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32)"]
6371#[inline]
6372#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
6373#[rustc_legacy_const_generics(1)]
6374#[target_feature(enable = "neon,fp16")]
6375#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6376#[cfg(not(target_arch = "arm64ec"))]
6377pub fn vcvth_n_f16_u32<const N: i32>(a: u32) -> f16 {
6378    static_assert!(N >= 1 && N <= 16);
6379    unsafe extern "unadjusted" {
6380        #[cfg_attr(
6381            any(target_arch = "aarch64", target_arch = "arm64ec"),
6382            link_name = "llvm.aarch64.neon.vcvtfxu2fp.f16.i32"
6383        )]
6384        fn _vcvth_n_f16_u32(a: u32, n: i32) -> f16;
6385    }
6386    unsafe { _vcvth_n_f16_u32(a, N) }
6387}
6388#[doc = "Fixed-point convert to floating-point"]
6389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u64)"]
6390#[inline]
6391#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
6392#[rustc_legacy_const_generics(1)]
6393#[target_feature(enable = "neon,fp16")]
6394#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6395#[cfg(not(target_arch = "arm64ec"))]
6396pub fn vcvth_n_f16_u64<const N: i32>(a: u64) -> f16 {
6397    static_assert!(N >= 1 && N <= 16);
6398    unsafe extern "unadjusted" {
6399        #[cfg_attr(
6400            any(target_arch = "aarch64", target_arch = "arm64ec"),
6401            link_name = "llvm.aarch64.neon.vcvtfxu2fp.f16.i64"
6402        )]
6403        fn _vcvth_n_f16_u64(a: u64, n: i32) -> f16;
6404    }
6405    unsafe { _vcvth_n_f16_u64(a, N) }
6406}
6407#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s16_f16)"]
6409#[inline]
6410#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
6411#[rustc_legacy_const_generics(1)]
6412#[target_feature(enable = "neon,fp16")]
6413#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6414#[cfg(not(target_arch = "arm64ec"))]
6415pub fn vcvth_n_s16_f16<const N: i32>(a: f16) -> i16 {
6416    static_assert!(N >= 1 && N <= 16);
6417    vcvth_n_s32_f16::<N>(a) as i16
6418}
6419#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s32_f16)"]
6421#[inline]
6422#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
6423#[rustc_legacy_const_generics(1)]
6424#[target_feature(enable = "neon,fp16")]
6425#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6426#[cfg(not(target_arch = "arm64ec"))]
6427pub fn vcvth_n_s32_f16<const N: i32>(a: f16) -> i32 {
6428    static_assert!(N >= 1 && N <= 16);
6429    unsafe extern "unadjusted" {
6430        #[cfg_attr(
6431            any(target_arch = "aarch64", target_arch = "arm64ec"),
6432            link_name = "llvm.aarch64.neon.vcvtfp2fxs.i32.f16"
6433        )]
6434        fn _vcvth_n_s32_f16(a: f16, n: i32) -> i32;
6435    }
6436    unsafe { _vcvth_n_s32_f16(a, N) }
6437}
6438#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s64_f16)"]
6440#[inline]
6441#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
6442#[rustc_legacy_const_generics(1)]
6443#[target_feature(enable = "neon,fp16")]
6444#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6445#[cfg(not(target_arch = "arm64ec"))]
6446pub fn vcvth_n_s64_f16<const N: i32>(a: f16) -> i64 {
6447    static_assert!(N >= 1 && N <= 16);
6448    unsafe extern "unadjusted" {
6449        #[cfg_attr(
6450            any(target_arch = "aarch64", target_arch = "arm64ec"),
6451            link_name = "llvm.aarch64.neon.vcvtfp2fxs.i64.f16"
6452        )]
6453        fn _vcvth_n_s64_f16(a: f16, n: i32) -> i64;
6454    }
6455    unsafe { _vcvth_n_s64_f16(a, N) }
6456}
6457#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u16_f16)"]
6459#[inline]
6460#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
6461#[rustc_legacy_const_generics(1)]
6462#[target_feature(enable = "neon,fp16")]
6463#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6464#[cfg(not(target_arch = "arm64ec"))]
6465pub fn vcvth_n_u16_f16<const N: i32>(a: f16) -> u16 {
6466    static_assert!(N >= 1 && N <= 16);
6467    vcvth_n_u32_f16::<N>(a) as u16
6468}
6469#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u32_f16)"]
6471#[inline]
6472#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
6473#[rustc_legacy_const_generics(1)]
6474#[target_feature(enable = "neon,fp16")]
6475#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6476#[cfg(not(target_arch = "arm64ec"))]
6477pub fn vcvth_n_u32_f16<const N: i32>(a: f16) -> u32 {
6478    static_assert!(N >= 1 && N <= 16);
6479    unsafe extern "unadjusted" {
6480        #[cfg_attr(
6481            any(target_arch = "aarch64", target_arch = "arm64ec"),
6482            link_name = "llvm.aarch64.neon.vcvtfp2fxu.i32.f16"
6483        )]
6484        fn _vcvth_n_u32_f16(a: f16, n: i32) -> u32;
6485    }
6486    unsafe { _vcvth_n_u32_f16(a, N) }
6487}
6488#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
6489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u64_f16)"]
6490#[inline]
6491#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
6492#[rustc_legacy_const_generics(1)]
6493#[target_feature(enable = "neon,fp16")]
6494#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6495#[cfg(not(target_arch = "arm64ec"))]
6496pub fn vcvth_n_u64_f16<const N: i32>(a: f16) -> u64 {
6497    static_assert!(N >= 1 && N <= 16);
6498    unsafe extern "unadjusted" {
6499        #[cfg_attr(
6500            any(target_arch = "aarch64", target_arch = "arm64ec"),
6501            link_name = "llvm.aarch64.neon.vcvtfp2fxu.i64.f16"
6502        )]
6503        fn _vcvth_n_u64_f16(a: f16, n: i32) -> u64;
6504    }
6505    unsafe { _vcvth_n_u64_f16(a, N) }
6506}
6507#[doc = "Floating-point convert to signed fixed-point"]
6508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s16_f16)"]
6509#[inline]
6510#[cfg_attr(test, assert_instr(fcvtzs))]
6511#[target_feature(enable = "neon,fp16")]
6512#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6513#[cfg(not(target_arch = "arm64ec"))]
6514pub fn vcvth_s16_f16(a: f16) -> i16 {
6515    a as i16
6516}
6517#[doc = "Floating-point convert to signed fixed-point"]
6518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s32_f16)"]
6519#[inline]
6520#[cfg_attr(test, assert_instr(fcvtzs))]
6521#[target_feature(enable = "neon,fp16")]
6522#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6523#[cfg(not(target_arch = "arm64ec"))]
6524pub fn vcvth_s32_f16(a: f16) -> i32 {
6525    a as i32
6526}
6527#[doc = "Floating-point convert to signed fixed-point"]
6528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s64_f16)"]
6529#[inline]
6530#[cfg_attr(test, assert_instr(fcvtzs))]
6531#[target_feature(enable = "neon,fp16")]
6532#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6533#[cfg(not(target_arch = "arm64ec"))]
6534pub fn vcvth_s64_f16(a: f16) -> i64 {
6535    a as i64
6536}
6537#[doc = "Floating-point convert to unsigned fixed-point"]
6538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u16_f16)"]
6539#[inline]
6540#[cfg_attr(test, assert_instr(fcvtzu))]
6541#[target_feature(enable = "neon,fp16")]
6542#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6543#[cfg(not(target_arch = "arm64ec"))]
6544pub fn vcvth_u16_f16(a: f16) -> u16 {
6545    a as u16
6546}
6547#[doc = "Floating-point convert to unsigned fixed-point"]
6548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u32_f16)"]
6549#[inline]
6550#[cfg_attr(test, assert_instr(fcvtzu))]
6551#[target_feature(enable = "neon,fp16")]
6552#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6553#[cfg(not(target_arch = "arm64ec"))]
6554pub fn vcvth_u32_f16(a: f16) -> u32 {
6555    a as u32
6556}
6557#[doc = "Floating-point convert to unsigned fixed-point"]
6558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u64_f16)"]
6559#[inline]
6560#[cfg_attr(test, assert_instr(fcvtzu))]
6561#[target_feature(enable = "neon,fp16")]
6562#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6563#[cfg(not(target_arch = "arm64ec"))]
6564pub fn vcvth_u64_f16(a: f16) -> u64 {
6565    a as u64
6566}
6567#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
6568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s16_f16)"]
6569#[inline]
6570#[cfg_attr(test, assert_instr(fcvtms))]
6571#[target_feature(enable = "neon,fp16")]
6572#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
6573#[cfg(not(target_arch = "arm64ec"))]
6574pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t {
6575    unsafe extern "unadjusted" {
6576        #[cfg_attr(
6577            any(target_arch = "aarch64", target_arch = "arm64ec"),
6578            link_name = "llvm.aarch64.neon.fcvtms.v4i16.v4f16"
6579        )]
6580        fn _vcvtm_s16_f16(a: float16x4_t) -> int16x4_t;
6581    }
6582    unsafe { _vcvtm_s16_f16(a) }
6583}
6584#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
6585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s16_f16)"]
6586#[inline]
6587#[cfg_attr(test, assert_instr(fcvtms))]
6588#[target_feature(enable = "neon,fp16")]
6589#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
6590#[cfg(not(target_arch = "arm64ec"))]
6591pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t {
6592    unsafe extern "unadjusted" {
6593        #[cfg_attr(
6594            any(target_arch = "aarch64", target_arch = "arm64ec"),
6595            link_name = "llvm.aarch64.neon.fcvtms.v8i16.v8f16"
6596        )]
6597        fn _vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t;
6598    }
6599    unsafe { _vcvtmq_s16_f16(a) }
6600}
6601#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
6602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)"]
6603#[inline]
6604#[target_feature(enable = "neon")]
6605#[cfg_attr(test, assert_instr(fcvtms))]
6606#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6607pub fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t {
6608    unsafe extern "unadjusted" {
6609        #[cfg_attr(
6610            any(target_arch = "aarch64", target_arch = "arm64ec"),
6611            link_name = "llvm.aarch64.neon.fcvtms.v2i32.v2f32"
6612        )]
6613        fn _vcvtm_s32_f32(a: float32x2_t) -> int32x2_t;
6614    }
6615    unsafe { _vcvtm_s32_f32(a) }
6616}
6617#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
6618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)"]
6619#[inline]
6620#[target_feature(enable = "neon")]
6621#[cfg_attr(test, assert_instr(fcvtms))]
6622#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6623pub fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t {
6624    unsafe extern "unadjusted" {
6625        #[cfg_attr(
6626            any(target_arch = "aarch64", target_arch = "arm64ec"),
6627            link_name = "llvm.aarch64.neon.fcvtms.v4i32.v4f32"
6628        )]
6629        fn _vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t;
6630    }
6631    unsafe { _vcvtmq_s32_f32(a) }
6632}
6633#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
6634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)"]
6635#[inline]
6636#[target_feature(enable = "neon")]
6637#[cfg_attr(test, assert_instr(fcvtms))]
6638#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6639pub fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t {
6640    unsafe extern "unadjusted" {
6641        #[cfg_attr(
6642            any(target_arch = "aarch64", target_arch = "arm64ec"),
6643            link_name = "llvm.aarch64.neon.fcvtms.v1i64.v1f64"
6644        )]
6645        fn _vcvtm_s64_f64(a: float64x1_t) -> int64x1_t;
6646    }
6647    unsafe { _vcvtm_s64_f64(a) }
6648}
6649#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
6650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)"]
6651#[inline]
6652#[target_feature(enable = "neon")]
6653#[cfg_attr(test, assert_instr(fcvtms))]
6654#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6655pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t {
6656    unsafe extern "unadjusted" {
6657        #[cfg_attr(
6658            any(target_arch = "aarch64", target_arch = "arm64ec"),
6659            link_name = "llvm.aarch64.neon.fcvtms.v2i64.v2f64"
6660        )]
6661        fn _vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t;
6662    }
6663    unsafe { _vcvtmq_s64_f64(a) }
6664}
6665#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
6666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u16_f16)"]
6667#[inline]
6668#[cfg_attr(test, assert_instr(fcvtmu))]
6669#[target_feature(enable = "neon,fp16")]
6670#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
6671#[cfg(not(target_arch = "arm64ec"))]
6672pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t {
6673    unsafe extern "unadjusted" {
6674        #[cfg_attr(
6675            any(target_arch = "aarch64", target_arch = "arm64ec"),
6676            link_name = "llvm.aarch64.neon.fcvtmu.v4i16.v4f16"
6677        )]
6678        fn _vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t;
6679    }
6680    unsafe { _vcvtm_u16_f16(a) }
6681}
6682#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
6683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u16_f16)"]
6684#[inline]
6685#[cfg_attr(test, assert_instr(fcvtmu))]
6686#[target_feature(enable = "neon,fp16")]
6687#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
6688#[cfg(not(target_arch = "arm64ec"))]
6689pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t {
6690    unsafe extern "unadjusted" {
6691        #[cfg_attr(
6692            any(target_arch = "aarch64", target_arch = "arm64ec"),
6693            link_name = "llvm.aarch64.neon.fcvtmu.v8i16.v8f16"
6694        )]
6695        fn _vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t;
6696    }
6697    unsafe { _vcvtmq_u16_f16(a) }
6698}
6699#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
6700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)"]
6701#[inline]
6702#[target_feature(enable = "neon")]
6703#[cfg_attr(test, assert_instr(fcvtmu))]
6704#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6705pub fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t {
6706    unsafe extern "unadjusted" {
6707        #[cfg_attr(
6708            any(target_arch = "aarch64", target_arch = "arm64ec"),
6709            link_name = "llvm.aarch64.neon.fcvtmu.v2i32.v2f32"
6710        )]
6711        fn _vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t;
6712    }
6713    unsafe { _vcvtm_u32_f32(a) }
6714}
6715#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
6716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)"]
6717#[inline]
6718#[target_feature(enable = "neon")]
6719#[cfg_attr(test, assert_instr(fcvtmu))]
6720#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6721pub fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t {
6722    unsafe extern "unadjusted" {
6723        #[cfg_attr(
6724            any(target_arch = "aarch64", target_arch = "arm64ec"),
6725            link_name = "llvm.aarch64.neon.fcvtmu.v4i32.v4f32"
6726        )]
6727        fn _vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t;
6728    }
6729    unsafe { _vcvtmq_u32_f32(a) }
6730}
6731#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
6732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)"]
6733#[inline]
6734#[target_feature(enable = "neon")]
6735#[cfg_attr(test, assert_instr(fcvtmu))]
6736#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6737pub fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t {
6738    unsafe extern "unadjusted" {
6739        #[cfg_attr(
6740            any(target_arch = "aarch64", target_arch = "arm64ec"),
6741            link_name = "llvm.aarch64.neon.fcvtmu.v1i64.v1f64"
6742        )]
6743        fn _vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t;
6744    }
6745    unsafe { _vcvtm_u64_f64(a) }
6746}
6747#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
6748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)"]
6749#[inline]
6750#[target_feature(enable = "neon")]
6751#[cfg_attr(test, assert_instr(fcvtmu))]
6752#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6753pub fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t {
6754    unsafe extern "unadjusted" {
6755        #[cfg_attr(
6756            any(target_arch = "aarch64", target_arch = "arm64ec"),
6757            link_name = "llvm.aarch64.neon.fcvtmu.v2i64.v2f64"
6758        )]
6759        fn _vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t;
6760    }
6761    unsafe { _vcvtmq_u64_f64(a) }
6762}
6763#[doc = "Floating-point convert to integer, rounding towards minus infinity"]
6764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s16_f16)"]
6765#[inline]
6766#[cfg_attr(test, assert_instr(fcvtms))]
6767#[target_feature(enable = "neon,fp16")]
6768#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6769#[cfg(not(target_arch = "arm64ec"))]
6770pub fn vcvtmh_s16_f16(a: f16) -> i16 {
6771    unsafe extern "unadjusted" {
6772        #[cfg_attr(
6773            any(target_arch = "aarch64", target_arch = "arm64ec"),
6774            link_name = "llvm.aarch64.neon.fcvtms.i16.f16"
6775        )]
6776        fn _vcvtmh_s16_f16(a: f16) -> i16;
6777    }
6778    unsafe { _vcvtmh_s16_f16(a) }
6779}
6780#[doc = "Floating-point convert to integer, rounding towards minus infinity"]
6781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s32_f16)"]
6782#[inline]
6783#[cfg_attr(test, assert_instr(fcvtms))]
6784#[target_feature(enable = "neon,fp16")]
6785#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6786#[cfg(not(target_arch = "arm64ec"))]
6787pub fn vcvtmh_s32_f16(a: f16) -> i32 {
6788    unsafe extern "unadjusted" {
6789        #[cfg_attr(
6790            any(target_arch = "aarch64", target_arch = "arm64ec"),
6791            link_name = "llvm.aarch64.neon.fcvtms.i32.f16"
6792        )]
6793        fn _vcvtmh_s32_f16(a: f16) -> i32;
6794    }
6795    unsafe { _vcvtmh_s32_f16(a) }
6796}
6797#[doc = "Floating-point convert to integer, rounding towards minus infinity"]
6798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s64_f16)"]
6799#[inline]
6800#[cfg_attr(test, assert_instr(fcvtms))]
6801#[target_feature(enable = "neon,fp16")]
6802#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6803#[cfg(not(target_arch = "arm64ec"))]
6804pub fn vcvtmh_s64_f16(a: f16) -> i64 {
6805    unsafe extern "unadjusted" {
6806        #[cfg_attr(
6807            any(target_arch = "aarch64", target_arch = "arm64ec"),
6808            link_name = "llvm.aarch64.neon.fcvtms.i64.f16"
6809        )]
6810        fn _vcvtmh_s64_f16(a: f16) -> i64;
6811    }
6812    unsafe { _vcvtmh_s64_f16(a) }
6813}
6814#[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
6815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u16_f16)"]
6816#[inline]
6817#[cfg_attr(test, assert_instr(fcvtmu))]
6818#[target_feature(enable = "neon,fp16")]
6819#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6820#[cfg(not(target_arch = "arm64ec"))]
6821pub fn vcvtmh_u16_f16(a: f16) -> u16 {
6822    unsafe extern "unadjusted" {
6823        #[cfg_attr(
6824            any(target_arch = "aarch64", target_arch = "arm64ec"),
6825            link_name = "llvm.aarch64.neon.fcvtmu.i16.f16"
6826        )]
6827        fn _vcvtmh_u16_f16(a: f16) -> u16;
6828    }
6829    unsafe { _vcvtmh_u16_f16(a) }
6830}
6831#[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
6832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u32_f16)"]
6833#[inline]
6834#[cfg_attr(test, assert_instr(fcvtmu))]
6835#[target_feature(enable = "neon,fp16")]
6836#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6837#[cfg(not(target_arch = "arm64ec"))]
6838pub fn vcvtmh_u32_f16(a: f16) -> u32 {
6839    unsafe extern "unadjusted" {
6840        #[cfg_attr(
6841            any(target_arch = "aarch64", target_arch = "arm64ec"),
6842            link_name = "llvm.aarch64.neon.fcvtmu.i32.f16"
6843        )]
6844        fn _vcvtmh_u32_f16(a: f16) -> u32;
6845    }
6846    unsafe { _vcvtmh_u32_f16(a) }
6847}
6848#[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
6849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u64_f16)"]
6850#[inline]
6851#[cfg_attr(test, assert_instr(fcvtmu))]
6852#[target_feature(enable = "neon,fp16")]
6853#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6854#[cfg(not(target_arch = "arm64ec"))]
6855pub fn vcvtmh_u64_f16(a: f16) -> u64 {
6856    unsafe extern "unadjusted" {
6857        #[cfg_attr(
6858            any(target_arch = "aarch64", target_arch = "arm64ec"),
6859            link_name = "llvm.aarch64.neon.fcvtmu.i64.f16"
6860        )]
6861        fn _vcvtmh_u64_f16(a: f16) -> u64;
6862    }
6863    unsafe { _vcvtmh_u64_f16(a) }
6864}
6865#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
6866#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)"]
6867#[inline]
6868#[target_feature(enable = "neon")]
6869#[cfg_attr(test, assert_instr(fcvtms))]
6870#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6871pub fn vcvtms_s32_f32(a: f32) -> i32 {
6872    unsafe extern "unadjusted" {
6873        #[cfg_attr(
6874            any(target_arch = "aarch64", target_arch = "arm64ec"),
6875            link_name = "llvm.aarch64.neon.fcvtms.i32.f32"
6876        )]
6877        fn _vcvtms_s32_f32(a: f32) -> i32;
6878    }
6879    unsafe { _vcvtms_s32_f32(a) }
6880}
6881#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
6882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64)"]
6883#[inline]
6884#[target_feature(enable = "neon")]
6885#[cfg_attr(test, assert_instr(fcvtms))]
6886#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6887pub fn vcvtmd_s64_f64(a: f64) -> i64 {
6888    unsafe extern "unadjusted" {
6889        #[cfg_attr(
6890            any(target_arch = "aarch64", target_arch = "arm64ec"),
6891            link_name = "llvm.aarch64.neon.fcvtms.i64.f64"
6892        )]
6893        fn _vcvtmd_s64_f64(a: f64) -> i64;
6894    }
6895    unsafe { _vcvtmd_s64_f64(a) }
6896}
6897#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
6898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)"]
6899#[inline]
6900#[target_feature(enable = "neon")]
6901#[cfg_attr(test, assert_instr(fcvtmu))]
6902#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6903pub fn vcvtms_u32_f32(a: f32) -> u32 {
6904    unsafe extern "unadjusted" {
6905        #[cfg_attr(
6906            any(target_arch = "aarch64", target_arch = "arm64ec"),
6907            link_name = "llvm.aarch64.neon.fcvtmu.i32.f32"
6908        )]
6909        fn _vcvtms_u32_f32(a: f32) -> u32;
6910    }
6911    unsafe { _vcvtms_u32_f32(a) }
6912}
6913#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
6914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64)"]
6915#[inline]
6916#[target_feature(enable = "neon")]
6917#[cfg_attr(test, assert_instr(fcvtmu))]
6918#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6919pub fn vcvtmd_u64_f64(a: f64) -> u64 {
6920    unsafe extern "unadjusted" {
6921        #[cfg_attr(
6922            any(target_arch = "aarch64", target_arch = "arm64ec"),
6923            link_name = "llvm.aarch64.neon.fcvtmu.i64.f64"
6924        )]
6925        fn _vcvtmd_u64_f64(a: f64) -> u64;
6926    }
6927    unsafe { _vcvtmd_u64_f64(a) }
6928}
6929#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
6930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s16_f16)"]
6931#[inline]
6932#[cfg_attr(test, assert_instr(fcvtns))]
6933#[target_feature(enable = "neon,fp16")]
6934#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
6935#[cfg(not(target_arch = "arm64ec"))]
6936pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t {
6937    unsafe extern "unadjusted" {
6938        #[cfg_attr(
6939            any(target_arch = "aarch64", target_arch = "arm64ec"),
6940            link_name = "llvm.aarch64.neon.fcvtns.v4i16.v4f16"
6941        )]
6942        fn _vcvtn_s16_f16(a: float16x4_t) -> int16x4_t;
6943    }
6944    unsafe { _vcvtn_s16_f16(a) }
6945}
6946#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
6947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s16_f16)"]
6948#[inline]
6949#[cfg_attr(test, assert_instr(fcvtns))]
6950#[target_feature(enable = "neon,fp16")]
6951#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
6952#[cfg(not(target_arch = "arm64ec"))]
6953pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t {
6954    unsafe extern "unadjusted" {
6955        #[cfg_attr(
6956            any(target_arch = "aarch64", target_arch = "arm64ec"),
6957            link_name = "llvm.aarch64.neon.fcvtns.v8i16.v8f16"
6958        )]
6959        fn _vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t;
6960    }
6961    unsafe { _vcvtnq_s16_f16(a) }
6962}
6963#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
6964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)"]
6965#[inline]
6966#[target_feature(enable = "neon")]
6967#[cfg_attr(test, assert_instr(fcvtns))]
6968#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6969pub fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t {
6970    unsafe extern "unadjusted" {
6971        #[cfg_attr(
6972            any(target_arch = "aarch64", target_arch = "arm64ec"),
6973            link_name = "llvm.aarch64.neon.fcvtns.v2i32.v2f32"
6974        )]
6975        fn _vcvtn_s32_f32(a: float32x2_t) -> int32x2_t;
6976    }
6977    unsafe { _vcvtn_s32_f32(a) }
6978}
6979#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
6980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)"]
6981#[inline]
6982#[target_feature(enable = "neon")]
6983#[cfg_attr(test, assert_instr(fcvtns))]
6984#[stable(feature = "neon_intrinsics", since = "1.59.0")]
6985pub fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t {
6986    unsafe extern "unadjusted" {
6987        #[cfg_attr(
6988            any(target_arch = "aarch64", target_arch = "arm64ec"),
6989            link_name = "llvm.aarch64.neon.fcvtns.v4i32.v4f32"
6990        )]
6991        fn _vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t;
6992    }
6993    unsafe { _vcvtnq_s32_f32(a) }
6994}
6995#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
6996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)"]
6997#[inline]
6998#[target_feature(enable = "neon")]
6999#[cfg_attr(test, assert_instr(fcvtns))]
7000#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7001pub fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t {
7002    unsafe extern "unadjusted" {
7003        #[cfg_attr(
7004            any(target_arch = "aarch64", target_arch = "arm64ec"),
7005            link_name = "llvm.aarch64.neon.fcvtns.v1i64.v1f64"
7006        )]
7007        fn _vcvtn_s64_f64(a: float64x1_t) -> int64x1_t;
7008    }
7009    unsafe { _vcvtn_s64_f64(a) }
7010}
7011#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
7012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)"]
7013#[inline]
7014#[target_feature(enable = "neon")]
7015#[cfg_attr(test, assert_instr(fcvtns))]
7016#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7017pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t {
7018    unsafe extern "unadjusted" {
7019        #[cfg_attr(
7020            any(target_arch = "aarch64", target_arch = "arm64ec"),
7021            link_name = "llvm.aarch64.neon.fcvtns.v2i64.v2f64"
7022        )]
7023        fn _vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t;
7024    }
7025    unsafe { _vcvtnq_s64_f64(a) }
7026}
7027#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u16_f16)"]
7029#[inline]
7030#[cfg_attr(test, assert_instr(fcvtnu))]
7031#[target_feature(enable = "neon,fp16")]
7032#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
7033#[cfg(not(target_arch = "arm64ec"))]
7034pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t {
7035    unsafe extern "unadjusted" {
7036        #[cfg_attr(
7037            any(target_arch = "aarch64", target_arch = "arm64ec"),
7038            link_name = "llvm.aarch64.neon.fcvtnu.v4i16.v4f16"
7039        )]
7040        fn _vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t;
7041    }
7042    unsafe { _vcvtn_u16_f16(a) }
7043}
7044#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u16_f16)"]
7046#[inline]
7047#[cfg_attr(test, assert_instr(fcvtnu))]
7048#[target_feature(enable = "neon,fp16")]
7049#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
7050#[cfg(not(target_arch = "arm64ec"))]
7051pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t {
7052    unsafe extern "unadjusted" {
7053        #[cfg_attr(
7054            any(target_arch = "aarch64", target_arch = "arm64ec"),
7055            link_name = "llvm.aarch64.neon.fcvtnu.v8i16.v8f16"
7056        )]
7057        fn _vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t;
7058    }
7059    unsafe { _vcvtnq_u16_f16(a) }
7060}
7061#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)"]
7063#[inline]
7064#[target_feature(enable = "neon")]
7065#[cfg_attr(test, assert_instr(fcvtnu))]
7066#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7067pub fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t {
7068    unsafe extern "unadjusted" {
7069        #[cfg_attr(
7070            any(target_arch = "aarch64", target_arch = "arm64ec"),
7071            link_name = "llvm.aarch64.neon.fcvtnu.v2i32.v2f32"
7072        )]
7073        fn _vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t;
7074    }
7075    unsafe { _vcvtn_u32_f32(a) }
7076}
7077#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)"]
7079#[inline]
7080#[target_feature(enable = "neon")]
7081#[cfg_attr(test, assert_instr(fcvtnu))]
7082#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7083pub fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t {
7084    unsafe extern "unadjusted" {
7085        #[cfg_attr(
7086            any(target_arch = "aarch64", target_arch = "arm64ec"),
7087            link_name = "llvm.aarch64.neon.fcvtnu.v4i32.v4f32"
7088        )]
7089        fn _vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t;
7090    }
7091    unsafe { _vcvtnq_u32_f32(a) }
7092}
7093#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)"]
7095#[inline]
7096#[target_feature(enable = "neon")]
7097#[cfg_attr(test, assert_instr(fcvtnu))]
7098#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7099pub fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t {
7100    unsafe extern "unadjusted" {
7101        #[cfg_attr(
7102            any(target_arch = "aarch64", target_arch = "arm64ec"),
7103            link_name = "llvm.aarch64.neon.fcvtnu.v1i64.v1f64"
7104        )]
7105        fn _vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t;
7106    }
7107    unsafe { _vcvtn_u64_f64(a) }
7108}
7109#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)"]
7111#[inline]
7112#[target_feature(enable = "neon")]
7113#[cfg_attr(test, assert_instr(fcvtnu))]
7114#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7115pub fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t {
7116    unsafe extern "unadjusted" {
7117        #[cfg_attr(
7118            any(target_arch = "aarch64", target_arch = "arm64ec"),
7119            link_name = "llvm.aarch64.neon.fcvtnu.v2i64.v2f64"
7120        )]
7121        fn _vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t;
7122    }
7123    unsafe { _vcvtnq_u64_f64(a) }
7124}
7125#[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
7126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s16_f16)"]
7127#[inline]
7128#[cfg_attr(test, assert_instr(fcvtns))]
7129#[target_feature(enable = "neon,fp16")]
7130#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7131#[cfg(not(target_arch = "arm64ec"))]
7132pub fn vcvtnh_s16_f16(a: f16) -> i16 {
7133    unsafe extern "unadjusted" {
7134        #[cfg_attr(
7135            any(target_arch = "aarch64", target_arch = "arm64ec"),
7136            link_name = "llvm.aarch64.neon.fcvtns.i16.f16"
7137        )]
7138        fn _vcvtnh_s16_f16(a: f16) -> i16;
7139    }
7140    unsafe { _vcvtnh_s16_f16(a) }
7141}
7142#[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
7143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s32_f16)"]
7144#[inline]
7145#[cfg_attr(test, assert_instr(fcvtns))]
7146#[target_feature(enable = "neon,fp16")]
7147#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7148#[cfg(not(target_arch = "arm64ec"))]
7149pub fn vcvtnh_s32_f16(a: f16) -> i32 {
7150    unsafe extern "unadjusted" {
7151        #[cfg_attr(
7152            any(target_arch = "aarch64", target_arch = "arm64ec"),
7153            link_name = "llvm.aarch64.neon.fcvtns.i32.f16"
7154        )]
7155        fn _vcvtnh_s32_f16(a: f16) -> i32;
7156    }
7157    unsafe { _vcvtnh_s32_f16(a) }
7158}
7159#[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
7160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s64_f16)"]
7161#[inline]
7162#[cfg_attr(test, assert_instr(fcvtns))]
7163#[target_feature(enable = "neon,fp16")]
7164#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7165#[cfg(not(target_arch = "arm64ec"))]
7166pub fn vcvtnh_s64_f16(a: f16) -> i64 {
7167    unsafe extern "unadjusted" {
7168        #[cfg_attr(
7169            any(target_arch = "aarch64", target_arch = "arm64ec"),
7170            link_name = "llvm.aarch64.neon.fcvtns.i64.f16"
7171        )]
7172        fn _vcvtnh_s64_f16(a: f16) -> i64;
7173    }
7174    unsafe { _vcvtnh_s64_f16(a) }
7175}
7176#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u16_f16)"]
7178#[inline]
7179#[cfg_attr(test, assert_instr(fcvtnu))]
7180#[target_feature(enable = "neon,fp16")]
7181#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7182#[cfg(not(target_arch = "arm64ec"))]
7183pub fn vcvtnh_u16_f16(a: f16) -> u16 {
7184    unsafe extern "unadjusted" {
7185        #[cfg_attr(
7186            any(target_arch = "aarch64", target_arch = "arm64ec"),
7187            link_name = "llvm.aarch64.neon.fcvtnu.i16.f16"
7188        )]
7189        fn _vcvtnh_u16_f16(a: f16) -> u16;
7190    }
7191    unsafe { _vcvtnh_u16_f16(a) }
7192}
7193#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u32_f16)"]
7195#[inline]
7196#[cfg_attr(test, assert_instr(fcvtnu))]
7197#[target_feature(enable = "neon,fp16")]
7198#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7199#[cfg(not(target_arch = "arm64ec"))]
7200pub fn vcvtnh_u32_f16(a: f16) -> u32 {
7201    unsafe extern "unadjusted" {
7202        #[cfg_attr(
7203            any(target_arch = "aarch64", target_arch = "arm64ec"),
7204            link_name = "llvm.aarch64.neon.fcvtnu.i32.f16"
7205        )]
7206        fn _vcvtnh_u32_f16(a: f16) -> u32;
7207    }
7208    unsafe { _vcvtnh_u32_f16(a) }
7209}
7210#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u64_f16)"]
7212#[inline]
7213#[cfg_attr(test, assert_instr(fcvtnu))]
7214#[target_feature(enable = "neon,fp16")]
7215#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7216#[cfg(not(target_arch = "arm64ec"))]
7217pub fn vcvtnh_u64_f16(a: f16) -> u64 {
7218    unsafe extern "unadjusted" {
7219        #[cfg_attr(
7220            any(target_arch = "aarch64", target_arch = "arm64ec"),
7221            link_name = "llvm.aarch64.neon.fcvtnu.i64.f16"
7222        )]
7223        fn _vcvtnh_u64_f16(a: f16) -> u64;
7224    }
7225    unsafe { _vcvtnh_u64_f16(a) }
7226}
7227#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
7228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)"]
7229#[inline]
7230#[target_feature(enable = "neon")]
7231#[cfg_attr(test, assert_instr(fcvtns))]
7232#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7233pub fn vcvtns_s32_f32(a: f32) -> i32 {
7234    unsafe extern "unadjusted" {
7235        #[cfg_attr(
7236            any(target_arch = "aarch64", target_arch = "arm64ec"),
7237            link_name = "llvm.aarch64.neon.fcvtns.i32.f32"
7238        )]
7239        fn _vcvtns_s32_f32(a: f32) -> i32;
7240    }
7241    unsafe { _vcvtns_s32_f32(a) }
7242}
7243#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
7244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64)"]
7245#[inline]
7246#[target_feature(enable = "neon")]
7247#[cfg_attr(test, assert_instr(fcvtns))]
7248#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7249pub fn vcvtnd_s64_f64(a: f64) -> i64 {
7250    unsafe extern "unadjusted" {
7251        #[cfg_attr(
7252            any(target_arch = "aarch64", target_arch = "arm64ec"),
7253            link_name = "llvm.aarch64.neon.fcvtns.i64.f64"
7254        )]
7255        fn _vcvtnd_s64_f64(a: f64) -> i64;
7256    }
7257    unsafe { _vcvtnd_s64_f64(a) }
7258}
7259#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)"]
7261#[inline]
7262#[target_feature(enable = "neon")]
7263#[cfg_attr(test, assert_instr(fcvtnu))]
7264#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7265pub fn vcvtns_u32_f32(a: f32) -> u32 {
7266    unsafe extern "unadjusted" {
7267        #[cfg_attr(
7268            any(target_arch = "aarch64", target_arch = "arm64ec"),
7269            link_name = "llvm.aarch64.neon.fcvtnu.i32.f32"
7270        )]
7271        fn _vcvtns_u32_f32(a: f32) -> u32;
7272    }
7273    unsafe { _vcvtns_u32_f32(a) }
7274}
7275#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
7276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64)"]
7277#[inline]
7278#[target_feature(enable = "neon")]
7279#[cfg_attr(test, assert_instr(fcvtnu))]
7280#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7281pub fn vcvtnd_u64_f64(a: f64) -> u64 {
7282    unsafe extern "unadjusted" {
7283        #[cfg_attr(
7284            any(target_arch = "aarch64", target_arch = "arm64ec"),
7285            link_name = "llvm.aarch64.neon.fcvtnu.i64.f64"
7286        )]
7287        fn _vcvtnd_u64_f64(a: f64) -> u64;
7288    }
7289    unsafe { _vcvtnd_u64_f64(a) }
7290}
7291#[doc = "Floating-point convert to signed integer, rounding to plus infinity"]
7292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s16_f16)"]
7293#[inline]
7294#[cfg_attr(test, assert_instr(fcvtps))]
7295#[target_feature(enable = "neon,fp16")]
7296#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
7297#[cfg(not(target_arch = "arm64ec"))]
7298pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t {
7299    unsafe extern "unadjusted" {
7300        #[cfg_attr(
7301            any(target_arch = "aarch64", target_arch = "arm64ec"),
7302            link_name = "llvm.aarch64.neon.fcvtps.v4i16.v4f16"
7303        )]
7304        fn _vcvtp_s16_f16(a: float16x4_t) -> int16x4_t;
7305    }
7306    unsafe { _vcvtp_s16_f16(a) }
7307}
7308#[doc = "Floating-point convert to signed integer, rounding to plus infinity"]
7309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s16_f16)"]
7310#[inline]
7311#[cfg_attr(test, assert_instr(fcvtps))]
7312#[target_feature(enable = "neon,fp16")]
7313#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
7314#[cfg(not(target_arch = "arm64ec"))]
7315pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t {
7316    unsafe extern "unadjusted" {
7317        #[cfg_attr(
7318            any(target_arch = "aarch64", target_arch = "arm64ec"),
7319            link_name = "llvm.aarch64.neon.fcvtps.v8i16.v8f16"
7320        )]
7321        fn _vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t;
7322    }
7323    unsafe { _vcvtpq_s16_f16(a) }
7324}
7325#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
7326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)"]
7327#[inline]
7328#[target_feature(enable = "neon")]
7329#[cfg_attr(test, assert_instr(fcvtps))]
7330#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7331pub fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t {
7332    unsafe extern "unadjusted" {
7333        #[cfg_attr(
7334            any(target_arch = "aarch64", target_arch = "arm64ec"),
7335            link_name = "llvm.aarch64.neon.fcvtps.v2i32.v2f32"
7336        )]
7337        fn _vcvtp_s32_f32(a: float32x2_t) -> int32x2_t;
7338    }
7339    unsafe { _vcvtp_s32_f32(a) }
7340}
7341#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
7342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)"]
7343#[inline]
7344#[target_feature(enable = "neon")]
7345#[cfg_attr(test, assert_instr(fcvtps))]
7346#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7347pub fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t {
7348    unsafe extern "unadjusted" {
7349        #[cfg_attr(
7350            any(target_arch = "aarch64", target_arch = "arm64ec"),
7351            link_name = "llvm.aarch64.neon.fcvtps.v4i32.v4f32"
7352        )]
7353        fn _vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t;
7354    }
7355    unsafe { _vcvtpq_s32_f32(a) }
7356}
7357#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
7358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)"]
7359#[inline]
7360#[target_feature(enable = "neon")]
7361#[cfg_attr(test, assert_instr(fcvtps))]
7362#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7363pub fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t {
7364    unsafe extern "unadjusted" {
7365        #[cfg_attr(
7366            any(target_arch = "aarch64", target_arch = "arm64ec"),
7367            link_name = "llvm.aarch64.neon.fcvtps.v1i64.v1f64"
7368        )]
7369        fn _vcvtp_s64_f64(a: float64x1_t) -> int64x1_t;
7370    }
7371    unsafe { _vcvtp_s64_f64(a) }
7372}
7373#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
7374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)"]
7375#[inline]
7376#[target_feature(enable = "neon")]
7377#[cfg_attr(test, assert_instr(fcvtps))]
7378#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7379pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t {
7380    unsafe extern "unadjusted" {
7381        #[cfg_attr(
7382            any(target_arch = "aarch64", target_arch = "arm64ec"),
7383            link_name = "llvm.aarch64.neon.fcvtps.v2i64.v2f64"
7384        )]
7385        fn _vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t;
7386    }
7387    unsafe { _vcvtpq_s64_f64(a) }
7388}
7389#[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
7390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u16_f16)"]
7391#[inline]
7392#[cfg_attr(test, assert_instr(fcvtpu))]
7393#[target_feature(enable = "neon,fp16")]
7394#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
7395#[cfg(not(target_arch = "arm64ec"))]
7396pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t {
7397    unsafe extern "unadjusted" {
7398        #[cfg_attr(
7399            any(target_arch = "aarch64", target_arch = "arm64ec"),
7400            link_name = "llvm.aarch64.neon.fcvtpu.v4i16.v4f16"
7401        )]
7402        fn _vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t;
7403    }
7404    unsafe { _vcvtp_u16_f16(a) }
7405}
7406#[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
7407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u16_f16)"]
7408#[inline]
7409#[cfg_attr(test, assert_instr(fcvtpu))]
7410#[target_feature(enable = "neon,fp16")]
7411#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
7412#[cfg(not(target_arch = "arm64ec"))]
7413pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t {
7414    unsafe extern "unadjusted" {
7415        #[cfg_attr(
7416            any(target_arch = "aarch64", target_arch = "arm64ec"),
7417            link_name = "llvm.aarch64.neon.fcvtpu.v8i16.v8f16"
7418        )]
7419        fn _vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t;
7420    }
7421    unsafe { _vcvtpq_u16_f16(a) }
7422}
7423#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
7424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)"]
7425#[inline]
7426#[target_feature(enable = "neon")]
7427#[cfg_attr(test, assert_instr(fcvtpu))]
7428#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7429pub fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t {
7430    unsafe extern "unadjusted" {
7431        #[cfg_attr(
7432            any(target_arch = "aarch64", target_arch = "arm64ec"),
7433            link_name = "llvm.aarch64.neon.fcvtpu.v2i32.v2f32"
7434        )]
7435        fn _vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t;
7436    }
7437    unsafe { _vcvtp_u32_f32(a) }
7438}
7439#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
7440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)"]
7441#[inline]
7442#[target_feature(enable = "neon")]
7443#[cfg_attr(test, assert_instr(fcvtpu))]
7444#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7445pub fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t {
7446    unsafe extern "unadjusted" {
7447        #[cfg_attr(
7448            any(target_arch = "aarch64", target_arch = "arm64ec"),
7449            link_name = "llvm.aarch64.neon.fcvtpu.v4i32.v4f32"
7450        )]
7451        fn _vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t;
7452    }
7453    unsafe { _vcvtpq_u32_f32(a) }
7454}
7455#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
7456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)"]
7457#[inline]
7458#[target_feature(enable = "neon")]
7459#[cfg_attr(test, assert_instr(fcvtpu))]
7460#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7461pub fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t {
7462    unsafe extern "unadjusted" {
7463        #[cfg_attr(
7464            any(target_arch = "aarch64", target_arch = "arm64ec"),
7465            link_name = "llvm.aarch64.neon.fcvtpu.v1i64.v1f64"
7466        )]
7467        fn _vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t;
7468    }
7469    unsafe { _vcvtp_u64_f64(a) }
7470}
7471#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
7472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)"]
7473#[inline]
7474#[target_feature(enable = "neon")]
7475#[cfg_attr(test, assert_instr(fcvtpu))]
7476#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7477pub fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t {
7478    unsafe extern "unadjusted" {
7479        #[cfg_attr(
7480            any(target_arch = "aarch64", target_arch = "arm64ec"),
7481            link_name = "llvm.aarch64.neon.fcvtpu.v2i64.v2f64"
7482        )]
7483        fn _vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t;
7484    }
7485    unsafe { _vcvtpq_u64_f64(a) }
7486}
7487#[doc = "Floating-point convert to integer, rounding to plus infinity"]
7488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s16_f16)"]
7489#[inline]
7490#[cfg_attr(test, assert_instr(fcvtps))]
7491#[target_feature(enable = "neon,fp16")]
7492#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7493#[cfg(not(target_arch = "arm64ec"))]
7494pub fn vcvtph_s16_f16(a: f16) -> i16 {
7495    unsafe extern "unadjusted" {
7496        #[cfg_attr(
7497            any(target_arch = "aarch64", target_arch = "arm64ec"),
7498            link_name = "llvm.aarch64.neon.fcvtps.i16.f16"
7499        )]
7500        fn _vcvtph_s16_f16(a: f16) -> i16;
7501    }
7502    unsafe { _vcvtph_s16_f16(a) }
7503}
7504#[doc = "Floating-point convert to integer, rounding to plus infinity"]
7505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s32_f16)"]
7506#[inline]
7507#[cfg_attr(test, assert_instr(fcvtps))]
7508#[target_feature(enable = "neon,fp16")]
7509#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7510#[cfg(not(target_arch = "arm64ec"))]
7511pub fn vcvtph_s32_f16(a: f16) -> i32 {
7512    unsafe extern "unadjusted" {
7513        #[cfg_attr(
7514            any(target_arch = "aarch64", target_arch = "arm64ec"),
7515            link_name = "llvm.aarch64.neon.fcvtps.i32.f16"
7516        )]
7517        fn _vcvtph_s32_f16(a: f16) -> i32;
7518    }
7519    unsafe { _vcvtph_s32_f16(a) }
7520}
7521#[doc = "Floating-point convert to integer, rounding to plus infinity"]
7522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s64_f16)"]
7523#[inline]
7524#[cfg_attr(test, assert_instr(fcvtps))]
7525#[target_feature(enable = "neon,fp16")]
7526#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7527#[cfg(not(target_arch = "arm64ec"))]
7528pub fn vcvtph_s64_f16(a: f16) -> i64 {
7529    unsafe extern "unadjusted" {
7530        #[cfg_attr(
7531            any(target_arch = "aarch64", target_arch = "arm64ec"),
7532            link_name = "llvm.aarch64.neon.fcvtps.i64.f16"
7533        )]
7534        fn _vcvtph_s64_f16(a: f16) -> i64;
7535    }
7536    unsafe { _vcvtph_s64_f16(a) }
7537}
7538#[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
7539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u16_f16)"]
7540#[inline]
7541#[cfg_attr(test, assert_instr(fcvtpu))]
7542#[target_feature(enable = "neon,fp16")]
7543#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7544#[cfg(not(target_arch = "arm64ec"))]
7545pub fn vcvtph_u16_f16(a: f16) -> u16 {
7546    unsafe extern "unadjusted" {
7547        #[cfg_attr(
7548            any(target_arch = "aarch64", target_arch = "arm64ec"),
7549            link_name = "llvm.aarch64.neon.fcvtpu.i16.f16"
7550        )]
7551        fn _vcvtph_u16_f16(a: f16) -> u16;
7552    }
7553    unsafe { _vcvtph_u16_f16(a) }
7554}
7555#[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
7556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u32_f16)"]
7557#[inline]
7558#[cfg_attr(test, assert_instr(fcvtpu))]
7559#[target_feature(enable = "neon,fp16")]
7560#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7561#[cfg(not(target_arch = "arm64ec"))]
7562pub fn vcvtph_u32_f16(a: f16) -> u32 {
7563    unsafe extern "unadjusted" {
7564        #[cfg_attr(
7565            any(target_arch = "aarch64", target_arch = "arm64ec"),
7566            link_name = "llvm.aarch64.neon.fcvtpu.i32.f16"
7567        )]
7568        fn _vcvtph_u32_f16(a: f16) -> u32;
7569    }
7570    unsafe { _vcvtph_u32_f16(a) }
7571}
7572#[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
7573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u64_f16)"]
7574#[inline]
7575#[cfg_attr(test, assert_instr(fcvtpu))]
7576#[target_feature(enable = "neon,fp16")]
7577#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7578#[cfg(not(target_arch = "arm64ec"))]
7579pub fn vcvtph_u64_f16(a: f16) -> u64 {
7580    unsafe extern "unadjusted" {
7581        #[cfg_attr(
7582            any(target_arch = "aarch64", target_arch = "arm64ec"),
7583            link_name = "llvm.aarch64.neon.fcvtpu.i64.f16"
7584        )]
7585        fn _vcvtph_u64_f16(a: f16) -> u64;
7586    }
7587    unsafe { _vcvtph_u64_f16(a) }
7588}
7589#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
7590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)"]
7591#[inline]
7592#[target_feature(enable = "neon")]
7593#[cfg_attr(test, assert_instr(fcvtps))]
7594#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7595pub fn vcvtps_s32_f32(a: f32) -> i32 {
7596    unsafe extern "unadjusted" {
7597        #[cfg_attr(
7598            any(target_arch = "aarch64", target_arch = "arm64ec"),
7599            link_name = "llvm.aarch64.neon.fcvtps.i32.f32"
7600        )]
7601        fn _vcvtps_s32_f32(a: f32) -> i32;
7602    }
7603    unsafe { _vcvtps_s32_f32(a) }
7604}
7605#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
7606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64)"]
7607#[inline]
7608#[target_feature(enable = "neon")]
7609#[cfg_attr(test, assert_instr(fcvtps))]
7610#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7611pub fn vcvtpd_s64_f64(a: f64) -> i64 {
7612    unsafe extern "unadjusted" {
7613        #[cfg_attr(
7614            any(target_arch = "aarch64", target_arch = "arm64ec"),
7615            link_name = "llvm.aarch64.neon.fcvtps.i64.f64"
7616        )]
7617        fn _vcvtpd_s64_f64(a: f64) -> i64;
7618    }
7619    unsafe { _vcvtpd_s64_f64(a) }
7620}
7621#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
7622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)"]
7623#[inline]
7624#[target_feature(enable = "neon")]
7625#[cfg_attr(test, assert_instr(fcvtpu))]
7626#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7627pub fn vcvtps_u32_f32(a: f32) -> u32 {
7628    unsafe extern "unadjusted" {
7629        #[cfg_attr(
7630            any(target_arch = "aarch64", target_arch = "arm64ec"),
7631            link_name = "llvm.aarch64.neon.fcvtpu.i32.f32"
7632        )]
7633        fn _vcvtps_u32_f32(a: f32) -> u32;
7634    }
7635    unsafe { _vcvtps_u32_f32(a) }
7636}
7637#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
7638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64)"]
7639#[inline]
7640#[target_feature(enable = "neon")]
7641#[cfg_attr(test, assert_instr(fcvtpu))]
7642#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7643pub fn vcvtpd_u64_f64(a: f64) -> u64 {
7644    unsafe extern "unadjusted" {
7645        #[cfg_attr(
7646            any(target_arch = "aarch64", target_arch = "arm64ec"),
7647            link_name = "llvm.aarch64.neon.fcvtpu.i64.f64"
7648        )]
7649        fn _vcvtpd_u64_f64(a: f64) -> u64;
7650    }
7651    unsafe { _vcvtpd_u64_f64(a) }
7652}
7653#[doc = "Fixed-point convert to floating-point"]
7654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)"]
7655#[inline]
7656#[target_feature(enable = "neon")]
7657#[cfg_attr(test, assert_instr(ucvtf))]
7658#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7659pub fn vcvts_f32_u32(a: u32) -> f32 {
7660    a as f32
7661}
7662#[doc = "Fixed-point convert to floating-point"]
7663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64)"]
7664#[inline]
7665#[target_feature(enable = "neon")]
7666#[cfg_attr(test, assert_instr(ucvtf))]
7667#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7668pub fn vcvtd_f64_u64(a: u64) -> f64 {
7669    a as f64
7670}
7671#[doc = "Fixed-point convert to floating-point"]
7672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32)"]
7673#[inline]
7674#[target_feature(enable = "neon")]
7675#[cfg_attr(test, assert_instr(scvtf, N = 2))]
7676#[rustc_legacy_const_generics(1)]
7677#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7678pub fn vcvts_n_f32_s32<const N: i32>(a: i32) -> f32 {
7679    static_assert!(N >= 1 && N <= 64);
7680    unsafe extern "unadjusted" {
7681        #[cfg_attr(
7682            any(target_arch = "aarch64", target_arch = "arm64ec"),
7683            link_name = "llvm.aarch64.neon.vcvtfxs2fp.f32.i32"
7684        )]
7685        fn _vcvts_n_f32_s32(a: i32, n: i32) -> f32;
7686    }
7687    unsafe { _vcvts_n_f32_s32(a, N) }
7688}
7689#[doc = "Fixed-point convert to floating-point"]
7690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64)"]
7691#[inline]
7692#[target_feature(enable = "neon")]
7693#[cfg_attr(test, assert_instr(scvtf, N = 2))]
7694#[rustc_legacy_const_generics(1)]
7695#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7696pub fn vcvtd_n_f64_s64<const N: i32>(a: i64) -> f64 {
7697    static_assert!(N >= 1 && N <= 64);
7698    unsafe extern "unadjusted" {
7699        #[cfg_attr(
7700            any(target_arch = "aarch64", target_arch = "arm64ec"),
7701            link_name = "llvm.aarch64.neon.vcvtfxs2fp.f64.i64"
7702        )]
7703        fn _vcvtd_n_f64_s64(a: i64, n: i32) -> f64;
7704    }
7705    unsafe { _vcvtd_n_f64_s64(a, N) }
7706}
7707#[doc = "Fixed-point convert to floating-point"]
7708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32)"]
7709#[inline]
7710#[target_feature(enable = "neon")]
7711#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
7712#[rustc_legacy_const_generics(1)]
7713#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7714pub fn vcvts_n_f32_u32<const N: i32>(a: u32) -> f32 {
7715    static_assert!(N >= 1 && N <= 32);
7716    unsafe extern "unadjusted" {
7717        #[cfg_attr(
7718            any(target_arch = "aarch64", target_arch = "arm64ec"),
7719            link_name = "llvm.aarch64.neon.vcvtfxu2fp.f32.i32"
7720        )]
7721        fn _vcvts_n_f32_u32(a: u32, n: i32) -> f32;
7722    }
7723    unsafe { _vcvts_n_f32_u32(a, N) }
7724}
7725#[doc = "Fixed-point convert to floating-point"]
7726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64)"]
7727#[inline]
7728#[target_feature(enable = "neon")]
7729#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
7730#[rustc_legacy_const_generics(1)]
7731#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7732pub fn vcvtd_n_f64_u64<const N: i32>(a: u64) -> f64 {
7733    static_assert!(N >= 1 && N <= 64);
7734    unsafe extern "unadjusted" {
7735        #[cfg_attr(
7736            any(target_arch = "aarch64", target_arch = "arm64ec"),
7737            link_name = "llvm.aarch64.neon.vcvtfxu2fp.f64.i64"
7738        )]
7739        fn _vcvtd_n_f64_u64(a: u64, n: i32) -> f64;
7740    }
7741    unsafe { _vcvtd_n_f64_u64(a, N) }
7742}
7743#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
7744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32)"]
7745#[inline]
7746#[target_feature(enable = "neon")]
7747#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
7748#[rustc_legacy_const_generics(1)]
7749#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7750pub fn vcvts_n_s32_f32<const N: i32>(a: f32) -> i32 {
7751    static_assert!(N >= 1 && N <= 32);
7752    unsafe extern "unadjusted" {
7753        #[cfg_attr(
7754            any(target_arch = "aarch64", target_arch = "arm64ec"),
7755            link_name = "llvm.aarch64.neon.vcvtfp2fxs.i32.f32"
7756        )]
7757        fn _vcvts_n_s32_f32(a: f32, n: i32) -> i32;
7758    }
7759    unsafe { _vcvts_n_s32_f32(a, N) }
7760}
7761#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
7762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64)"]
7763#[inline]
7764#[target_feature(enable = "neon")]
7765#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
7766#[rustc_legacy_const_generics(1)]
7767#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7768pub fn vcvtd_n_s64_f64<const N: i32>(a: f64) -> i64 {
7769    static_assert!(N >= 1 && N <= 64);
7770    unsafe extern "unadjusted" {
7771        #[cfg_attr(
7772            any(target_arch = "aarch64", target_arch = "arm64ec"),
7773            link_name = "llvm.aarch64.neon.vcvtfp2fxs.i64.f64"
7774        )]
7775        fn _vcvtd_n_s64_f64(a: f64, n: i32) -> i64;
7776    }
7777    unsafe { _vcvtd_n_s64_f64(a, N) }
7778}
7779#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
7780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32)"]
7781#[inline]
7782#[target_feature(enable = "neon")]
7783#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
7784#[rustc_legacy_const_generics(1)]
7785#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7786pub fn vcvts_n_u32_f32<const N: i32>(a: f32) -> u32 {
7787    static_assert!(N >= 1 && N <= 32);
7788    unsafe extern "unadjusted" {
7789        #[cfg_attr(
7790            any(target_arch = "aarch64", target_arch = "arm64ec"),
7791            link_name = "llvm.aarch64.neon.vcvtfp2fxu.i32.f32"
7792        )]
7793        fn _vcvts_n_u32_f32(a: f32, n: i32) -> u32;
7794    }
7795    unsafe { _vcvts_n_u32_f32(a, N) }
7796}
7797#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
7798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64)"]
7799#[inline]
7800#[target_feature(enable = "neon")]
7801#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
7802#[rustc_legacy_const_generics(1)]
7803#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7804pub fn vcvtd_n_u64_f64<const N: i32>(a: f64) -> u64 {
7805    static_assert!(N >= 1 && N <= 64);
7806    unsafe extern "unadjusted" {
7807        #[cfg_attr(
7808            any(target_arch = "aarch64", target_arch = "arm64ec"),
7809            link_name = "llvm.aarch64.neon.vcvtfp2fxu.i64.f64"
7810        )]
7811        fn _vcvtd_n_u64_f64(a: f64, n: i32) -> u64;
7812    }
7813    unsafe { _vcvtd_n_u64_f64(a, N) }
7814}
7815#[doc = "Fixed-point convert to floating-point"]
7816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)"]
7817#[inline]
7818#[target_feature(enable = "neon")]
7819#[cfg_attr(test, assert_instr(fcvtzs))]
7820#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7821pub fn vcvts_s32_f32(a: f32) -> i32 {
7822    a as i32
7823}
7824#[doc = "Fixed-point convert to floating-point"]
7825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64)"]
7826#[inline]
7827#[target_feature(enable = "neon")]
7828#[cfg_attr(test, assert_instr(fcvtzs))]
7829#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7830pub fn vcvtd_s64_f64(a: f64) -> i64 {
7831    a as i64
7832}
7833#[doc = "Fixed-point convert to floating-point"]
7834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)"]
7835#[inline]
7836#[target_feature(enable = "neon")]
7837#[cfg_attr(test, assert_instr(fcvtzu))]
7838#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7839pub fn vcvts_u32_f32(a: f32) -> u32 {
7840    a as u32
7841}
7842#[doc = "Fixed-point convert to floating-point"]
7843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64)"]
7844#[inline]
7845#[target_feature(enable = "neon")]
7846#[cfg_attr(test, assert_instr(fcvtzu))]
7847#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7848pub fn vcvtd_u64_f64(a: f64) -> u64 {
7849    a as u64
7850}
7851#[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
7852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"]
7853#[inline]
7854#[target_feature(enable = "neon")]
7855#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn))]
7856#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7857pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
7858    unsafe extern "unadjusted" {
7859        #[cfg_attr(
7860            any(target_arch = "aarch64", target_arch = "arm64ec"),
7861            link_name = "llvm.aarch64.neon.fcvtxn.v2f32.v2f64"
7862        )]
7863        fn _vcvtx_f32_f64(a: float64x2_t) -> float32x2_t;
7864    }
7865    unsafe { _vcvtx_f32_f64(a) }
7866}
7867#[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
7868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"]
7869#[inline]
7870#[target_feature(enable = "neon")]
7871#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn2))]
7872#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7873pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
7874    vcombine_f32(a, vcvtx_f32_f64(b))
7875}
7876#[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
7877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"]
7878#[inline]
7879#[target_feature(enable = "neon")]
7880#[cfg_attr(test, assert_instr(fcvtxn))]
7881#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7882pub fn vcvtxd_f32_f64(a: f64) -> f32 {
7883    vget_lane_f32::<0>(vcvtx_f32_f64(vdupq_n_f64(a)))
7884}
7885#[doc = "Divide"]
7886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"]
7887#[inline]
7888#[target_feature(enable = "neon,fp16")]
7889#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
7890#[cfg(not(target_arch = "arm64ec"))]
7891#[cfg_attr(test, assert_instr(fdiv))]
7892pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
7893    unsafe { simd_div(a, b) }
7894}
7895#[doc = "Divide"]
7896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"]
7897#[inline]
7898#[target_feature(enable = "neon,fp16")]
7899#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
7900#[cfg(not(target_arch = "arm64ec"))]
7901#[cfg_attr(test, assert_instr(fdiv))]
7902pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
7903    unsafe { simd_div(a, b) }
7904}
7905#[doc = "Divide"]
7906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)"]
7907#[inline]
7908#[target_feature(enable = "neon")]
7909#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7910#[cfg_attr(test, assert_instr(fdiv))]
7911pub fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
7912    unsafe { simd_div(a, b) }
7913}
7914#[doc = "Divide"]
7915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)"]
7916#[inline]
7917#[target_feature(enable = "neon")]
7918#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7919#[cfg_attr(test, assert_instr(fdiv))]
7920pub fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
7921    unsafe { simd_div(a, b) }
7922}
7923#[doc = "Divide"]
7924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)"]
7925#[inline]
7926#[target_feature(enable = "neon")]
7927#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7928#[cfg_attr(test, assert_instr(fdiv))]
7929pub fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
7930    unsafe { simd_div(a, b) }
7931}
7932#[doc = "Divide"]
7933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)"]
7934#[inline]
7935#[target_feature(enable = "neon")]
7936#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7937#[cfg_attr(test, assert_instr(fdiv))]
7938pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
7939    unsafe { simd_div(a, b) }
7940}
7941#[doc = "Divide"]
7942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivh_f16)"]
7943#[inline]
7944#[target_feature(enable = "neon,fp16")]
7945#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7946#[cfg(not(target_arch = "arm64ec"))]
7947#[cfg_attr(test, assert_instr(fdiv))]
7948pub fn vdivh_f16(a: f16, b: f16) -> f16 {
7949    a / b
7950}
7951#[doc = "Set all vector lanes to the same value"]
7952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"]
7953#[inline]
7954#[target_feature(enable = "neon")]
7955#[cfg_attr(test, assert_instr(nop, N = 0))]
7956#[rustc_legacy_const_generics(1)]
7957#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7958pub fn vdup_lane_f64<const N: i32>(a: float64x1_t) -> float64x1_t {
7959    static_assert!(N == 0);
7960    a
7961}
7962#[doc = "Set all vector lanes to the same value"]
7963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64)"]
7964#[inline]
7965#[target_feature(enable = "neon")]
7966#[cfg_attr(test, assert_instr(nop, N = 0))]
7967#[rustc_legacy_const_generics(1)]
7968#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7969pub fn vdup_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x1_t {
7970    static_assert!(N == 0);
7971    a
7972}
7973#[doc = "Set all vector lanes to the same value"]
7974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64)"]
7975#[inline]
7976#[target_feature(enable = "neon")]
7977#[cfg_attr(test, assert_instr(nop, N = 1))]
7978#[rustc_legacy_const_generics(1)]
7979#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7980pub fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t {
7981    static_assert_uimm_bits!(N, 1);
7982    unsafe { transmute(vgetq_lane_f64::<N>(a)) }
7983}
7984#[doc = "Set all vector lanes to the same value"]
7985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"]
7986#[inline]
7987#[target_feature(enable = "neon")]
7988#[cfg_attr(test, assert_instr(nop, N = 1))]
7989#[rustc_legacy_const_generics(1)]
7990#[stable(feature = "neon_intrinsics", since = "1.59.0")]
7991pub fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t {
7992    static_assert_uimm_bits!(N, 1);
7993    unsafe { transmute(vgetq_lane_p64::<N>(a)) }
7994}
7995#[doc = "Set all vector lanes to the same value"]
7996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"]
7997#[inline]
7998#[target_feature(enable = "neon")]
7999#[cfg_attr(test, assert_instr(nop, N = 4))]
8000#[rustc_legacy_const_generics(1)]
8001#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8002pub fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 {
8003    static_assert_uimm_bits!(N, 3);
8004    vget_lane_s8::<N>(a)
8005}
8006#[doc = "Set all vector lanes to the same value"]
8007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"]
8008#[inline]
8009#[target_feature(enable = "neon")]
8010#[cfg_attr(test, assert_instr(nop, N = 4))]
8011#[rustc_legacy_const_generics(1)]
8012#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8013pub fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 {
8014    static_assert_uimm_bits!(N, 3);
8015    vgetq_lane_s16::<N>(a)
8016}
8017#[doc = "Set all vector lanes to the same value"]
8018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"]
8019#[inline]
8020#[target_feature(enable = "neon")]
8021#[cfg_attr(test, assert_instr(nop, N = 4))]
8022#[rustc_legacy_const_generics(1)]
8023#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8024pub fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 {
8025    static_assert_uimm_bits!(N, 3);
8026    vget_lane_u8::<N>(a)
8027}
8028#[doc = "Set all vector lanes to the same value"]
8029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"]
8030#[inline]
8031#[target_feature(enable = "neon")]
8032#[cfg_attr(test, assert_instr(nop, N = 4))]
8033#[rustc_legacy_const_generics(1)]
8034#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8035pub fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 {
8036    static_assert_uimm_bits!(N, 3);
8037    vgetq_lane_u16::<N>(a)
8038}
8039#[doc = "Set all vector lanes to the same value"]
8040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"]
8041#[inline]
8042#[target_feature(enable = "neon")]
8043#[cfg_attr(test, assert_instr(nop, N = 4))]
8044#[rustc_legacy_const_generics(1)]
8045#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8046pub fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 {
8047    static_assert_uimm_bits!(N, 3);
8048    vget_lane_p8::<N>(a)
8049}
8050#[doc = "Set all vector lanes to the same value"]
8051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"]
8052#[inline]
8053#[target_feature(enable = "neon")]
8054#[cfg_attr(test, assert_instr(nop, N = 4))]
8055#[rustc_legacy_const_generics(1)]
8056#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8057pub fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 {
8058    static_assert_uimm_bits!(N, 3);
8059    vgetq_lane_p16::<N>(a)
8060}
8061#[doc = "Extract an element from a vector"]
8062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"]
8063#[inline]
8064#[target_feature(enable = "neon")]
8065#[cfg_attr(test, assert_instr(nop, N = 8))]
8066#[rustc_legacy_const_generics(1)]
8067#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8068pub fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 {
8069    static_assert_uimm_bits!(N, 4);
8070    vgetq_lane_s8::<N>(a)
8071}
8072#[doc = "Extract an element from a vector"]
8073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"]
8074#[inline]
8075#[target_feature(enable = "neon")]
8076#[cfg_attr(test, assert_instr(nop, N = 8))]
8077#[rustc_legacy_const_generics(1)]
8078#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8079pub fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 {
8080    static_assert_uimm_bits!(N, 4);
8081    vgetq_lane_u8::<N>(a)
8082}
8083#[doc = "Extract an element from a vector"]
8084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"]
8085#[inline]
8086#[target_feature(enable = "neon")]
8087#[cfg_attr(test, assert_instr(nop, N = 8))]
8088#[rustc_legacy_const_generics(1)]
8089#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8090pub fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 {
8091    static_assert_uimm_bits!(N, 4);
8092    vgetq_lane_p8::<N>(a)
8093}
8094#[doc = "Set all vector lanes to the same value"]
8095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"]
8096#[inline]
8097#[target_feature(enable = "neon")]
8098#[cfg_attr(test, assert_instr(nop, N = 0))]
8099#[rustc_legacy_const_generics(1)]
8100#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8101pub fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 {
8102    static_assert!(N == 0);
8103    vget_lane_f64::<N>(a)
8104}
8105#[doc = "Set all vector lanes to the same value"]
8106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"]
8107#[inline]
8108#[target_feature(enable = "neon")]
8109#[cfg_attr(test, assert_instr(nop, N = 0))]
8110#[rustc_legacy_const_generics(1)]
8111#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8112pub fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 {
8113    static_assert!(N == 0);
8114    vget_lane_s64::<N>(a)
8115}
8116#[doc = "Set all vector lanes to the same value"]
8117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"]
8118#[inline]
8119#[target_feature(enable = "neon")]
8120#[cfg_attr(test, assert_instr(nop, N = 0))]
8121#[rustc_legacy_const_generics(1)]
8122#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8123pub fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 {
8124    static_assert!(N == 0);
8125    vget_lane_u64::<N>(a)
8126}
8127#[doc = "Set all vector lanes to the same value"]
8128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_f16)"]
8129#[inline]
8130#[cfg_attr(test, assert_instr(nop, N = 2))]
8131#[rustc_legacy_const_generics(1)]
8132#[target_feature(enable = "neon,fp16")]
8133#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8134#[cfg(not(target_arch = "arm64ec"))]
8135pub fn vduph_lane_f16<const N: i32>(a: float16x4_t) -> f16 {
8136    static_assert_uimm_bits!(N, 2);
8137    vget_lane_f16::<N>(a)
8138}
8139#[doc = "Extract an element from a vector"]
8140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_f16)"]
8141#[inline]
8142#[cfg_attr(test, assert_instr(nop, N = 4))]
8143#[rustc_legacy_const_generics(1)]
8144#[target_feature(enable = "neon,fp16")]
8145#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8146#[cfg(not(target_arch = "arm64ec"))]
8147pub fn vduph_laneq_f16<const N: i32>(a: float16x8_t) -> f16 {
8148    static_assert_uimm_bits!(N, 4);
8149    vgetq_lane_f16::<N>(a)
8150}
8151#[doc = "Set all vector lanes to the same value"]
8152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"]
8153#[inline]
8154#[cfg(target_endian = "little")]
8155#[target_feature(enable = "neon")]
8156#[cfg_attr(test, assert_instr(dup, N = 0))]
8157#[rustc_legacy_const_generics(1)]
8158#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8159pub fn vdupq_lane_f64<const N: i32>(a: float64x1_t) -> float64x2_t {
8160    static_assert!(N == 0);
8161    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
8162}
8163#[doc = "Set all vector lanes to the same value"]
8164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"]
8165#[inline]
8166#[cfg(target_endian = "big")]
8167#[target_feature(enable = "neon")]
8168#[cfg_attr(test, assert_instr(dup, N = 0))]
8169#[rustc_legacy_const_generics(1)]
8170#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8171pub fn vdupq_lane_f64<const N: i32>(a: float64x1_t) -> float64x2_t {
8172    static_assert!(N == 0);
8173    unsafe {
8174        let ret_val: float64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]);
8175        simd_shuffle!(ret_val, ret_val, [1, 0])
8176    }
8177}
8178#[doc = "Set all vector lanes to the same value"]
8179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"]
8180#[inline]
8181#[cfg(target_endian = "little")]
8182#[target_feature(enable = "neon")]
8183#[cfg_attr(test, assert_instr(dup, N = 0))]
8184#[rustc_legacy_const_generics(1)]
8185#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8186pub fn vdupq_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x2_t {
8187    static_assert!(N == 0);
8188    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
8189}
8190#[doc = "Set all vector lanes to the same value"]
8191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"]
8192#[inline]
8193#[cfg(target_endian = "big")]
8194#[target_feature(enable = "neon")]
8195#[cfg_attr(test, assert_instr(dup, N = 0))]
8196#[rustc_legacy_const_generics(1)]
8197#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8198pub fn vdupq_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x2_t {
8199    static_assert!(N == 0);
8200    unsafe {
8201        let ret_val: poly64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]);
8202        simd_shuffle!(ret_val, ret_val, [1, 0])
8203    }
8204}
8205#[doc = "Set all vector lanes to the same value"]
8206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"]
8207#[inline]
8208#[cfg(target_endian = "little")]
8209#[target_feature(enable = "neon")]
8210#[cfg_attr(test, assert_instr(dup, N = 1))]
8211#[rustc_legacy_const_generics(1)]
8212#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8213pub fn vdupq_laneq_f64<const N: i32>(a: float64x2_t) -> float64x2_t {
8214    static_assert_uimm_bits!(N, 1);
8215    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
8216}
8217#[doc = "Set all vector lanes to the same value"]
8218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"]
8219#[inline]
8220#[cfg(target_endian = "big")]
8221#[target_feature(enable = "neon")]
8222#[cfg_attr(test, assert_instr(dup, N = 1))]
8223#[rustc_legacy_const_generics(1)]
8224#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8225pub fn vdupq_laneq_f64<const N: i32>(a: float64x2_t) -> float64x2_t {
8226    static_assert_uimm_bits!(N, 1);
8227    unsafe {
8228        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
8229        let ret_val: float64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]);
8230        simd_shuffle!(ret_val, ret_val, [1, 0])
8231    }
8232}
8233#[doc = "Set all vector lanes to the same value"]
8234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"]
8235#[inline]
8236#[cfg(target_endian = "little")]
8237#[target_feature(enable = "neon")]
8238#[cfg_attr(test, assert_instr(dup, N = 1))]
8239#[rustc_legacy_const_generics(1)]
8240#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8241pub fn vdupq_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x2_t {
8242    static_assert_uimm_bits!(N, 1);
8243    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
8244}
8245#[doc = "Set all vector lanes to the same value"]
8246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"]
8247#[inline]
8248#[cfg(target_endian = "big")]
8249#[target_feature(enable = "neon")]
8250#[cfg_attr(test, assert_instr(dup, N = 1))]
8251#[rustc_legacy_const_generics(1)]
8252#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8253pub fn vdupq_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x2_t {
8254    static_assert_uimm_bits!(N, 1);
8255    unsafe {
8256        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
8257        let ret_val: poly64x2_t = simd_shuffle!(a, a, [N as u32, N as u32]);
8258        simd_shuffle!(ret_val, ret_val, [1, 0])
8259    }
8260}
8261#[doc = "Set all vector lanes to the same value"]
8262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"]
8263#[inline]
8264#[target_feature(enable = "neon")]
8265#[cfg_attr(test, assert_instr(nop, N = 1))]
8266#[rustc_legacy_const_generics(1)]
8267#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8268pub fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 {
8269    static_assert_uimm_bits!(N, 1);
8270    vget_lane_f32::<N>(a)
8271}
8272#[doc = "Set all vector lanes to the same value"]
8273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"]
8274#[inline]
8275#[target_feature(enable = "neon")]
8276#[cfg_attr(test, assert_instr(nop, N = 1))]
8277#[rustc_legacy_const_generics(1)]
8278#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8279pub fn vdupd_laneq_f64<const N: i32>(a: float64x2_t) -> f64 {
8280    static_assert_uimm_bits!(N, 1);
8281    vgetq_lane_f64::<N>(a)
8282}
8283#[doc = "Set all vector lanes to the same value"]
8284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"]
8285#[inline]
8286#[target_feature(enable = "neon")]
8287#[cfg_attr(test, assert_instr(nop, N = 1))]
8288#[rustc_legacy_const_generics(1)]
8289#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8290pub fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 {
8291    static_assert_uimm_bits!(N, 1);
8292    vget_lane_s32::<N>(a)
8293}
8294#[doc = "Set all vector lanes to the same value"]
8295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"]
8296#[inline]
8297#[target_feature(enable = "neon")]
8298#[cfg_attr(test, assert_instr(nop, N = 1))]
8299#[rustc_legacy_const_generics(1)]
8300#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8301pub fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 {
8302    static_assert_uimm_bits!(N, 1);
8303    vgetq_lane_s64::<N>(a)
8304}
8305#[doc = "Set all vector lanes to the same value"]
8306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"]
8307#[inline]
8308#[target_feature(enable = "neon")]
8309#[cfg_attr(test, assert_instr(nop, N = 1))]
8310#[rustc_legacy_const_generics(1)]
8311#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8312pub fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 {
8313    static_assert_uimm_bits!(N, 1);
8314    vget_lane_u32::<N>(a)
8315}
8316#[doc = "Set all vector lanes to the same value"]
8317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"]
8318#[inline]
8319#[target_feature(enable = "neon")]
8320#[cfg_attr(test, assert_instr(nop, N = 1))]
8321#[rustc_legacy_const_generics(1)]
8322#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8323pub fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 {
8324    static_assert_uimm_bits!(N, 1);
8325    vgetq_lane_u64::<N>(a)
8326}
8327#[doc = "Set all vector lanes to the same value"]
8328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"]
8329#[inline]
8330#[target_feature(enable = "neon")]
8331#[cfg_attr(test, assert_instr(nop, N = 2))]
8332#[rustc_legacy_const_generics(1)]
8333#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8334pub fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 {
8335    static_assert_uimm_bits!(N, 2);
8336    vgetq_lane_f32::<N>(a)
8337}
8338#[doc = "Set all vector lanes to the same value"]
8339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"]
8340#[inline]
8341#[target_feature(enable = "neon")]
8342#[cfg_attr(test, assert_instr(nop, N = 2))]
8343#[rustc_legacy_const_generics(1)]
8344#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8345pub fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 {
8346    static_assert_uimm_bits!(N, 2);
8347    vget_lane_s16::<N>(a)
8348}
8349#[doc = "Set all vector lanes to the same value"]
8350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"]
8351#[inline]
8352#[target_feature(enable = "neon")]
8353#[cfg_attr(test, assert_instr(nop, N = 2))]
8354#[rustc_legacy_const_generics(1)]
8355#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8356pub fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 {
8357    static_assert_uimm_bits!(N, 2);
8358    vgetq_lane_s32::<N>(a)
8359}
8360#[doc = "Set all vector lanes to the same value"]
8361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"]
8362#[inline]
8363#[target_feature(enable = "neon")]
8364#[cfg_attr(test, assert_instr(nop, N = 2))]
8365#[rustc_legacy_const_generics(1)]
8366#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8367pub fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 {
8368    static_assert_uimm_bits!(N, 2);
8369    vget_lane_u16::<N>(a)
8370}
8371#[doc = "Set all vector lanes to the same value"]
8372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"]
8373#[inline]
8374#[target_feature(enable = "neon")]
8375#[cfg_attr(test, assert_instr(nop, N = 2))]
8376#[rustc_legacy_const_generics(1)]
8377#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8378pub fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 {
8379    static_assert_uimm_bits!(N, 2);
8380    vgetq_lane_u32::<N>(a)
8381}
8382#[doc = "Set all vector lanes to the same value"]
8383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"]
8384#[inline]
8385#[target_feature(enable = "neon")]
8386#[cfg_attr(test, assert_instr(nop, N = 2))]
8387#[rustc_legacy_const_generics(1)]
8388#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8389pub fn vduph_lane_p16<const N: i32>(a: poly16x4_t) -> p16 {
8390    static_assert_uimm_bits!(N, 2);
8391    vget_lane_p16::<N>(a)
8392}
8393#[doc = "Three-way exclusive OR"]
8394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"]
8395#[inline]
8396#[target_feature(enable = "neon,sha3")]
8397#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
8398#[cfg_attr(test, assert_instr(eor3))]
8399pub fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
8400    unsafe extern "unadjusted" {
8401        #[cfg_attr(
8402            any(target_arch = "aarch64", target_arch = "arm64ec"),
8403            link_name = "llvm.aarch64.crypto.eor3s.v16i8"
8404        )]
8405        fn _veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
8406    }
8407    unsafe { _veor3q_s8(a, b, c) }
8408}
8409#[doc = "Three-way exclusive OR"]
8410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16)"]
8411#[inline]
8412#[target_feature(enable = "neon,sha3")]
8413#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
8414#[cfg_attr(test, assert_instr(eor3))]
8415pub fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
8416    unsafe extern "unadjusted" {
8417        #[cfg_attr(
8418            any(target_arch = "aarch64", target_arch = "arm64ec"),
8419            link_name = "llvm.aarch64.crypto.eor3s.v8i16"
8420        )]
8421        fn _veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
8422    }
8423    unsafe { _veor3q_s16(a, b, c) }
8424}
8425#[doc = "Three-way exclusive OR"]
8426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32)"]
8427#[inline]
8428#[target_feature(enable = "neon,sha3")]
8429#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
8430#[cfg_attr(test, assert_instr(eor3))]
8431pub fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
8432    unsafe extern "unadjusted" {
8433        #[cfg_attr(
8434            any(target_arch = "aarch64", target_arch = "arm64ec"),
8435            link_name = "llvm.aarch64.crypto.eor3s.v4i32"
8436        )]
8437        fn _veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
8438    }
8439    unsafe { _veor3q_s32(a, b, c) }
8440}
8441#[doc = "Three-way exclusive OR"]
8442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64)"]
8443#[inline]
8444#[target_feature(enable = "neon,sha3")]
8445#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
8446#[cfg_attr(test, assert_instr(eor3))]
8447pub fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
8448    unsafe extern "unadjusted" {
8449        #[cfg_attr(
8450            any(target_arch = "aarch64", target_arch = "arm64ec"),
8451            link_name = "llvm.aarch64.crypto.eor3s.v2i64"
8452        )]
8453        fn _veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
8454    }
8455    unsafe { _veor3q_s64(a, b, c) }
8456}
8457#[doc = "Three-way exclusive OR"]
8458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8)"]
8459#[inline]
8460#[target_feature(enable = "neon,sha3")]
8461#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
8462#[cfg_attr(test, assert_instr(eor3))]
8463pub fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
8464    unsafe extern "unadjusted" {
8465        #[cfg_attr(
8466            any(target_arch = "aarch64", target_arch = "arm64ec"),
8467            link_name = "llvm.aarch64.crypto.eor3u.v16i8"
8468        )]
8469        fn _veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t;
8470    }
8471    unsafe { _veor3q_u8(a, b, c) }
8472}
8473#[doc = "Three-way exclusive OR"]
8474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16)"]
8475#[inline]
8476#[target_feature(enable = "neon,sha3")]
8477#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
8478#[cfg_attr(test, assert_instr(eor3))]
8479pub fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
8480    unsafe extern "unadjusted" {
8481        #[cfg_attr(
8482            any(target_arch = "aarch64", target_arch = "arm64ec"),
8483            link_name = "llvm.aarch64.crypto.eor3u.v8i16"
8484        )]
8485        fn _veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t;
8486    }
8487    unsafe { _veor3q_u16(a, b, c) }
8488}
8489#[doc = "Three-way exclusive OR"]
8490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32)"]
8491#[inline]
8492#[target_feature(enable = "neon,sha3")]
8493#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
8494#[cfg_attr(test, assert_instr(eor3))]
8495pub fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
8496    unsafe extern "unadjusted" {
8497        #[cfg_attr(
8498            any(target_arch = "aarch64", target_arch = "arm64ec"),
8499            link_name = "llvm.aarch64.crypto.eor3u.v4i32"
8500        )]
8501        fn _veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t;
8502    }
8503    unsafe { _veor3q_u32(a, b, c) }
8504}
8505#[doc = "Three-way exclusive OR"]
8506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64)"]
8507#[inline]
8508#[target_feature(enable = "neon,sha3")]
8509#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
8510#[cfg_attr(test, assert_instr(eor3))]
8511pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
8512    unsafe extern "unadjusted" {
8513        #[cfg_attr(
8514            any(target_arch = "aarch64", target_arch = "arm64ec"),
8515            link_name = "llvm.aarch64.crypto.eor3u.v2i64"
8516        )]
8517        fn _veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t;
8518    }
8519    unsafe { _veor3q_u64(a, b, c) }
8520}
8521#[doc = "Extract vector from pair of vectors"]
8522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"]
8523#[inline]
8524#[cfg(target_endian = "little")]
8525#[target_feature(enable = "neon")]
8526#[cfg_attr(test, assert_instr(ext, N = 1))]
8527#[rustc_legacy_const_generics(2)]
8528#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8529pub fn vextq_f64<const N: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
8530    static_assert_uimm_bits!(N, 1);
8531    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) }
8532}
8533#[doc = "Extract vector from pair of vectors"]
8534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"]
8535#[inline]
8536#[cfg(target_endian = "big")]
8537#[target_feature(enable = "neon")]
8538#[cfg_attr(test, assert_instr(ext, N = 1))]
8539#[rustc_legacy_const_generics(2)]
8540#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8541pub fn vextq_f64<const N: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
8542    static_assert_uimm_bits!(N, 1);
8543    unsafe {
8544        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
8545        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
8546        let ret_val: float64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]);
8547        simd_shuffle!(ret_val, ret_val, [1, 0])
8548    }
8549}
8550#[doc = "Extract vector from pair of vectors"]
8551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"]
8552#[inline]
8553#[cfg(target_endian = "little")]
8554#[target_feature(enable = "neon")]
8555#[cfg_attr(test, assert_instr(ext, N = 1))]
8556#[rustc_legacy_const_generics(2)]
8557#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8558pub fn vextq_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
8559    static_assert_uimm_bits!(N, 1);
8560    unsafe { simd_shuffle!(a, b, [N as u32, N as u32 + 1]) }
8561}
8562#[doc = "Extract vector from pair of vectors"]
8563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"]
8564#[inline]
8565#[cfg(target_endian = "big")]
8566#[target_feature(enable = "neon")]
8567#[cfg_attr(test, assert_instr(ext, N = 1))]
8568#[rustc_legacy_const_generics(2)]
8569#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8570pub fn vextq_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
8571    static_assert_uimm_bits!(N, 1);
8572    unsafe {
8573        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
8574        let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]);
8575        let ret_val: poly64x2_t = simd_shuffle!(a, b, [N as u32, N as u32 + 1]);
8576        simd_shuffle!(ret_val, ret_val, [1, 0])
8577    }
8578}
8579#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
8580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"]
8581#[inline]
8582#[target_feature(enable = "neon")]
8583#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8584#[cfg_attr(test, assert_instr(fmadd))]
8585pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
8586    unsafe { simd_fma(b, c, a) }
8587}
8588#[doc = "Floating-point fused multiply-add to accumulator"]
8589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f16)"]
8590#[inline]
8591#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8592#[rustc_legacy_const_generics(3)]
8593#[target_feature(enable = "neon,fp16")]
8594#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
8595#[cfg(not(target_arch = "arm64ec"))]
8596pub fn vfma_lane_f16<const LANE: i32>(
8597    a: float16x4_t,
8598    b: float16x4_t,
8599    c: float16x4_t,
8600) -> float16x4_t {
8601    static_assert_uimm_bits!(LANE, 2);
8602    vfma_f16(a, b, vdup_n_f16(vget_lane_f16::<LANE>(c)))
8603}
8604#[doc = "Floating-point fused multiply-add to accumulator"]
8605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f16)"]
8606#[inline]
8607#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8608#[rustc_legacy_const_generics(3)]
8609#[target_feature(enable = "neon,fp16")]
8610#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
8611#[cfg(not(target_arch = "arm64ec"))]
8612pub fn vfma_laneq_f16<const LANE: i32>(
8613    a: float16x4_t,
8614    b: float16x4_t,
8615    c: float16x8_t,
8616) -> float16x4_t {
8617    static_assert_uimm_bits!(LANE, 3);
8618    vfma_f16(a, b, vdup_n_f16(vgetq_lane_f16::<LANE>(c)))
8619}
8620#[doc = "Floating-point fused multiply-add to accumulator"]
8621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f16)"]
8622#[inline]
8623#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8624#[rustc_legacy_const_generics(3)]
8625#[target_feature(enable = "neon,fp16")]
8626#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
8627#[cfg(not(target_arch = "arm64ec"))]
8628pub fn vfmaq_lane_f16<const LANE: i32>(
8629    a: float16x8_t,
8630    b: float16x8_t,
8631    c: float16x4_t,
8632) -> float16x8_t {
8633    static_assert_uimm_bits!(LANE, 2);
8634    vfmaq_f16(a, b, vdupq_n_f16(vget_lane_f16::<LANE>(c)))
8635}
8636#[doc = "Floating-point fused multiply-add to accumulator"]
8637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f16)"]
8638#[inline]
8639#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8640#[rustc_legacy_const_generics(3)]
8641#[target_feature(enable = "neon,fp16")]
8642#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
8643#[cfg(not(target_arch = "arm64ec"))]
8644pub fn vfmaq_laneq_f16<const LANE: i32>(
8645    a: float16x8_t,
8646    b: float16x8_t,
8647    c: float16x8_t,
8648) -> float16x8_t {
8649    static_assert_uimm_bits!(LANE, 3);
8650    vfmaq_f16(a, b, vdupq_n_f16(vgetq_lane_f16::<LANE>(c)))
8651}
8652#[doc = "Floating-point fused multiply-add to accumulator"]
8653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"]
8654#[inline]
8655#[target_feature(enable = "neon")]
8656#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8657#[rustc_legacy_const_generics(3)]
8658#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8659pub fn vfma_lane_f32<const LANE: i32>(
8660    a: float32x2_t,
8661    b: float32x2_t,
8662    c: float32x2_t,
8663) -> float32x2_t {
8664    static_assert_uimm_bits!(LANE, 1);
8665    vfma_f32(a, b, vdup_n_f32(vget_lane_f32::<LANE>(c)))
8666}
8667#[doc = "Floating-point fused multiply-add to accumulator"]
8668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"]
8669#[inline]
8670#[target_feature(enable = "neon")]
8671#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8672#[rustc_legacy_const_generics(3)]
8673#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8674pub fn vfma_laneq_f32<const LANE: i32>(
8675    a: float32x2_t,
8676    b: float32x2_t,
8677    c: float32x4_t,
8678) -> float32x2_t {
8679    static_assert_uimm_bits!(LANE, 2);
8680    vfma_f32(a, b, vdup_n_f32(vgetq_lane_f32::<LANE>(c)))
8681}
8682#[doc = "Floating-point fused multiply-add to accumulator"]
8683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"]
8684#[inline]
8685#[target_feature(enable = "neon")]
8686#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8687#[rustc_legacy_const_generics(3)]
8688#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8689pub fn vfmaq_lane_f32<const LANE: i32>(
8690    a: float32x4_t,
8691    b: float32x4_t,
8692    c: float32x2_t,
8693) -> float32x4_t {
8694    static_assert_uimm_bits!(LANE, 1);
8695    vfmaq_f32(a, b, vdupq_n_f32(vget_lane_f32::<LANE>(c)))
8696}
8697#[doc = "Floating-point fused multiply-add to accumulator"]
8698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"]
8699#[inline]
8700#[target_feature(enable = "neon")]
8701#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8702#[rustc_legacy_const_generics(3)]
8703#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8704pub fn vfmaq_laneq_f32<const LANE: i32>(
8705    a: float32x4_t,
8706    b: float32x4_t,
8707    c: float32x4_t,
8708) -> float32x4_t {
8709    static_assert_uimm_bits!(LANE, 2);
8710    vfmaq_f32(a, b, vdupq_n_f32(vgetq_lane_f32::<LANE>(c)))
8711}
8712#[doc = "Floating-point fused multiply-add to accumulator"]
8713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"]
8714#[inline]
8715#[target_feature(enable = "neon")]
8716#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8717#[rustc_legacy_const_generics(3)]
8718#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8719pub fn vfmaq_laneq_f64<const LANE: i32>(
8720    a: float64x2_t,
8721    b: float64x2_t,
8722    c: float64x2_t,
8723) -> float64x2_t {
8724    static_assert_uimm_bits!(LANE, 1);
8725    vfmaq_f64(a, b, vdupq_n_f64(vgetq_lane_f64::<LANE>(c)))
8726}
8727#[doc = "Floating-point fused multiply-add to accumulator"]
8728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"]
8729#[inline]
8730#[target_feature(enable = "neon")]
8731#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
8732#[rustc_legacy_const_generics(3)]
8733#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8734pub fn vfma_lane_f64<const LANE: i32>(
8735    a: float64x1_t,
8736    b: float64x1_t,
8737    c: float64x1_t,
8738) -> float64x1_t {
8739    static_assert!(LANE == 0);
8740    vfma_f64(a, b, vdup_n_f64(vget_lane_f64::<LANE>(c)))
8741}
8742#[doc = "Floating-point fused multiply-add to accumulator"]
8743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"]
8744#[inline]
8745#[target_feature(enable = "neon")]
8746#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
8747#[rustc_legacy_const_generics(3)]
8748#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8749pub fn vfma_laneq_f64<const LANE: i32>(
8750    a: float64x1_t,
8751    b: float64x1_t,
8752    c: float64x2_t,
8753) -> float64x1_t {
8754    static_assert_uimm_bits!(LANE, 1);
8755    vfma_f64(a, b, vdup_n_f64(vgetq_lane_f64::<LANE>(c)))
8756}
8757#[doc = "Floating-point fused Multiply-Subtract from accumulator."]
8758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f16)"]
8759#[inline]
8760#[target_feature(enable = "neon,fp16")]
8761#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8762#[cfg(not(target_arch = "arm64ec"))]
8763#[cfg_attr(test, assert_instr(fmla))]
8764pub fn vfma_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t {
8765    vfma_f16(a, b, vdup_n_f16(c))
8766}
8767#[doc = "Floating-point fused Multiply-Subtract from accumulator."]
8768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f16)"]
8769#[inline]
8770#[target_feature(enable = "neon,fp16")]
8771#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8772#[cfg(not(target_arch = "arm64ec"))]
8773#[cfg_attr(test, assert_instr(fmla))]
8774pub fn vfmaq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t {
8775    vfmaq_f16(a, b, vdupq_n_f16(c))
8776}
8777#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
8778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64)"]
8779#[inline]
8780#[target_feature(enable = "neon")]
8781#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8782#[cfg_attr(test, assert_instr(fmadd))]
8783pub fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t {
8784    vfma_f64(a, b, vdup_n_f64(c))
8785}
8786#[doc = "Floating-point fused multiply-add to accumulator"]
8787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64)"]
8788#[inline]
8789#[target_feature(enable = "neon")]
8790#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
8791#[rustc_legacy_const_generics(3)]
8792#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8793pub fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
8794    static_assert!(LANE == 0);
8795    let c: f64 = vget_lane_f64::<LANE>(c);
8796    fmaf64(b, c, a)
8797}
8798#[doc = "Floating-point fused multiply-add to accumulator"]
8799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_f16)"]
8800#[inline]
8801#[cfg_attr(test, assert_instr(fmadd))]
8802#[target_feature(enable = "neon,fp16")]
8803#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8804#[cfg(not(target_arch = "arm64ec"))]
8805pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 {
8806    fmaf16(b, c, a)
8807}
8808#[doc = "Floating-point fused multiply-add to accumulator"]
8809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"]
8810#[inline]
8811#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
8812#[rustc_legacy_const_generics(3)]
8813#[target_feature(enable = "neon,fp16")]
8814#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8815#[cfg(not(target_arch = "arm64ec"))]
8816pub fn vfmah_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
8817    static_assert_uimm_bits!(LANE, 2);
8818    let c: f16 = vget_lane_f16::<LANE>(v);
8819    vfmah_f16(a, b, c)
8820}
8821#[doc = "Floating-point fused multiply-add to accumulator"]
8822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"]
8823#[inline]
8824#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
8825#[rustc_legacy_const_generics(3)]
8826#[target_feature(enable = "neon,fp16")]
8827#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8828#[cfg(not(target_arch = "arm64ec"))]
8829pub fn vfmah_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
8830    static_assert_uimm_bits!(LANE, 3);
8831    let c: f16 = vgetq_lane_f16::<LANE>(v);
8832    vfmah_f16(a, b, c)
8833}
8834#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
8835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"]
8836#[inline]
8837#[target_feature(enable = "neon")]
8838#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8839#[cfg_attr(test, assert_instr(fmla))]
8840pub fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
8841    unsafe { simd_fma(b, c, a) }
8842}
8843#[doc = "Floating-point fused multiply-add to accumulator"]
8844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64)"]
8845#[inline]
8846#[target_feature(enable = "neon")]
8847#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
8848#[rustc_legacy_const_generics(3)]
8849#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8850pub fn vfmaq_lane_f64<const LANE: i32>(
8851    a: float64x2_t,
8852    b: float64x2_t,
8853    c: float64x1_t,
8854) -> float64x2_t {
8855    static_assert!(LANE == 0);
8856    vfmaq_f64(a, b, vdupq_n_f64(vget_lane_f64::<LANE>(c)))
8857}
8858#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
8859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"]
8860#[inline]
8861#[target_feature(enable = "neon")]
8862#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8863#[cfg_attr(test, assert_instr(fmla))]
8864pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
8865    vfmaq_f64(a, b, vdupq_n_f64(c))
8866}
8867#[doc = "Floating-point fused multiply-add to accumulator"]
8868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"]
8869#[inline]
8870#[target_feature(enable = "neon")]
8871#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
8872#[rustc_legacy_const_generics(3)]
8873#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8874pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
8875    static_assert_uimm_bits!(LANE, 1);
8876    let c: f32 = vget_lane_f32::<LANE>(c);
8877    fmaf32(b, c, a)
8878}
8879#[doc = "Floating-point fused multiply-add to accumulator"]
8880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"]
8881#[inline]
8882#[target_feature(enable = "neon")]
8883#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
8884#[rustc_legacy_const_generics(3)]
8885#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8886pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
8887    static_assert_uimm_bits!(LANE, 2);
8888    let c: f32 = vgetq_lane_f32::<LANE>(c);
8889    fmaf32(b, c, a)
8890}
8891#[doc = "Floating-point fused multiply-add to accumulator"]
8892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"]
8893#[inline]
8894#[target_feature(enable = "neon")]
8895#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
8896#[rustc_legacy_const_generics(3)]
8897#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8898pub fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
8899    static_assert_uimm_bits!(LANE, 1);
8900    let c: f64 = vgetq_lane_f64::<LANE>(c);
8901    fmaf64(b, c, a)
8902}
8903#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
8904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"]
8905#[inline]
8906#[cfg(target_endian = "little")]
8907#[target_feature(enable = "neon,fp16")]
8908#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
8909#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
8910#[cfg(not(target_arch = "arm64ec"))]
8911#[cfg_attr(test, assert_instr(fmlal2))]
8912pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
8913    unsafe extern "unadjusted" {
8914        #[cfg_attr(
8915            any(target_arch = "aarch64", target_arch = "arm64ec"),
8916            link_name = "llvm.aarch64.neon.fmlal2.v2f32.v4f16"
8917        )]
8918        fn _vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t;
8919    }
8920    unsafe { _vfmlal_high_f16(r, a, b) }
8921}
8922#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
8923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"]
8924#[inline]
8925#[cfg(target_endian = "big")]
8926#[target_feature(enable = "neon,fp16")]
8927#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
8928#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
8929#[cfg(not(target_arch = "arm64ec"))]
8930#[cfg_attr(test, assert_instr(fmlal2))]
8931pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
8932    unsafe extern "unadjusted" {
8933        #[cfg_attr(
8934            any(target_arch = "aarch64", target_arch = "arm64ec"),
8935            link_name = "llvm.aarch64.neon.fmlal2.v2f32.v4f16"
8936        )]
8937        fn _vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t;
8938    }
8939    unsafe {
8940        let r: float32x2_t = simd_shuffle!(r, r, [1, 0]);
8941        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
8942        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
8943        let ret_val: float32x2_t = _vfmlal_high_f16(r, a, b);
8944        simd_shuffle!(ret_val, ret_val, [1, 0])
8945    }
8946}
8947#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
8948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"]
8949#[inline]
8950#[cfg(target_endian = "little")]
8951#[target_feature(enable = "neon,fp16")]
8952#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
8953#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
8954#[cfg(not(target_arch = "arm64ec"))]
8955#[cfg_attr(test, assert_instr(fmlal2))]
8956pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
8957    unsafe extern "unadjusted" {
8958        #[cfg_attr(
8959            any(target_arch = "aarch64", target_arch = "arm64ec"),
8960            link_name = "llvm.aarch64.neon.fmlal2.v4f32.v8f16"
8961        )]
8962        fn _vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t;
8963    }
8964    unsafe { _vfmlalq_high_f16(r, a, b) }
8965}
8966#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
8967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"]
8968#[inline]
8969#[cfg(target_endian = "big")]
8970#[target_feature(enable = "neon,fp16")]
8971#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
8972#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
8973#[cfg(not(target_arch = "arm64ec"))]
8974#[cfg_attr(test, assert_instr(fmlal2))]
8975pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
8976    unsafe extern "unadjusted" {
8977        #[cfg_attr(
8978            any(target_arch = "aarch64", target_arch = "arm64ec"),
8979            link_name = "llvm.aarch64.neon.fmlal2.v4f32.v8f16"
8980        )]
8981        fn _vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t;
8982    }
8983    unsafe {
8984        let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]);
8985        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
8986        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
8987        let ret_val: float32x4_t = _vfmlalq_high_f16(r, a, b);
8988        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8989    }
8990}
8991#[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
8992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_high_f16)"]
8993#[inline]
8994#[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
8995#[target_feature(enable = "neon,fp16")]
8996#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
8997#[rustc_legacy_const_generics(3)]
8998#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
8999#[cfg(not(target_arch = "arm64ec"))]
9000pub fn vfmlal_lane_high_f16<const LANE: i32>(
9001    r: float32x2_t,
9002    a: float16x4_t,
9003    b: float16x4_t,
9004) -> float32x2_t {
9005    static_assert_uimm_bits!(LANE, 2);
9006    vfmlal_high_f16(r, a, vdup_lane_f16::<LANE>(b))
9007}
9008#[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
9009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_high_f16)"]
9010#[inline]
9011#[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
9012#[target_feature(enable = "neon,fp16")]
9013#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9014#[rustc_legacy_const_generics(3)]
9015#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9016#[cfg(not(target_arch = "arm64ec"))]
9017pub fn vfmlal_laneq_high_f16<const LANE: i32>(
9018    r: float32x2_t,
9019    a: float16x4_t,
9020    b: float16x8_t,
9021) -> float32x2_t {
9022    static_assert_uimm_bits!(LANE, 3);
9023    vfmlal_high_f16(r, a, vdup_laneq_f16::<LANE>(b))
9024}
9025#[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
9026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_high_f16)"]
9027#[inline]
9028#[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
9029#[target_feature(enable = "neon,fp16")]
9030#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9031#[rustc_legacy_const_generics(3)]
9032#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9033#[cfg(not(target_arch = "arm64ec"))]
9034pub fn vfmlalq_lane_high_f16<const LANE: i32>(
9035    r: float32x4_t,
9036    a: float16x8_t,
9037    b: float16x4_t,
9038) -> float32x4_t {
9039    static_assert_uimm_bits!(LANE, 2);
9040    vfmlalq_high_f16(r, a, vdupq_lane_f16::<LANE>(b))
9041}
9042#[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
9043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_high_f16)"]
9044#[inline]
9045#[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
9046#[target_feature(enable = "neon,fp16")]
9047#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9048#[rustc_legacy_const_generics(3)]
9049#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9050#[cfg(not(target_arch = "arm64ec"))]
9051pub fn vfmlalq_laneq_high_f16<const LANE: i32>(
9052    r: float32x4_t,
9053    a: float16x8_t,
9054    b: float16x8_t,
9055) -> float32x4_t {
9056    static_assert_uimm_bits!(LANE, 3);
9057    vfmlalq_high_f16(r, a, vdupq_laneq_f16::<LANE>(b))
9058}
9059#[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
9060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_low_f16)"]
9061#[inline]
9062#[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
9063#[target_feature(enable = "neon,fp16")]
9064#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9065#[rustc_legacy_const_generics(3)]
9066#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9067#[cfg(not(target_arch = "arm64ec"))]
9068pub fn vfmlal_lane_low_f16<const LANE: i32>(
9069    r: float32x2_t,
9070    a: float16x4_t,
9071    b: float16x4_t,
9072) -> float32x2_t {
9073    static_assert_uimm_bits!(LANE, 2);
9074    vfmlal_low_f16(r, a, vdup_lane_f16::<LANE>(b))
9075}
9076#[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
9077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_low_f16)"]
9078#[inline]
9079#[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
9080#[target_feature(enable = "neon,fp16")]
9081#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9082#[rustc_legacy_const_generics(3)]
9083#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9084#[cfg(not(target_arch = "arm64ec"))]
9085pub fn vfmlal_laneq_low_f16<const LANE: i32>(
9086    r: float32x2_t,
9087    a: float16x4_t,
9088    b: float16x8_t,
9089) -> float32x2_t {
9090    static_assert_uimm_bits!(LANE, 3);
9091    vfmlal_low_f16(r, a, vdup_laneq_f16::<LANE>(b))
9092}
9093#[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
9094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_low_f16)"]
9095#[inline]
9096#[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
9097#[target_feature(enable = "neon,fp16")]
9098#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9099#[rustc_legacy_const_generics(3)]
9100#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9101#[cfg(not(target_arch = "arm64ec"))]
9102pub fn vfmlalq_lane_low_f16<const LANE: i32>(
9103    r: float32x4_t,
9104    a: float16x8_t,
9105    b: float16x4_t,
9106) -> float32x4_t {
9107    static_assert_uimm_bits!(LANE, 2);
9108    vfmlalq_low_f16(r, a, vdupq_lane_f16::<LANE>(b))
9109}
9110#[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
9111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_low_f16)"]
9112#[inline]
9113#[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
9114#[target_feature(enable = "neon,fp16")]
9115#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9116#[rustc_legacy_const_generics(3)]
9117#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9118#[cfg(not(target_arch = "arm64ec"))]
9119pub fn vfmlalq_laneq_low_f16<const LANE: i32>(
9120    r: float32x4_t,
9121    a: float16x8_t,
9122    b: float16x8_t,
9123) -> float32x4_t {
9124    static_assert_uimm_bits!(LANE, 3);
9125    vfmlalq_low_f16(r, a, vdupq_laneq_f16::<LANE>(b))
9126}
9127#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
9128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"]
9129#[inline]
9130#[cfg(target_endian = "little")]
9131#[target_feature(enable = "neon,fp16")]
9132#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9133#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9134#[cfg(not(target_arch = "arm64ec"))]
9135#[cfg_attr(test, assert_instr(fmlal))]
9136pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
9137    unsafe extern "unadjusted" {
9138        #[cfg_attr(
9139            any(target_arch = "aarch64", target_arch = "arm64ec"),
9140            link_name = "llvm.aarch64.neon.fmlal.v2f32.v4f16"
9141        )]
9142        fn _vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t;
9143    }
9144    unsafe { _vfmlal_low_f16(r, a, b) }
9145}
9146#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
9147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"]
9148#[inline]
9149#[cfg(target_endian = "big")]
9150#[target_feature(enable = "neon,fp16")]
9151#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9152#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9153#[cfg(not(target_arch = "arm64ec"))]
9154#[cfg_attr(test, assert_instr(fmlal))]
9155pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
9156    unsafe extern "unadjusted" {
9157        #[cfg_attr(
9158            any(target_arch = "aarch64", target_arch = "arm64ec"),
9159            link_name = "llvm.aarch64.neon.fmlal.v2f32.v4f16"
9160        )]
9161        fn _vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t;
9162    }
9163    unsafe {
9164        let r: float32x2_t = simd_shuffle!(r, r, [1, 0]);
9165        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
9166        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
9167        let ret_val: float32x2_t = _vfmlal_low_f16(r, a, b);
9168        simd_shuffle!(ret_val, ret_val, [1, 0])
9169    }
9170}
9171#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
9172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"]
9173#[inline]
9174#[cfg(target_endian = "little")]
9175#[target_feature(enable = "neon,fp16")]
9176#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9177#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9178#[cfg(not(target_arch = "arm64ec"))]
9179#[cfg_attr(test, assert_instr(fmlal))]
9180pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
9181    unsafe extern "unadjusted" {
9182        #[cfg_attr(
9183            any(target_arch = "aarch64", target_arch = "arm64ec"),
9184            link_name = "llvm.aarch64.neon.fmlal.v4f32.v8f16"
9185        )]
9186        fn _vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t;
9187    }
9188    unsafe { _vfmlalq_low_f16(r, a, b) }
9189}
9190#[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
9191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"]
9192#[inline]
9193#[cfg(target_endian = "big")]
9194#[target_feature(enable = "neon,fp16")]
9195#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9196#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9197#[cfg(not(target_arch = "arm64ec"))]
9198#[cfg_attr(test, assert_instr(fmlal))]
9199pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
9200    unsafe extern "unadjusted" {
9201        #[cfg_attr(
9202            any(target_arch = "aarch64", target_arch = "arm64ec"),
9203            link_name = "llvm.aarch64.neon.fmlal.v4f32.v8f16"
9204        )]
9205        fn _vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t;
9206    }
9207    unsafe {
9208        let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]);
9209        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
9210        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
9211        let ret_val: float32x4_t = _vfmlalq_low_f16(r, a, b);
9212        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
9213    }
9214}
9215#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
9216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"]
9217#[inline]
9218#[cfg(target_endian = "little")]
9219#[target_feature(enable = "neon,fp16")]
9220#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9221#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9222#[cfg(not(target_arch = "arm64ec"))]
9223#[cfg_attr(test, assert_instr(fmlsl2))]
9224pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
9225    unsafe extern "unadjusted" {
9226        #[cfg_attr(
9227            any(target_arch = "aarch64", target_arch = "arm64ec"),
9228            link_name = "llvm.aarch64.neon.fmlsl2.v2f32.v4f16"
9229        )]
9230        fn _vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t;
9231    }
9232    unsafe { _vfmlsl_high_f16(r, a, b) }
9233}
9234#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
9235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"]
9236#[inline]
9237#[cfg(target_endian = "big")]
9238#[target_feature(enable = "neon,fp16")]
9239#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9240#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9241#[cfg(not(target_arch = "arm64ec"))]
9242#[cfg_attr(test, assert_instr(fmlsl2))]
9243pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
9244    unsafe extern "unadjusted" {
9245        #[cfg_attr(
9246            any(target_arch = "aarch64", target_arch = "arm64ec"),
9247            link_name = "llvm.aarch64.neon.fmlsl2.v2f32.v4f16"
9248        )]
9249        fn _vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t;
9250    }
9251    unsafe {
9252        let r: float32x2_t = simd_shuffle!(r, r, [1, 0]);
9253        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
9254        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
9255        let ret_val: float32x2_t = _vfmlsl_high_f16(r, a, b);
9256        simd_shuffle!(ret_val, ret_val, [1, 0])
9257    }
9258}
9259#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
9260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"]
9261#[inline]
9262#[cfg(target_endian = "little")]
9263#[target_feature(enable = "neon,fp16")]
9264#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9265#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9266#[cfg(not(target_arch = "arm64ec"))]
9267#[cfg_attr(test, assert_instr(fmlsl2))]
9268pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
9269    unsafe extern "unadjusted" {
9270        #[cfg_attr(
9271            any(target_arch = "aarch64", target_arch = "arm64ec"),
9272            link_name = "llvm.aarch64.neon.fmlsl2.v4f32.v8f16"
9273        )]
9274        fn _vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t;
9275    }
9276    unsafe { _vfmlslq_high_f16(r, a, b) }
9277}
9278#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
9279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"]
9280#[inline]
9281#[cfg(target_endian = "big")]
9282#[target_feature(enable = "neon,fp16")]
9283#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9284#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9285#[cfg(not(target_arch = "arm64ec"))]
9286#[cfg_attr(test, assert_instr(fmlsl2))]
9287pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
9288    unsafe extern "unadjusted" {
9289        #[cfg_attr(
9290            any(target_arch = "aarch64", target_arch = "arm64ec"),
9291            link_name = "llvm.aarch64.neon.fmlsl2.v4f32.v8f16"
9292        )]
9293        fn _vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t;
9294    }
9295    unsafe {
9296        let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]);
9297        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
9298        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
9299        let ret_val: float32x4_t = _vfmlslq_high_f16(r, a, b);
9300        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
9301    }
9302}
9303#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
9304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_high_f16)"]
9305#[inline]
9306#[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
9307#[target_feature(enable = "neon,fp16")]
9308#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9309#[rustc_legacy_const_generics(3)]
9310#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9311#[cfg(not(target_arch = "arm64ec"))]
9312pub fn vfmlsl_lane_high_f16<const LANE: i32>(
9313    r: float32x2_t,
9314    a: float16x4_t,
9315    b: float16x4_t,
9316) -> float32x2_t {
9317    static_assert_uimm_bits!(LANE, 2);
9318    vfmlsl_high_f16(r, a, vdup_lane_f16::<LANE>(b))
9319}
9320#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
9321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_high_f16)"]
9322#[inline]
9323#[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
9324#[target_feature(enable = "neon,fp16")]
9325#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9326#[rustc_legacy_const_generics(3)]
9327#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9328#[cfg(not(target_arch = "arm64ec"))]
9329pub fn vfmlsl_laneq_high_f16<const LANE: i32>(
9330    r: float32x2_t,
9331    a: float16x4_t,
9332    b: float16x8_t,
9333) -> float32x2_t {
9334    static_assert_uimm_bits!(LANE, 3);
9335    vfmlsl_high_f16(r, a, vdup_laneq_f16::<LANE>(b))
9336}
9337#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
9338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_high_f16)"]
9339#[inline]
9340#[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
9341#[target_feature(enable = "neon,fp16")]
9342#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9343#[rustc_legacy_const_generics(3)]
9344#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9345#[cfg(not(target_arch = "arm64ec"))]
9346pub fn vfmlslq_lane_high_f16<const LANE: i32>(
9347    r: float32x4_t,
9348    a: float16x8_t,
9349    b: float16x4_t,
9350) -> float32x4_t {
9351    static_assert_uimm_bits!(LANE, 2);
9352    vfmlslq_high_f16(r, a, vdupq_lane_f16::<LANE>(b))
9353}
9354#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
9355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_high_f16)"]
9356#[inline]
9357#[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
9358#[target_feature(enable = "neon,fp16")]
9359#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9360#[rustc_legacy_const_generics(3)]
9361#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9362#[cfg(not(target_arch = "arm64ec"))]
9363pub fn vfmlslq_laneq_high_f16<const LANE: i32>(
9364    r: float32x4_t,
9365    a: float16x8_t,
9366    b: float16x8_t,
9367) -> float32x4_t {
9368    static_assert_uimm_bits!(LANE, 3);
9369    vfmlslq_high_f16(r, a, vdupq_laneq_f16::<LANE>(b))
9370}
9371#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
9372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_low_f16)"]
9373#[inline]
9374#[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
9375#[target_feature(enable = "neon,fp16")]
9376#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9377#[rustc_legacy_const_generics(3)]
9378#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9379#[cfg(not(target_arch = "arm64ec"))]
9380pub fn vfmlsl_lane_low_f16<const LANE: i32>(
9381    r: float32x2_t,
9382    a: float16x4_t,
9383    b: float16x4_t,
9384) -> float32x2_t {
9385    static_assert_uimm_bits!(LANE, 2);
9386    vfmlsl_low_f16(r, a, vdup_lane_f16::<LANE>(b))
9387}
9388#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
9389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_low_f16)"]
9390#[inline]
9391#[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
9392#[target_feature(enable = "neon,fp16")]
9393#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9394#[rustc_legacy_const_generics(3)]
9395#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9396#[cfg(not(target_arch = "arm64ec"))]
9397pub fn vfmlsl_laneq_low_f16<const LANE: i32>(
9398    r: float32x2_t,
9399    a: float16x4_t,
9400    b: float16x8_t,
9401) -> float32x2_t {
9402    static_assert_uimm_bits!(LANE, 3);
9403    vfmlsl_low_f16(r, a, vdup_laneq_f16::<LANE>(b))
9404}
9405#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
9406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_low_f16)"]
9407#[inline]
9408#[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
9409#[target_feature(enable = "neon,fp16")]
9410#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9411#[rustc_legacy_const_generics(3)]
9412#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9413#[cfg(not(target_arch = "arm64ec"))]
9414pub fn vfmlslq_lane_low_f16<const LANE: i32>(
9415    r: float32x4_t,
9416    a: float16x8_t,
9417    b: float16x4_t,
9418) -> float32x4_t {
9419    static_assert_uimm_bits!(LANE, 2);
9420    vfmlslq_low_f16(r, a, vdupq_lane_f16::<LANE>(b))
9421}
9422#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
9423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_low_f16)"]
9424#[inline]
9425#[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
9426#[target_feature(enable = "neon,fp16")]
9427#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9428#[rustc_legacy_const_generics(3)]
9429#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9430#[cfg(not(target_arch = "arm64ec"))]
9431pub fn vfmlslq_laneq_low_f16<const LANE: i32>(
9432    r: float32x4_t,
9433    a: float16x8_t,
9434    b: float16x8_t,
9435) -> float32x4_t {
9436    static_assert_uimm_bits!(LANE, 3);
9437    vfmlslq_low_f16(r, a, vdupq_laneq_f16::<LANE>(b))
9438}
9439#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
9440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"]
9441#[inline]
9442#[cfg(target_endian = "little")]
9443#[target_feature(enable = "neon,fp16")]
9444#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9445#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9446#[cfg(not(target_arch = "arm64ec"))]
9447#[cfg_attr(test, assert_instr(fmlsl))]
9448pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
9449    unsafe extern "unadjusted" {
9450        #[cfg_attr(
9451            any(target_arch = "aarch64", target_arch = "arm64ec"),
9452            link_name = "llvm.aarch64.neon.fmlsl.v2f32.v4f16"
9453        )]
9454        fn _vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t;
9455    }
9456    unsafe { _vfmlsl_low_f16(r, a, b) }
9457}
9458#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
9459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"]
9460#[inline]
9461#[cfg(target_endian = "big")]
9462#[target_feature(enable = "neon,fp16")]
9463#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9464#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9465#[cfg(not(target_arch = "arm64ec"))]
9466#[cfg_attr(test, assert_instr(fmlsl))]
9467pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t {
9468    unsafe extern "unadjusted" {
9469        #[cfg_attr(
9470            any(target_arch = "aarch64", target_arch = "arm64ec"),
9471            link_name = "llvm.aarch64.neon.fmlsl.v2f32.v4f16"
9472        )]
9473        fn _vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t;
9474    }
9475    unsafe {
9476        let r: float32x2_t = simd_shuffle!(r, r, [1, 0]);
9477        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
9478        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
9479        let ret_val: float32x2_t = _vfmlsl_low_f16(r, a, b);
9480        simd_shuffle!(ret_val, ret_val, [1, 0])
9481    }
9482}
9483#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
9484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"]
9485#[inline]
9486#[cfg(target_endian = "little")]
9487#[target_feature(enable = "neon,fp16")]
9488#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9489#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9490#[cfg(not(target_arch = "arm64ec"))]
9491#[cfg_attr(test, assert_instr(fmlsl))]
9492pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
9493    unsafe extern "unadjusted" {
9494        #[cfg_attr(
9495            any(target_arch = "aarch64", target_arch = "arm64ec"),
9496            link_name = "llvm.aarch64.neon.fmlsl.v4f32.v8f16"
9497        )]
9498        fn _vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t;
9499    }
9500    unsafe { _vfmlslq_low_f16(r, a, b) }
9501}
9502#[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
9503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"]
9504#[inline]
9505#[cfg(target_endian = "big")]
9506#[target_feature(enable = "neon,fp16")]
9507#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
9508#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9509#[cfg(not(target_arch = "arm64ec"))]
9510#[cfg_attr(test, assert_instr(fmlsl))]
9511pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t {
9512    unsafe extern "unadjusted" {
9513        #[cfg_attr(
9514            any(target_arch = "aarch64", target_arch = "arm64ec"),
9515            link_name = "llvm.aarch64.neon.fmlsl.v4f32.v8f16"
9516        )]
9517        fn _vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t;
9518    }
9519    unsafe {
9520        let r: float32x4_t = simd_shuffle!(r, r, [3, 2, 1, 0]);
9521        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
9522        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
9523        let ret_val: float32x4_t = _vfmlslq_low_f16(r, a, b);
9524        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
9525    }
9526}
9527#[doc = "Floating-point fused multiply-subtract from accumulator"]
9528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)"]
9529#[inline]
9530#[target_feature(enable = "neon")]
9531#[cfg_attr(test, assert_instr(fmsub))]
9532#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9533pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
9534    unsafe {
9535        let b: float64x1_t = simd_neg(b);
9536        vfma_f64(a, b, c)
9537    }
9538}
9539#[doc = "Floating-point fused multiply-subtract from accumulator"]
9540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f16)"]
9541#[inline]
9542#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9543#[rustc_legacy_const_generics(3)]
9544#[target_feature(enable = "neon,fp16")]
9545#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9546#[cfg(not(target_arch = "arm64ec"))]
9547pub fn vfms_lane_f16<const LANE: i32>(
9548    a: float16x4_t,
9549    b: float16x4_t,
9550    c: float16x4_t,
9551) -> float16x4_t {
9552    static_assert_uimm_bits!(LANE, 2);
9553    vfms_f16(a, b, vdup_n_f16(vget_lane_f16::<LANE>(c)))
9554}
9555#[doc = "Floating-point fused multiply-subtract from accumulator"]
9556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f16)"]
9557#[inline]
9558#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9559#[rustc_legacy_const_generics(3)]
9560#[target_feature(enable = "neon,fp16")]
9561#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9562#[cfg(not(target_arch = "arm64ec"))]
9563pub fn vfms_laneq_f16<const LANE: i32>(
9564    a: float16x4_t,
9565    b: float16x4_t,
9566    c: float16x8_t,
9567) -> float16x4_t {
9568    static_assert_uimm_bits!(LANE, 3);
9569    vfms_f16(a, b, vdup_n_f16(vgetq_lane_f16::<LANE>(c)))
9570}
9571#[doc = "Floating-point fused multiply-subtract from accumulator"]
9572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f16)"]
9573#[inline]
9574#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9575#[rustc_legacy_const_generics(3)]
9576#[target_feature(enable = "neon,fp16")]
9577#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9578#[cfg(not(target_arch = "arm64ec"))]
9579pub fn vfmsq_lane_f16<const LANE: i32>(
9580    a: float16x8_t,
9581    b: float16x8_t,
9582    c: float16x4_t,
9583) -> float16x8_t {
9584    static_assert_uimm_bits!(LANE, 2);
9585    vfmsq_f16(a, b, vdupq_n_f16(vget_lane_f16::<LANE>(c)))
9586}
9587#[doc = "Floating-point fused multiply-subtract from accumulator"]
9588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f16)"]
9589#[inline]
9590#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9591#[rustc_legacy_const_generics(3)]
9592#[target_feature(enable = "neon,fp16")]
9593#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
9594#[cfg(not(target_arch = "arm64ec"))]
9595pub fn vfmsq_laneq_f16<const LANE: i32>(
9596    a: float16x8_t,
9597    b: float16x8_t,
9598    c: float16x8_t,
9599) -> float16x8_t {
9600    static_assert_uimm_bits!(LANE, 3);
9601    vfmsq_f16(a, b, vdupq_n_f16(vgetq_lane_f16::<LANE>(c)))
9602}
9603#[doc = "Floating-point fused multiply-subtract to accumulator"]
9604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"]
9605#[inline]
9606#[target_feature(enable = "neon")]
9607#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9608#[rustc_legacy_const_generics(3)]
9609#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9610pub fn vfms_lane_f32<const LANE: i32>(
9611    a: float32x2_t,
9612    b: float32x2_t,
9613    c: float32x2_t,
9614) -> float32x2_t {
9615    static_assert_uimm_bits!(LANE, 1);
9616    vfms_f32(a, b, vdup_n_f32(vget_lane_f32::<LANE>(c)))
9617}
9618#[doc = "Floating-point fused multiply-subtract to accumulator"]
9619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"]
9620#[inline]
9621#[target_feature(enable = "neon")]
9622#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9623#[rustc_legacy_const_generics(3)]
9624#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9625pub fn vfms_laneq_f32<const LANE: i32>(
9626    a: float32x2_t,
9627    b: float32x2_t,
9628    c: float32x4_t,
9629) -> float32x2_t {
9630    static_assert_uimm_bits!(LANE, 2);
9631    vfms_f32(a, b, vdup_n_f32(vgetq_lane_f32::<LANE>(c)))
9632}
9633#[doc = "Floating-point fused multiply-subtract to accumulator"]
9634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"]
9635#[inline]
9636#[target_feature(enable = "neon")]
9637#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9638#[rustc_legacy_const_generics(3)]
9639#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9640pub fn vfmsq_lane_f32<const LANE: i32>(
9641    a: float32x4_t,
9642    b: float32x4_t,
9643    c: float32x2_t,
9644) -> float32x4_t {
9645    static_assert_uimm_bits!(LANE, 1);
9646    vfmsq_f32(a, b, vdupq_n_f32(vget_lane_f32::<LANE>(c)))
9647}
9648#[doc = "Floating-point fused multiply-subtract to accumulator"]
9649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"]
9650#[inline]
9651#[target_feature(enable = "neon")]
9652#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9653#[rustc_legacy_const_generics(3)]
9654#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9655pub fn vfmsq_laneq_f32<const LANE: i32>(
9656    a: float32x4_t,
9657    b: float32x4_t,
9658    c: float32x4_t,
9659) -> float32x4_t {
9660    static_assert_uimm_bits!(LANE, 2);
9661    vfmsq_f32(a, b, vdupq_n_f32(vgetq_lane_f32::<LANE>(c)))
9662}
9663#[doc = "Floating-point fused multiply-subtract to accumulator"]
9664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"]
9665#[inline]
9666#[target_feature(enable = "neon")]
9667#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9668#[rustc_legacy_const_generics(3)]
9669#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9670pub fn vfmsq_laneq_f64<const LANE: i32>(
9671    a: float64x2_t,
9672    b: float64x2_t,
9673    c: float64x2_t,
9674) -> float64x2_t {
9675    static_assert_uimm_bits!(LANE, 1);
9676    vfmsq_f64(a, b, vdupq_n_f64(vgetq_lane_f64::<LANE>(c)))
9677}
9678#[doc = "Floating-point fused multiply-subtract to accumulator"]
9679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"]
9680#[inline]
9681#[target_feature(enable = "neon")]
9682#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
9683#[rustc_legacy_const_generics(3)]
9684#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9685pub fn vfms_lane_f64<const LANE: i32>(
9686    a: float64x1_t,
9687    b: float64x1_t,
9688    c: float64x1_t,
9689) -> float64x1_t {
9690    static_assert!(LANE == 0);
9691    vfms_f64(a, b, vdup_n_f64(vget_lane_f64::<LANE>(c)))
9692}
9693#[doc = "Floating-point fused multiply-subtract to accumulator"]
9694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"]
9695#[inline]
9696#[target_feature(enable = "neon")]
9697#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
9698#[rustc_legacy_const_generics(3)]
9699#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9700pub fn vfms_laneq_f64<const LANE: i32>(
9701    a: float64x1_t,
9702    b: float64x1_t,
9703    c: float64x2_t,
9704) -> float64x1_t {
9705    static_assert_uimm_bits!(LANE, 1);
9706    vfms_f64(a, b, vdup_n_f64(vgetq_lane_f64::<LANE>(c)))
9707}
9708#[doc = "Floating-point fused Multiply-Subtract from accumulator."]
9709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f16)"]
9710#[inline]
9711#[target_feature(enable = "neon,fp16")]
9712#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9713#[cfg(not(target_arch = "arm64ec"))]
9714#[cfg_attr(test, assert_instr(fmls))]
9715pub fn vfms_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t {
9716    vfms_f16(a, b, vdup_n_f16(c))
9717}
9718#[doc = "Floating-point fused Multiply-Subtract from accumulator."]
9719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f16)"]
9720#[inline]
9721#[target_feature(enable = "neon,fp16")]
9722#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9723#[cfg(not(target_arch = "arm64ec"))]
9724#[cfg_attr(test, assert_instr(fmls))]
9725pub fn vfmsq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t {
9726    vfmsq_f16(a, b, vdupq_n_f16(c))
9727}
9728#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
9729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64)"]
9730#[inline]
9731#[target_feature(enable = "neon")]
9732#[cfg_attr(test, assert_instr(fmsub))]
9733#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9734pub fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t {
9735    vfms_f64(a, b, vdup_n_f64(c))
9736}
9737#[doc = "Floating-point fused multiply-subtract from accumulator"]
9738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_f16)"]
9739#[inline]
9740#[cfg_attr(test, assert_instr(fmsub))]
9741#[target_feature(enable = "neon,fp16")]
9742#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9743#[cfg(not(target_arch = "arm64ec"))]
9744pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 {
9745    vfmah_f16(a, -b, c)
9746}
9747#[doc = "Floating-point fused multiply-subtract from accumulator"]
9748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_lane_f16)"]
9749#[inline]
9750#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
9751#[rustc_legacy_const_generics(3)]
9752#[target_feature(enable = "neon,fp16")]
9753#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9754#[cfg(not(target_arch = "arm64ec"))]
9755pub fn vfmsh_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
9756    static_assert_uimm_bits!(LANE, 2);
9757    let c: f16 = vget_lane_f16::<LANE>(v);
9758    vfmsh_f16(a, b, c)
9759}
9760#[doc = "Floating-point fused multiply-subtract from accumulator"]
9761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"]
9762#[inline]
9763#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
9764#[rustc_legacy_const_generics(3)]
9765#[target_feature(enable = "neon,fp16")]
9766#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9767#[cfg(not(target_arch = "arm64ec"))]
9768pub fn vfmsh_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
9769    static_assert_uimm_bits!(LANE, 3);
9770    let c: f16 = vgetq_lane_f16::<LANE>(v);
9771    vfmsh_f16(a, b, c)
9772}
9773#[doc = "Floating-point fused multiply-subtract from accumulator"]
9774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"]
9775#[inline]
9776#[target_feature(enable = "neon")]
9777#[cfg_attr(test, assert_instr(fmls))]
9778#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9779pub fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
9780    unsafe {
9781        let b: float64x2_t = simd_neg(b);
9782        vfmaq_f64(a, b, c)
9783    }
9784}
9785#[doc = "Floating-point fused multiply-subtract to accumulator"]
9786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64)"]
9787#[inline]
9788#[target_feature(enable = "neon")]
9789#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9790#[rustc_legacy_const_generics(3)]
9791#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9792pub fn vfmsq_lane_f64<const LANE: i32>(
9793    a: float64x2_t,
9794    b: float64x2_t,
9795    c: float64x1_t,
9796) -> float64x2_t {
9797    static_assert!(LANE == 0);
9798    vfmsq_f64(a, b, vdupq_n_f64(vget_lane_f64::<LANE>(c)))
9799}
9800#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
9801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"]
9802#[inline]
9803#[target_feature(enable = "neon")]
9804#[cfg_attr(test, assert_instr(fmls))]
9805#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9806pub fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
9807    vfmsq_f64(a, b, vdupq_n_f64(c))
9808}
9809#[doc = "Floating-point fused multiply-subtract to accumulator"]
9810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"]
9811#[inline]
9812#[target_feature(enable = "neon")]
9813#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
9814#[rustc_legacy_const_generics(3)]
9815#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9816pub fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
9817    vfmas_lane_f32::<LANE>(a, -b, c)
9818}
9819#[doc = "Floating-point fused multiply-subtract to accumulator"]
9820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"]
9821#[inline]
9822#[target_feature(enable = "neon")]
9823#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
9824#[rustc_legacy_const_generics(3)]
9825#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9826pub fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
9827    vfmas_laneq_f32::<LANE>(a, -b, c)
9828}
9829#[doc = "Floating-point fused multiply-subtract to accumulator"]
9830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"]
9831#[inline]
9832#[target_feature(enable = "neon")]
9833#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
9834#[rustc_legacy_const_generics(3)]
9835#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9836pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
9837    vfmad_lane_f64::<LANE>(a, -b, c)
9838}
9839#[doc = "Floating-point fused multiply-subtract to accumulator"]
9840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"]
9841#[inline]
9842#[target_feature(enable = "neon")]
9843#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
9844#[rustc_legacy_const_generics(3)]
9845#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9846pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
9847    vfmad_laneq_f64::<LANE>(a, -b, c)
9848}
9849#[doc = "Duplicate vector element to vector or scalar"]
9850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f64)"]
9851#[inline]
9852#[cfg(target_endian = "little")]
9853#[target_feature(enable = "neon")]
9854#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9855#[cfg_attr(test, assert_instr(nop))]
9856pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
9857    unsafe { float64x1_t([simd_extract!(a, 1)]) }
9858}
9859#[doc = "Duplicate vector element to vector or scalar"]
9860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f64)"]
9861#[inline]
9862#[cfg(target_endian = "big")]
9863#[target_feature(enable = "neon")]
9864#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9865#[cfg_attr(test, assert_instr(nop))]
9866pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
9867    unsafe {
9868        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
9869        float64x1_t([simd_extract!(a, 1)])
9870    }
9871}
9872#[doc = "Duplicate vector element to vector or scalar"]
9873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f64)"]
9874#[inline]
9875#[cfg(target_endian = "little")]
9876#[target_feature(enable = "neon")]
9877#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9878#[cfg_attr(test, assert_instr(nop))]
9879pub fn vget_low_f64(a: float64x2_t) -> float64x1_t {
9880    unsafe { float64x1_t([simd_extract!(a, 0)]) }
9881}
9882#[doc = "Duplicate vector element to vector or scalar"]
9883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f64)"]
9884#[inline]
9885#[cfg(target_endian = "big")]
9886#[target_feature(enable = "neon")]
9887#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9888#[cfg_attr(test, assert_instr(nop))]
9889pub fn vget_low_f64(a: float64x2_t) -> float64x1_t {
9890    unsafe {
9891        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
9892        float64x1_t([simd_extract!(a, 0)])
9893    }
9894}
9895#[doc = "Duplicate vector element to vector or scalar"]
9896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)"]
9897#[inline]
9898#[cfg(target_endian = "little")]
9899#[target_feature(enable = "neon")]
9900#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9901#[rustc_legacy_const_generics(1)]
9902#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
9903pub fn vgetq_lane_f64<const IMM5: i32>(a: float64x2_t) -> f64 {
9904    static_assert_uimm_bits!(IMM5, 1);
9905    unsafe { simd_extract!(a, IMM5 as u32) }
9906}
9907#[doc = "Duplicate vector element to vector or scalar"]
9908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)"]
9909#[inline]
9910#[cfg(target_endian = "big")]
9911#[target_feature(enable = "neon")]
9912#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9913#[rustc_legacy_const_generics(1)]
9914#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
9915pub fn vgetq_lane_f64<const IMM5: i32>(a: float64x2_t) -> f64 {
9916    static_assert_uimm_bits!(IMM5, 1);
9917    unsafe {
9918        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
9919        simd_extract!(a, IMM5 as u32)
9920    }
9921}
9922#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
9923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
9924#[doc = "## Safety"]
9925#[doc = "  * Neon intrinsic unsafe"]
9926#[inline]
9927#[target_feature(enable = "neon,fp16")]
9928#[cfg_attr(test, assert_instr(ldr))]
9929#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9930#[cfg(not(target_arch = "arm64ec"))]
9931pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
9932    crate::ptr::read_unaligned(ptr.cast())
9933}
9934#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
9935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
9936#[doc = "## Safety"]
9937#[doc = "  * Neon intrinsic unsafe"]
9938#[inline]
9939#[target_feature(enable = "neon,fp16")]
9940#[cfg_attr(test, assert_instr(ldr))]
9941#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9942#[cfg(not(target_arch = "arm64ec"))]
9943pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
9944    crate::ptr::read_unaligned(ptr.cast())
9945}
9946#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
9947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
9948#[doc = "## Safety"]
9949#[doc = "  * Neon intrinsic unsafe"]
9950#[inline]
9951#[target_feature(enable = "neon")]
9952#[cfg_attr(test, assert_instr(ldr))]
9953#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9954pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
9955    crate::ptr::read_unaligned(ptr.cast())
9956}
9957#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
9958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
9959#[doc = "## Safety"]
9960#[doc = "  * Neon intrinsic unsafe"]
9961#[inline]
9962#[target_feature(enable = "neon")]
9963#[cfg_attr(test, assert_instr(ldr))]
9964#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9965pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
9966    crate::ptr::read_unaligned(ptr.cast())
9967}
9968#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
9969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"]
9970#[doc = "## Safety"]
9971#[doc = "  * Neon intrinsic unsafe"]
9972#[inline]
9973#[target_feature(enable = "neon")]
9974#[cfg_attr(test, assert_instr(ldr))]
9975#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9976pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t {
9977    crate::ptr::read_unaligned(ptr.cast())
9978}
9979#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
9980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"]
9981#[doc = "## Safety"]
9982#[doc = "  * Neon intrinsic unsafe"]
9983#[inline]
9984#[target_feature(enable = "neon")]
9985#[cfg_attr(test, assert_instr(ldr))]
9986#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9987pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t {
9988    crate::ptr::read_unaligned(ptr.cast())
9989}
9990#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
9991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
9992#[doc = "## Safety"]
9993#[doc = "  * Neon intrinsic unsafe"]
9994#[inline]
9995#[target_feature(enable = "neon")]
9996#[cfg_attr(test, assert_instr(ldr))]
9997#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9998pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
9999    crate::ptr::read_unaligned(ptr.cast())
10000}
10001#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
10003#[doc = "## Safety"]
10004#[doc = "  * Neon intrinsic unsafe"]
10005#[inline]
10006#[target_feature(enable = "neon")]
10007#[cfg_attr(test, assert_instr(ldr))]
10008#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10009pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
10010    crate::ptr::read_unaligned(ptr.cast())
10011}
10012#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
10014#[doc = "## Safety"]
10015#[doc = "  * Neon intrinsic unsafe"]
10016#[inline]
10017#[target_feature(enable = "neon")]
10018#[cfg_attr(test, assert_instr(ldr))]
10019#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10020pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
10021    crate::ptr::read_unaligned(ptr.cast())
10022}
10023#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
10025#[doc = "## Safety"]
10026#[doc = "  * Neon intrinsic unsafe"]
10027#[inline]
10028#[target_feature(enable = "neon")]
10029#[cfg_attr(test, assert_instr(ldr))]
10030#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10031pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
10032    crate::ptr::read_unaligned(ptr.cast())
10033}
10034#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
10036#[doc = "## Safety"]
10037#[doc = "  * Neon intrinsic unsafe"]
10038#[inline]
10039#[target_feature(enable = "neon")]
10040#[cfg_attr(test, assert_instr(ldr))]
10041#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10042pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
10043    crate::ptr::read_unaligned(ptr.cast())
10044}
10045#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
10047#[doc = "## Safety"]
10048#[doc = "  * Neon intrinsic unsafe"]
10049#[inline]
10050#[target_feature(enable = "neon")]
10051#[cfg_attr(test, assert_instr(ldr))]
10052#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10053pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
10054    crate::ptr::read_unaligned(ptr.cast())
10055}
10056#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
10058#[doc = "## Safety"]
10059#[doc = "  * Neon intrinsic unsafe"]
10060#[inline]
10061#[target_feature(enable = "neon")]
10062#[cfg_attr(test, assert_instr(ldr))]
10063#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10064pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
10065    crate::ptr::read_unaligned(ptr.cast())
10066}
10067#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
10069#[doc = "## Safety"]
10070#[doc = "  * Neon intrinsic unsafe"]
10071#[inline]
10072#[target_feature(enable = "neon")]
10073#[cfg_attr(test, assert_instr(ldr))]
10074#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10075pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
10076    crate::ptr::read_unaligned(ptr.cast())
10077}
10078#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
10080#[doc = "## Safety"]
10081#[doc = "  * Neon intrinsic unsafe"]
10082#[inline]
10083#[target_feature(enable = "neon")]
10084#[cfg_attr(test, assert_instr(ldr))]
10085#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10086pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
10087    crate::ptr::read_unaligned(ptr.cast())
10088}
10089#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
10091#[doc = "## Safety"]
10092#[doc = "  * Neon intrinsic unsafe"]
10093#[inline]
10094#[target_feature(enable = "neon")]
10095#[cfg_attr(test, assert_instr(ldr))]
10096#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10097pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
10098    crate::ptr::read_unaligned(ptr.cast())
10099}
10100#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
10102#[doc = "## Safety"]
10103#[doc = "  * Neon intrinsic unsafe"]
10104#[inline]
10105#[target_feature(enable = "neon")]
10106#[cfg_attr(test, assert_instr(ldr))]
10107#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10108pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
10109    crate::ptr::read_unaligned(ptr.cast())
10110}
10111#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
10113#[doc = "## Safety"]
10114#[doc = "  * Neon intrinsic unsafe"]
10115#[inline]
10116#[target_feature(enable = "neon")]
10117#[cfg_attr(test, assert_instr(ldr))]
10118#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10119pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
10120    crate::ptr::read_unaligned(ptr.cast())
10121}
10122#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
10124#[doc = "## Safety"]
10125#[doc = "  * Neon intrinsic unsafe"]
10126#[inline]
10127#[target_feature(enable = "neon")]
10128#[cfg_attr(test, assert_instr(ldr))]
10129#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10130pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
10131    crate::ptr::read_unaligned(ptr.cast())
10132}
10133#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
10135#[doc = "## Safety"]
10136#[doc = "  * Neon intrinsic unsafe"]
10137#[inline]
10138#[target_feature(enable = "neon")]
10139#[cfg_attr(test, assert_instr(ldr))]
10140#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10141pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
10142    crate::ptr::read_unaligned(ptr.cast())
10143}
10144#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
10146#[doc = "## Safety"]
10147#[doc = "  * Neon intrinsic unsafe"]
10148#[inline]
10149#[target_feature(enable = "neon")]
10150#[cfg_attr(test, assert_instr(ldr))]
10151#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10152pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
10153    crate::ptr::read_unaligned(ptr.cast())
10154}
10155#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
10157#[doc = "## Safety"]
10158#[doc = "  * Neon intrinsic unsafe"]
10159#[inline]
10160#[target_feature(enable = "neon")]
10161#[cfg_attr(test, assert_instr(ldr))]
10162#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10163pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
10164    crate::ptr::read_unaligned(ptr.cast())
10165}
10166#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
10168#[doc = "## Safety"]
10169#[doc = "  * Neon intrinsic unsafe"]
10170#[inline]
10171#[target_feature(enable = "neon")]
10172#[cfg_attr(test, assert_instr(ldr))]
10173#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10174pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
10175    crate::ptr::read_unaligned(ptr.cast())
10176}
10177#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
10179#[doc = "## Safety"]
10180#[doc = "  * Neon intrinsic unsafe"]
10181#[inline]
10182#[target_feature(enable = "neon")]
10183#[cfg_attr(test, assert_instr(ldr))]
10184#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10185pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
10186    crate::ptr::read_unaligned(ptr.cast())
10187}
10188#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
10190#[doc = "## Safety"]
10191#[doc = "  * Neon intrinsic unsafe"]
10192#[inline]
10193#[target_feature(enable = "neon")]
10194#[cfg_attr(test, assert_instr(ldr))]
10195#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10196pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
10197    crate::ptr::read_unaligned(ptr.cast())
10198}
10199#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
10201#[doc = "## Safety"]
10202#[doc = "  * Neon intrinsic unsafe"]
10203#[inline]
10204#[target_feature(enable = "neon")]
10205#[cfg_attr(test, assert_instr(ldr))]
10206#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10207pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
10208    crate::ptr::read_unaligned(ptr.cast())
10209}
10210#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
10212#[doc = "## Safety"]
10213#[doc = "  * Neon intrinsic unsafe"]
10214#[inline]
10215#[target_feature(enable = "neon,aes")]
10216#[cfg_attr(test, assert_instr(ldr))]
10217#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10218pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
10219    crate::ptr::read_unaligned(ptr.cast())
10220}
10221#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
10223#[doc = "## Safety"]
10224#[doc = "  * Neon intrinsic unsafe"]
10225#[inline]
10226#[target_feature(enable = "neon,aes")]
10227#[cfg_attr(test, assert_instr(ldr))]
10228#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10229pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
10230    crate::ptr::read_unaligned(ptr.cast())
10231}
10232#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"]
10234#[doc = "## Safety"]
10235#[doc = "  * Neon intrinsic unsafe"]
10236#[inline]
10237#[target_feature(enable = "neon")]
10238#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10239#[cfg_attr(test, assert_instr(ld))]
10240pub unsafe fn vld1_f64_x2(ptr: *const f64) -> float64x1x2_t {
10241    crate::ptr::read_unaligned(ptr.cast())
10242}
10243#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"]
10245#[doc = "## Safety"]
10246#[doc = "  * Neon intrinsic unsafe"]
10247#[inline]
10248#[target_feature(enable = "neon")]
10249#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10250#[cfg_attr(test, assert_instr(ld))]
10251pub unsafe fn vld1_f64_x3(ptr: *const f64) -> float64x1x3_t {
10252    crate::ptr::read_unaligned(ptr.cast())
10253}
10254#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"]
10256#[doc = "## Safety"]
10257#[doc = "  * Neon intrinsic unsafe"]
10258#[inline]
10259#[target_feature(enable = "neon")]
10260#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10261#[cfg_attr(test, assert_instr(ld))]
10262pub unsafe fn vld1_f64_x4(ptr: *const f64) -> float64x1x4_t {
10263    crate::ptr::read_unaligned(ptr.cast())
10264}
10265#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"]
10267#[doc = "## Safety"]
10268#[doc = "  * Neon intrinsic unsafe"]
10269#[inline]
10270#[target_feature(enable = "neon")]
10271#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10272#[cfg_attr(test, assert_instr(ld))]
10273pub unsafe fn vld1q_f64_x2(ptr: *const f64) -> float64x2x2_t {
10274    crate::ptr::read_unaligned(ptr.cast())
10275}
10276#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"]
10278#[doc = "## Safety"]
10279#[doc = "  * Neon intrinsic unsafe"]
10280#[inline]
10281#[target_feature(enable = "neon")]
10282#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10283#[cfg_attr(test, assert_instr(ld))]
10284pub unsafe fn vld1q_f64_x3(ptr: *const f64) -> float64x2x3_t {
10285    crate::ptr::read_unaligned(ptr.cast())
10286}
10287#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
10288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"]
10289#[doc = "## Safety"]
10290#[doc = "  * Neon intrinsic unsafe"]
10291#[inline]
10292#[target_feature(enable = "neon")]
10293#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10294#[cfg_attr(test, assert_instr(ld))]
10295pub unsafe fn vld1q_f64_x4(ptr: *const f64) -> float64x2x4_t {
10296    crate::ptr::read_unaligned(ptr.cast())
10297}
10298#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
10299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"]
10300#[doc = "## Safety"]
10301#[doc = "  * Neon intrinsic unsafe"]
10302#[inline]
10303#[target_feature(enable = "neon")]
10304#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10305#[cfg_attr(test, assert_instr(ld2r))]
10306pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t {
10307    unsafe extern "unadjusted" {
10308        #[cfg_attr(
10309            any(target_arch = "aarch64", target_arch = "arm64ec"),
10310            link_name = "llvm.aarch64.neon.ld2r.v1f64.p0"
10311        )]
10312        fn _vld2_dup_f64(ptr: *const f64) -> float64x1x2_t;
10313    }
10314    _vld2_dup_f64(a as _)
10315}
10316#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
10317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"]
10318#[doc = "## Safety"]
10319#[doc = "  * Neon intrinsic unsafe"]
10320#[inline]
10321#[target_feature(enable = "neon")]
10322#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10323#[cfg_attr(test, assert_instr(ld2r))]
10324pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t {
10325    unsafe extern "unadjusted" {
10326        #[cfg_attr(
10327            any(target_arch = "aarch64", target_arch = "arm64ec"),
10328            link_name = "llvm.aarch64.neon.ld2r.v2f64.p0"
10329        )]
10330        fn _vld2q_dup_f64(ptr: *const f64) -> float64x2x2_t;
10331    }
10332    _vld2q_dup_f64(a as _)
10333}
10334#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
10335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"]
10336#[doc = "## Safety"]
10337#[doc = "  * Neon intrinsic unsafe"]
10338#[inline]
10339#[target_feature(enable = "neon")]
10340#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10341#[cfg_attr(test, assert_instr(ld2r))]
10342pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t {
10343    unsafe extern "unadjusted" {
10344        #[cfg_attr(
10345            any(target_arch = "aarch64", target_arch = "arm64ec"),
10346            link_name = "llvm.aarch64.neon.ld2r.v2i64.p0"
10347        )]
10348        fn _vld2q_dup_s64(ptr: *const i64) -> int64x2x2_t;
10349    }
10350    _vld2q_dup_s64(a as _)
10351}
10352#[doc = "Load multiple 2-element structures to two registers"]
10353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"]
10354#[doc = "## Safety"]
10355#[doc = "  * Neon intrinsic unsafe"]
10356#[inline]
10357#[target_feature(enable = "neon")]
10358#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10359#[cfg_attr(test, assert_instr(nop))]
10360pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t {
10361    crate::ptr::read_unaligned(a.cast())
10362}
10363#[doc = "Load multiple 2-element structures to two registers"]
10364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"]
10365#[doc = "## Safety"]
10366#[doc = "  * Neon intrinsic unsafe"]
10367#[inline]
10368#[target_feature(enable = "neon")]
10369#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10370#[rustc_legacy_const_generics(2)]
10371#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10372pub unsafe fn vld2_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x2_t) -> float64x1x2_t {
10373    static_assert!(LANE == 0);
10374    unsafe extern "unadjusted" {
10375        #[cfg_attr(
10376            any(target_arch = "aarch64", target_arch = "arm64ec"),
10377            link_name = "llvm.aarch64.neon.ld2lane.v1f64.p0"
10378        )]
10379        fn _vld2_lane_f64(a: float64x1_t, b: float64x1_t, n: i64, ptr: *const i8) -> float64x1x2_t;
10380    }
10381    _vld2_lane_f64(b.0, b.1, LANE as i64, a as _)
10382}
10383#[doc = "Load multiple 2-element structures to two registers"]
10384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"]
10385#[doc = "## Safety"]
10386#[doc = "  * Neon intrinsic unsafe"]
10387#[inline]
10388#[target_feature(enable = "neon")]
10389#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10390#[rustc_legacy_const_generics(2)]
10391#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10392pub unsafe fn vld2_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x2_t) -> int64x1x2_t {
10393    static_assert!(LANE == 0);
10394    unsafe extern "unadjusted" {
10395        #[cfg_attr(
10396            any(target_arch = "aarch64", target_arch = "arm64ec"),
10397            link_name = "llvm.aarch64.neon.ld2lane.v1i64.p0"
10398        )]
10399        fn _vld2_lane_s64(a: int64x1_t, b: int64x1_t, n: i64, ptr: *const i8) -> int64x1x2_t;
10400    }
10401    _vld2_lane_s64(b.0, b.1, LANE as i64, a as _)
10402}
10403#[doc = "Load multiple 2-element structures to two registers"]
10404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"]
10405#[doc = "## Safety"]
10406#[doc = "  * Neon intrinsic unsafe"]
10407#[inline]
10408#[target_feature(enable = "neon,aes")]
10409#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10410#[rustc_legacy_const_generics(2)]
10411#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10412pub unsafe fn vld2_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x2_t) -> poly64x1x2_t {
10413    static_assert!(LANE == 0);
10414    transmute(vld2_lane_s64::<LANE>(transmute(a), transmute(b)))
10415}
10416#[doc = "Load multiple 2-element structures to two registers"]
10417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"]
10418#[doc = "## Safety"]
10419#[doc = "  * Neon intrinsic unsafe"]
10420#[inline]
10421#[target_feature(enable = "neon")]
10422#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10423#[rustc_legacy_const_generics(2)]
10424#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10425pub unsafe fn vld2_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x2_t) -> uint64x1x2_t {
10426    static_assert!(LANE == 0);
10427    transmute(vld2_lane_s64::<LANE>(transmute(a), transmute(b)))
10428}
10429#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
10430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
10431#[doc = "## Safety"]
10432#[doc = "  * Neon intrinsic unsafe"]
10433#[inline]
10434#[target_feature(enable = "neon,aes")]
10435#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10436#[cfg_attr(test, assert_instr(ld2r))]
10437pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
10438    transmute(vld2q_dup_s64(transmute(a)))
10439}
10440#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
10441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
10442#[doc = "## Safety"]
10443#[doc = "  * Neon intrinsic unsafe"]
10444#[inline]
10445#[target_feature(enable = "neon")]
10446#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10447#[cfg_attr(test, assert_instr(ld2r))]
10448pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
10449    transmute(vld2q_dup_s64(transmute(a)))
10450}
10451#[doc = "Load multiple 2-element structures to two registers"]
10452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"]
10453#[doc = "## Safety"]
10454#[doc = "  * Neon intrinsic unsafe"]
10455#[inline]
10456#[target_feature(enable = "neon")]
10457#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10458#[cfg_attr(test, assert_instr(ld2))]
10459pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t {
10460    unsafe extern "unadjusted" {
10461        #[cfg_attr(
10462            any(target_arch = "aarch64", target_arch = "arm64ec"),
10463            link_name = "llvm.aarch64.neon.ld2.v2f64.p0"
10464        )]
10465        fn _vld2q_f64(ptr: *const float64x2_t) -> float64x2x2_t;
10466    }
10467    _vld2q_f64(a as _)
10468}
10469#[doc = "Load multiple 2-element structures to two registers"]
10470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"]
10471#[doc = "## Safety"]
10472#[doc = "  * Neon intrinsic unsafe"]
10473#[inline]
10474#[target_feature(enable = "neon")]
10475#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10476#[cfg_attr(test, assert_instr(ld2))]
10477pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t {
10478    unsafe extern "unadjusted" {
10479        #[cfg_attr(
10480            any(target_arch = "aarch64", target_arch = "arm64ec"),
10481            link_name = "llvm.aarch64.neon.ld2.v2i64.p0"
10482        )]
10483        fn _vld2q_s64(ptr: *const int64x2_t) -> int64x2x2_t;
10484    }
10485    _vld2q_s64(a as _)
10486}
10487#[doc = "Load multiple 2-element structures to two registers"]
10488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"]
10489#[doc = "## Safety"]
10490#[doc = "  * Neon intrinsic unsafe"]
10491#[inline]
10492#[target_feature(enable = "neon")]
10493#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10494#[rustc_legacy_const_generics(2)]
10495#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10496pub unsafe fn vld2q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x2_t) -> float64x2x2_t {
10497    static_assert_uimm_bits!(LANE, 1);
10498    unsafe extern "unadjusted" {
10499        #[cfg_attr(
10500            any(target_arch = "aarch64", target_arch = "arm64ec"),
10501            link_name = "llvm.aarch64.neon.ld2lane.v2f64.p0"
10502        )]
10503        fn _vld2q_lane_f64(a: float64x2_t, b: float64x2_t, n: i64, ptr: *const i8)
10504            -> float64x2x2_t;
10505    }
10506    _vld2q_lane_f64(b.0, b.1, LANE as i64, a as _)
10507}
10508#[doc = "Load multiple 2-element structures to two registers"]
10509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"]
10510#[doc = "## Safety"]
10511#[doc = "  * Neon intrinsic unsafe"]
10512#[inline]
10513#[target_feature(enable = "neon")]
10514#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10515#[rustc_legacy_const_generics(2)]
10516#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10517pub unsafe fn vld2q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x2_t) -> int8x16x2_t {
10518    static_assert_uimm_bits!(LANE, 4);
10519    unsafe extern "unadjusted" {
10520        #[cfg_attr(
10521            any(target_arch = "aarch64", target_arch = "arm64ec"),
10522            link_name = "llvm.aarch64.neon.ld2lane.v16i8.p0"
10523        )]
10524        fn _vld2q_lane_s8(a: int8x16_t, b: int8x16_t, n: i64, ptr: *const i8) -> int8x16x2_t;
10525    }
10526    _vld2q_lane_s8(b.0, b.1, LANE as i64, a as _)
10527}
10528#[doc = "Load multiple 2-element structures to two registers"]
10529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"]
10530#[doc = "## Safety"]
10531#[doc = "  * Neon intrinsic unsafe"]
10532#[inline]
10533#[target_feature(enable = "neon")]
10534#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10535#[rustc_legacy_const_generics(2)]
10536#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10537pub unsafe fn vld2q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x2_t) -> int64x2x2_t {
10538    static_assert_uimm_bits!(LANE, 1);
10539    unsafe extern "unadjusted" {
10540        #[cfg_attr(
10541            any(target_arch = "aarch64", target_arch = "arm64ec"),
10542            link_name = "llvm.aarch64.neon.ld2lane.v2i64.p0"
10543        )]
10544        fn _vld2q_lane_s64(a: int64x2_t, b: int64x2_t, n: i64, ptr: *const i8) -> int64x2x2_t;
10545    }
10546    _vld2q_lane_s64(b.0, b.1, LANE as i64, a as _)
10547}
10548#[doc = "Load multiple 2-element structures to two registers"]
10549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"]
10550#[doc = "## Safety"]
10551#[doc = "  * Neon intrinsic unsafe"]
10552#[inline]
10553#[target_feature(enable = "neon,aes")]
10554#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10555#[rustc_legacy_const_generics(2)]
10556#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10557pub unsafe fn vld2q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x2_t) -> poly64x2x2_t {
10558    static_assert_uimm_bits!(LANE, 1);
10559    transmute(vld2q_lane_s64::<LANE>(transmute(a), transmute(b)))
10560}
10561#[doc = "Load multiple 2-element structures to two registers"]
10562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"]
10563#[doc = "## Safety"]
10564#[doc = "  * Neon intrinsic unsafe"]
10565#[inline]
10566#[target_feature(enable = "neon")]
10567#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10568#[rustc_legacy_const_generics(2)]
10569#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10570pub unsafe fn vld2q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x2_t) -> uint8x16x2_t {
10571    static_assert_uimm_bits!(LANE, 4);
10572    transmute(vld2q_lane_s8::<LANE>(transmute(a), transmute(b)))
10573}
10574#[doc = "Load multiple 2-element structures to two registers"]
10575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"]
10576#[doc = "## Safety"]
10577#[doc = "  * Neon intrinsic unsafe"]
10578#[inline]
10579#[target_feature(enable = "neon")]
10580#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10581#[rustc_legacy_const_generics(2)]
10582#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10583pub unsafe fn vld2q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x2_t) -> uint64x2x2_t {
10584    static_assert_uimm_bits!(LANE, 1);
10585    transmute(vld2q_lane_s64::<LANE>(transmute(a), transmute(b)))
10586}
10587#[doc = "Load multiple 2-element structures to two registers"]
10588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"]
10589#[doc = "## Safety"]
10590#[doc = "  * Neon intrinsic unsafe"]
10591#[inline]
10592#[target_feature(enable = "neon")]
10593#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
10594#[rustc_legacy_const_generics(2)]
10595#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10596pub unsafe fn vld2q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x2_t) -> poly8x16x2_t {
10597    static_assert_uimm_bits!(LANE, 4);
10598    transmute(vld2q_lane_s8::<LANE>(transmute(a), transmute(b)))
10599}
10600#[doc = "Load multiple 2-element structures to two registers"]
10601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
10602#[doc = "## Safety"]
10603#[doc = "  * Neon intrinsic unsafe"]
10604#[inline]
10605#[target_feature(enable = "neon,aes")]
10606#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10607#[cfg_attr(test, assert_instr(ld2))]
10608pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
10609    transmute(vld2q_s64(transmute(a)))
10610}
10611#[doc = "Load multiple 2-element structures to two registers"]
10612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
10613#[doc = "## Safety"]
10614#[doc = "  * Neon intrinsic unsafe"]
10615#[inline]
10616#[target_feature(enable = "neon")]
10617#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10618#[cfg_attr(test, assert_instr(ld2))]
10619pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
10620    transmute(vld2q_s64(transmute(a)))
10621}
10622#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
10623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"]
10624#[doc = "## Safety"]
10625#[doc = "  * Neon intrinsic unsafe"]
10626#[inline]
10627#[target_feature(enable = "neon")]
10628#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10629#[cfg_attr(test, assert_instr(ld3r))]
10630pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t {
10631    unsafe extern "unadjusted" {
10632        #[cfg_attr(
10633            any(target_arch = "aarch64", target_arch = "arm64ec"),
10634            link_name = "llvm.aarch64.neon.ld3r.v1f64.p0"
10635        )]
10636        fn _vld3_dup_f64(ptr: *const f64) -> float64x1x3_t;
10637    }
10638    _vld3_dup_f64(a as _)
10639}
10640#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
10641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"]
10642#[doc = "## Safety"]
10643#[doc = "  * Neon intrinsic unsafe"]
10644#[inline]
10645#[target_feature(enable = "neon")]
10646#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10647#[cfg_attr(test, assert_instr(ld3r))]
10648pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t {
10649    unsafe extern "unadjusted" {
10650        #[cfg_attr(
10651            any(target_arch = "aarch64", target_arch = "arm64ec"),
10652            link_name = "llvm.aarch64.neon.ld3r.v2f64.p0"
10653        )]
10654        fn _vld3q_dup_f64(ptr: *const f64) -> float64x2x3_t;
10655    }
10656    _vld3q_dup_f64(a as _)
10657}
10658#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
10659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"]
10660#[doc = "## Safety"]
10661#[doc = "  * Neon intrinsic unsafe"]
10662#[inline]
10663#[target_feature(enable = "neon")]
10664#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10665#[cfg_attr(test, assert_instr(ld3r))]
10666pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t {
10667    unsafe extern "unadjusted" {
10668        #[cfg_attr(
10669            any(target_arch = "aarch64", target_arch = "arm64ec"),
10670            link_name = "llvm.aarch64.neon.ld3r.v2i64.p0"
10671        )]
10672        fn _vld3q_dup_s64(ptr: *const i64) -> int64x2x3_t;
10673    }
10674    _vld3q_dup_s64(a as _)
10675}
10676#[doc = "Load multiple 3-element structures to three registers"]
10677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"]
10678#[doc = "## Safety"]
10679#[doc = "  * Neon intrinsic unsafe"]
10680#[inline]
10681#[target_feature(enable = "neon")]
10682#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10683#[cfg_attr(test, assert_instr(nop))]
10684pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t {
10685    crate::ptr::read_unaligned(a.cast())
10686}
10687#[doc = "Load multiple 3-element structures to three registers"]
10688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"]
10689#[doc = "## Safety"]
10690#[doc = "  * Neon intrinsic unsafe"]
10691#[inline]
10692#[target_feature(enable = "neon")]
10693#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10694#[rustc_legacy_const_generics(2)]
10695#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10696pub unsafe fn vld3_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x3_t) -> float64x1x3_t {
10697    static_assert!(LANE == 0);
10698    unsafe extern "unadjusted" {
10699        #[cfg_attr(
10700            any(target_arch = "aarch64", target_arch = "arm64ec"),
10701            link_name = "llvm.aarch64.neon.ld3lane.v1f64.p0"
10702        )]
10703        fn _vld3_lane_f64(
10704            a: float64x1_t,
10705            b: float64x1_t,
10706            c: float64x1_t,
10707            n: i64,
10708            ptr: *const i8,
10709        ) -> float64x1x3_t;
10710    }
10711    _vld3_lane_f64(b.0, b.1, b.2, LANE as i64, a as _)
10712}
10713#[doc = "Load multiple 3-element structures to three registers"]
10714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"]
10715#[doc = "## Safety"]
10716#[doc = "  * Neon intrinsic unsafe"]
10717#[inline]
10718#[target_feature(enable = "neon,aes")]
10719#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10720#[rustc_legacy_const_generics(2)]
10721#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10722pub unsafe fn vld3_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x3_t) -> poly64x1x3_t {
10723    static_assert!(LANE == 0);
10724    transmute(vld3_lane_s64::<LANE>(transmute(a), transmute(b)))
10725}
10726#[doc = "Load multiple 3-element structures to two registers"]
10727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"]
10728#[doc = "## Safety"]
10729#[doc = "  * Neon intrinsic unsafe"]
10730#[inline]
10731#[target_feature(enable = "neon")]
10732#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10733#[rustc_legacy_const_generics(2)]
10734#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10735pub unsafe fn vld3_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x3_t) -> int64x1x3_t {
10736    static_assert!(LANE == 0);
10737    unsafe extern "unadjusted" {
10738        #[cfg_attr(
10739            any(target_arch = "aarch64", target_arch = "arm64ec"),
10740            link_name = "llvm.aarch64.neon.ld3lane.v1i64.p0"
10741        )]
10742        fn _vld3_lane_s64(
10743            a: int64x1_t,
10744            b: int64x1_t,
10745            c: int64x1_t,
10746            n: i64,
10747            ptr: *const i8,
10748        ) -> int64x1x3_t;
10749    }
10750    _vld3_lane_s64(b.0, b.1, b.2, LANE as i64, a as _)
10751}
10752#[doc = "Load multiple 3-element structures to three registers"]
10753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"]
10754#[doc = "## Safety"]
10755#[doc = "  * Neon intrinsic unsafe"]
10756#[inline]
10757#[target_feature(enable = "neon")]
10758#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10759#[rustc_legacy_const_generics(2)]
10760#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10761pub unsafe fn vld3_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x3_t) -> uint64x1x3_t {
10762    static_assert!(LANE == 0);
10763    transmute(vld3_lane_s64::<LANE>(transmute(a), transmute(b)))
10764}
10765#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
10766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
10767#[doc = "## Safety"]
10768#[doc = "  * Neon intrinsic unsafe"]
10769#[inline]
10770#[target_feature(enable = "neon,aes")]
10771#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10772#[cfg_attr(test, assert_instr(ld3r))]
10773pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
10774    transmute(vld3q_dup_s64(transmute(a)))
10775}
10776#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
10777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
10778#[doc = "## Safety"]
10779#[doc = "  * Neon intrinsic unsafe"]
10780#[inline]
10781#[target_feature(enable = "neon")]
10782#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10783#[cfg_attr(test, assert_instr(ld3r))]
10784pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
10785    transmute(vld3q_dup_s64(transmute(a)))
10786}
10787#[doc = "Load multiple 3-element structures to three registers"]
10788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"]
10789#[doc = "## Safety"]
10790#[doc = "  * Neon intrinsic unsafe"]
10791#[inline]
10792#[target_feature(enable = "neon")]
10793#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10794#[cfg_attr(test, assert_instr(ld3))]
10795pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t {
10796    crate::core_arch::macros::deinterleaving_load!(f64, 2, 3, a)
10797}
10798#[doc = "Load multiple 3-element structures to three registers"]
10799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"]
10800#[doc = "## Safety"]
10801#[doc = "  * Neon intrinsic unsafe"]
10802#[inline]
10803#[target_feature(enable = "neon")]
10804#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10805#[cfg_attr(test, assert_instr(ld3))]
10806pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t {
10807    crate::core_arch::macros::deinterleaving_load!(i64, 2, 3, a)
10808}
10809#[doc = "Load multiple 3-element structures to three registers"]
10810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"]
10811#[doc = "## Safety"]
10812#[doc = "  * Neon intrinsic unsafe"]
10813#[inline]
10814#[target_feature(enable = "neon")]
10815#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10816#[rustc_legacy_const_generics(2)]
10817#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10818pub unsafe fn vld3q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x3_t) -> float64x2x3_t {
10819    static_assert_uimm_bits!(LANE, 1);
10820    unsafe extern "unadjusted" {
10821        #[cfg_attr(
10822            any(target_arch = "aarch64", target_arch = "arm64ec"),
10823            link_name = "llvm.aarch64.neon.ld3lane.v2f64.p0"
10824        )]
10825        fn _vld3q_lane_f64(
10826            a: float64x2_t,
10827            b: float64x2_t,
10828            c: float64x2_t,
10829            n: i64,
10830            ptr: *const i8,
10831        ) -> float64x2x3_t;
10832    }
10833    _vld3q_lane_f64(b.0, b.1, b.2, LANE as i64, a as _)
10834}
10835#[doc = "Load multiple 3-element structures to three registers"]
10836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"]
10837#[doc = "## Safety"]
10838#[doc = "  * Neon intrinsic unsafe"]
10839#[inline]
10840#[target_feature(enable = "neon,aes")]
10841#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10842#[rustc_legacy_const_generics(2)]
10843#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10844pub unsafe fn vld3q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x3_t) -> poly64x2x3_t {
10845    static_assert_uimm_bits!(LANE, 1);
10846    transmute(vld3q_lane_s64::<LANE>(transmute(a), transmute(b)))
10847}
10848#[doc = "Load multiple 3-element structures to two registers"]
10849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"]
10850#[doc = "## Safety"]
10851#[doc = "  * Neon intrinsic unsafe"]
10852#[inline]
10853#[target_feature(enable = "neon")]
10854#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10855#[rustc_legacy_const_generics(2)]
10856#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10857pub unsafe fn vld3q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x3_t) -> int8x16x3_t {
10858    static_assert_uimm_bits!(LANE, 4);
10859    unsafe extern "unadjusted" {
10860        #[cfg_attr(
10861            any(target_arch = "aarch64", target_arch = "arm64ec"),
10862            link_name = "llvm.aarch64.neon.ld3lane.v16i8.p0"
10863        )]
10864        fn _vld3q_lane_s8(
10865            a: int8x16_t,
10866            b: int8x16_t,
10867            c: int8x16_t,
10868            n: i64,
10869            ptr: *const i8,
10870        ) -> int8x16x3_t;
10871    }
10872    _vld3q_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
10873}
10874#[doc = "Load multiple 3-element structures to two registers"]
10875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"]
10876#[doc = "## Safety"]
10877#[doc = "  * Neon intrinsic unsafe"]
10878#[inline]
10879#[target_feature(enable = "neon")]
10880#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10881#[rustc_legacy_const_generics(2)]
10882#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10883pub unsafe fn vld3q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x3_t) -> int64x2x3_t {
10884    static_assert_uimm_bits!(LANE, 1);
10885    unsafe extern "unadjusted" {
10886        #[cfg_attr(
10887            any(target_arch = "aarch64", target_arch = "arm64ec"),
10888            link_name = "llvm.aarch64.neon.ld3lane.v2i64.p0"
10889        )]
10890        fn _vld3q_lane_s64(
10891            a: int64x2_t,
10892            b: int64x2_t,
10893            c: int64x2_t,
10894            n: i64,
10895            ptr: *const i8,
10896        ) -> int64x2x3_t;
10897    }
10898    _vld3q_lane_s64(b.0, b.1, b.2, LANE as i64, a as _)
10899}
10900#[doc = "Load multiple 3-element structures to three registers"]
10901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"]
10902#[doc = "## Safety"]
10903#[doc = "  * Neon intrinsic unsafe"]
10904#[inline]
10905#[target_feature(enable = "neon")]
10906#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10907#[rustc_legacy_const_generics(2)]
10908#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10909pub unsafe fn vld3q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x3_t) -> uint8x16x3_t {
10910    static_assert_uimm_bits!(LANE, 4);
10911    transmute(vld3q_lane_s8::<LANE>(transmute(a), transmute(b)))
10912}
10913#[doc = "Load multiple 3-element structures to three registers"]
10914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"]
10915#[doc = "## Safety"]
10916#[doc = "  * Neon intrinsic unsafe"]
10917#[inline]
10918#[target_feature(enable = "neon")]
10919#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10920#[rustc_legacy_const_generics(2)]
10921#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10922pub unsafe fn vld3q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x3_t) -> uint64x2x3_t {
10923    static_assert_uimm_bits!(LANE, 1);
10924    transmute(vld3q_lane_s64::<LANE>(transmute(a), transmute(b)))
10925}
10926#[doc = "Load multiple 3-element structures to three registers"]
10927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"]
10928#[doc = "## Safety"]
10929#[doc = "  * Neon intrinsic unsafe"]
10930#[inline]
10931#[target_feature(enable = "neon")]
10932#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
10933#[rustc_legacy_const_generics(2)]
10934#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10935pub unsafe fn vld3q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x3_t) -> poly8x16x3_t {
10936    static_assert_uimm_bits!(LANE, 4);
10937    transmute(vld3q_lane_s8::<LANE>(transmute(a), transmute(b)))
10938}
10939#[doc = "Load multiple 3-element structures to three registers"]
10940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
10941#[doc = "## Safety"]
10942#[doc = "  * Neon intrinsic unsafe"]
10943#[inline]
10944#[target_feature(enable = "neon,aes")]
10945#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10946#[cfg_attr(test, assert_instr(ld3))]
10947pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
10948    transmute(vld3q_s64(transmute(a)))
10949}
10950#[doc = "Load multiple 3-element structures to three registers"]
10951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
10952#[doc = "## Safety"]
10953#[doc = "  * Neon intrinsic unsafe"]
10954#[inline]
10955#[target_feature(enable = "neon")]
10956#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10957#[cfg_attr(test, assert_instr(ld3))]
10958pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
10959    transmute(vld3q_s64(transmute(a)))
10960}
10961#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
10962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"]
10963#[doc = "## Safety"]
10964#[doc = "  * Neon intrinsic unsafe"]
10965#[inline]
10966#[target_feature(enable = "neon")]
10967#[cfg_attr(test, assert_instr(ld4r))]
10968#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10969pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t {
10970    unsafe extern "unadjusted" {
10971        #[cfg_attr(
10972            any(target_arch = "aarch64", target_arch = "arm64ec"),
10973            link_name = "llvm.aarch64.neon.ld4r.v1f64.p0"
10974        )]
10975        fn _vld4_dup_f64(ptr: *const f64) -> float64x1x4_t;
10976    }
10977    _vld4_dup_f64(a as _)
10978}
10979#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
10980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"]
10981#[doc = "## Safety"]
10982#[doc = "  * Neon intrinsic unsafe"]
10983#[inline]
10984#[target_feature(enable = "neon")]
10985#[cfg_attr(test, assert_instr(ld4r))]
10986#[stable(feature = "neon_intrinsics", since = "1.59.0")]
10987pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t {
10988    unsafe extern "unadjusted" {
10989        #[cfg_attr(
10990            any(target_arch = "aarch64", target_arch = "arm64ec"),
10991            link_name = "llvm.aarch64.neon.ld4r.v2f64.p0"
10992        )]
10993        fn _vld4q_dup_f64(ptr: *const f64) -> float64x2x4_t;
10994    }
10995    _vld4q_dup_f64(a as _)
10996}
10997#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
10998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"]
10999#[doc = "## Safety"]
11000#[doc = "  * Neon intrinsic unsafe"]
11001#[inline]
11002#[target_feature(enable = "neon")]
11003#[cfg_attr(test, assert_instr(ld4r))]
11004#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11005pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t {
11006    unsafe extern "unadjusted" {
11007        #[cfg_attr(
11008            any(target_arch = "aarch64", target_arch = "arm64ec"),
11009            link_name = "llvm.aarch64.neon.ld4r.v2i64.p0"
11010        )]
11011        fn _vld4q_dup_s64(ptr: *const i64) -> int64x2x4_t;
11012    }
11013    _vld4q_dup_s64(a as _)
11014}
11015#[doc = "Load multiple 4-element structures to four registers"]
11016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"]
11017#[doc = "## Safety"]
11018#[doc = "  * Neon intrinsic unsafe"]
11019#[inline]
11020#[target_feature(enable = "neon")]
11021#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11022#[cfg_attr(test, assert_instr(nop))]
11023pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t {
11024    crate::ptr::read_unaligned(a.cast())
11025}
11026#[doc = "Load multiple 4-element structures to four registers"]
11027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"]
11028#[doc = "## Safety"]
11029#[doc = "  * Neon intrinsic unsafe"]
11030#[inline]
11031#[target_feature(enable = "neon")]
11032#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11033#[rustc_legacy_const_generics(2)]
11034#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11035pub unsafe fn vld4_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x4_t) -> float64x1x4_t {
11036    static_assert!(LANE == 0);
11037    unsafe extern "unadjusted" {
11038        #[cfg_attr(
11039            any(target_arch = "aarch64", target_arch = "arm64ec"),
11040            link_name = "llvm.aarch64.neon.ld4lane.v1f64.p0"
11041        )]
11042        fn _vld4_lane_f64(
11043            a: float64x1_t,
11044            b: float64x1_t,
11045            c: float64x1_t,
11046            d: float64x1_t,
11047            n: i64,
11048            ptr: *const i8,
11049        ) -> float64x1x4_t;
11050    }
11051    _vld4_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _)
11052}
11053#[doc = "Load multiple 4-element structures to four registers"]
11054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"]
11055#[doc = "## Safety"]
11056#[doc = "  * Neon intrinsic unsafe"]
11057#[inline]
11058#[target_feature(enable = "neon")]
11059#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11060#[rustc_legacy_const_generics(2)]
11061#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11062pub unsafe fn vld4_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x4_t) -> int64x1x4_t {
11063    static_assert!(LANE == 0);
11064    unsafe extern "unadjusted" {
11065        #[cfg_attr(
11066            any(target_arch = "aarch64", target_arch = "arm64ec"),
11067            link_name = "llvm.aarch64.neon.ld4lane.v1i64.p0"
11068        )]
11069        fn _vld4_lane_s64(
11070            a: int64x1_t,
11071            b: int64x1_t,
11072            c: int64x1_t,
11073            d: int64x1_t,
11074            n: i64,
11075            ptr: *const i8,
11076        ) -> int64x1x4_t;
11077    }
11078    _vld4_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _)
11079}
11080#[doc = "Load multiple 4-element structures to four registers"]
11081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"]
11082#[doc = "## Safety"]
11083#[doc = "  * Neon intrinsic unsafe"]
11084#[inline]
11085#[target_feature(enable = "neon,aes")]
11086#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11087#[rustc_legacy_const_generics(2)]
11088#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11089pub unsafe fn vld4_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x4_t) -> poly64x1x4_t {
11090    static_assert!(LANE == 0);
11091    transmute(vld4_lane_s64::<LANE>(transmute(a), transmute(b)))
11092}
11093#[doc = "Load multiple 4-element structures to four registers"]
11094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"]
11095#[doc = "## Safety"]
11096#[doc = "  * Neon intrinsic unsafe"]
11097#[inline]
11098#[target_feature(enable = "neon")]
11099#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11100#[rustc_legacy_const_generics(2)]
11101#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11102pub unsafe fn vld4_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x4_t) -> uint64x1x4_t {
11103    static_assert!(LANE == 0);
11104    transmute(vld4_lane_s64::<LANE>(transmute(a), transmute(b)))
11105}
11106#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
11107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
11108#[doc = "## Safety"]
11109#[doc = "  * Neon intrinsic unsafe"]
11110#[inline]
11111#[target_feature(enable = "neon,aes")]
11112#[cfg_attr(test, assert_instr(ld4r))]
11113#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11114pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
11115    transmute(vld4q_dup_s64(transmute(a)))
11116}
11117#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
11118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
11119#[doc = "## Safety"]
11120#[doc = "  * Neon intrinsic unsafe"]
11121#[inline]
11122#[target_feature(enable = "neon")]
11123#[cfg_attr(test, assert_instr(ld4r))]
11124#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11125pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
11126    transmute(vld4q_dup_s64(transmute(a)))
11127}
11128#[doc = "Load multiple 4-element structures to four registers"]
11129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"]
11130#[doc = "## Safety"]
11131#[doc = "  * Neon intrinsic unsafe"]
11132#[inline]
11133#[target_feature(enable = "neon")]
11134#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11135#[cfg_attr(test, assert_instr(ld4))]
11136pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t {
11137    crate::core_arch::macros::deinterleaving_load!(f64, 2, 4, a)
11138}
11139#[doc = "Load multiple 4-element structures to four registers"]
11140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"]
11141#[doc = "## Safety"]
11142#[doc = "  * Neon intrinsic unsafe"]
11143#[inline]
11144#[target_feature(enable = "neon")]
11145#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11146#[cfg_attr(test, assert_instr(ld4))]
11147pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t {
11148    crate::core_arch::macros::deinterleaving_load!(i64, 2, 4, a)
11149}
11150#[doc = "Load multiple 4-element structures to four registers"]
11151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"]
11152#[doc = "## Safety"]
11153#[doc = "  * Neon intrinsic unsafe"]
11154#[inline]
11155#[target_feature(enable = "neon")]
11156#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11157#[rustc_legacy_const_generics(2)]
11158#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11159pub unsafe fn vld4q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x4_t) -> float64x2x4_t {
11160    static_assert_uimm_bits!(LANE, 1);
11161    unsafe extern "unadjusted" {
11162        #[cfg_attr(
11163            any(target_arch = "aarch64", target_arch = "arm64ec"),
11164            link_name = "llvm.aarch64.neon.ld4lane.v2f64.p0"
11165        )]
11166        fn _vld4q_lane_f64(
11167            a: float64x2_t,
11168            b: float64x2_t,
11169            c: float64x2_t,
11170            d: float64x2_t,
11171            n: i64,
11172            ptr: *const i8,
11173        ) -> float64x2x4_t;
11174    }
11175    _vld4q_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _)
11176}
11177#[doc = "Load multiple 4-element structures to four registers"]
11178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"]
11179#[doc = "## Safety"]
11180#[doc = "  * Neon intrinsic unsafe"]
11181#[inline]
11182#[target_feature(enable = "neon")]
11183#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11184#[rustc_legacy_const_generics(2)]
11185#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11186pub unsafe fn vld4q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x4_t) -> int8x16x4_t {
11187    static_assert_uimm_bits!(LANE, 4);
11188    unsafe extern "unadjusted" {
11189        #[cfg_attr(
11190            any(target_arch = "aarch64", target_arch = "arm64ec"),
11191            link_name = "llvm.aarch64.neon.ld4lane.v16i8.p0"
11192        )]
11193        fn _vld4q_lane_s8(
11194            a: int8x16_t,
11195            b: int8x16_t,
11196            c: int8x16_t,
11197            d: int8x16_t,
11198            n: i64,
11199            ptr: *const i8,
11200        ) -> int8x16x4_t;
11201    }
11202    _vld4q_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
11203}
11204#[doc = "Load multiple 4-element structures to four registers"]
11205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"]
11206#[doc = "## Safety"]
11207#[doc = "  * Neon intrinsic unsafe"]
11208#[inline]
11209#[target_feature(enable = "neon")]
11210#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11211#[rustc_legacy_const_generics(2)]
11212#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11213pub unsafe fn vld4q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x4_t) -> int64x2x4_t {
11214    static_assert_uimm_bits!(LANE, 1);
11215    unsafe extern "unadjusted" {
11216        #[cfg_attr(
11217            any(target_arch = "aarch64", target_arch = "arm64ec"),
11218            link_name = "llvm.aarch64.neon.ld4lane.v2i64.p0"
11219        )]
11220        fn _vld4q_lane_s64(
11221            a: int64x2_t,
11222            b: int64x2_t,
11223            c: int64x2_t,
11224            d: int64x2_t,
11225            n: i64,
11226            ptr: *const i8,
11227        ) -> int64x2x4_t;
11228    }
11229    _vld4q_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _)
11230}
11231#[doc = "Load multiple 4-element structures to four registers"]
11232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"]
11233#[doc = "## Safety"]
11234#[doc = "  * Neon intrinsic unsafe"]
11235#[inline]
11236#[target_feature(enable = "neon,aes")]
11237#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11238#[rustc_legacy_const_generics(2)]
11239#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11240pub unsafe fn vld4q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x4_t) -> poly64x2x4_t {
11241    static_assert_uimm_bits!(LANE, 1);
11242    transmute(vld4q_lane_s64::<LANE>(transmute(a), transmute(b)))
11243}
11244#[doc = "Load multiple 4-element structures to four registers"]
11245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"]
11246#[doc = "## Safety"]
11247#[doc = "  * Neon intrinsic unsafe"]
11248#[inline]
11249#[target_feature(enable = "neon")]
11250#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11251#[rustc_legacy_const_generics(2)]
11252#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11253pub unsafe fn vld4q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x4_t) -> uint8x16x4_t {
11254    static_assert_uimm_bits!(LANE, 4);
11255    transmute(vld4q_lane_s8::<LANE>(transmute(a), transmute(b)))
11256}
11257#[doc = "Load multiple 4-element structures to four registers"]
11258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"]
11259#[doc = "## Safety"]
11260#[doc = "  * Neon intrinsic unsafe"]
11261#[inline]
11262#[target_feature(enable = "neon")]
11263#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11264#[rustc_legacy_const_generics(2)]
11265#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11266pub unsafe fn vld4q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x4_t) -> uint64x2x4_t {
11267    static_assert_uimm_bits!(LANE, 1);
11268    transmute(vld4q_lane_s64::<LANE>(transmute(a), transmute(b)))
11269}
11270#[doc = "Load multiple 4-element structures to four registers"]
11271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"]
11272#[doc = "## Safety"]
11273#[doc = "  * Neon intrinsic unsafe"]
11274#[inline]
11275#[target_feature(enable = "neon")]
11276#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
11277#[rustc_legacy_const_generics(2)]
11278#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11279pub unsafe fn vld4q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x4_t) -> poly8x16x4_t {
11280    static_assert_uimm_bits!(LANE, 4);
11281    transmute(vld4q_lane_s8::<LANE>(transmute(a), transmute(b)))
11282}
11283#[doc = "Load multiple 4-element structures to four registers"]
11284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
11285#[doc = "## Safety"]
11286#[doc = "  * Neon intrinsic unsafe"]
11287#[inline]
11288#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11289#[target_feature(enable = "neon,aes")]
11290#[cfg_attr(test, assert_instr(ld4))]
11291pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
11292    transmute(vld4q_s64(transmute(a)))
11293}
11294#[doc = "Load multiple 4-element structures to four registers"]
11295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
11296#[doc = "## Safety"]
11297#[doc = "  * Neon intrinsic unsafe"]
11298#[inline]
11299#[target_feature(enable = "neon")]
11300#[stable(feature = "neon_intrinsics", since = "1.59.0")]
11301#[cfg_attr(test, assert_instr(ld4))]
11302pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
11303    transmute(vld4q_s64(transmute(a)))
11304}
11305#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
11306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"]
11307#[doc = "## Safety"]
11308#[doc = "  * Neon intrinsic unsafe"]
11309#[inline]
11310#[target_feature(enable = "neon,rcpc3")]
11311#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
11312#[rustc_legacy_const_generics(2)]
11313#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
11314#[cfg(target_has_atomic = "64")]
11315pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
11316    static_assert!(LANE == 0);
11317    let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64);
11318    simd_insert!(
11319        src,
11320        LANE as u32,
11321        atomic_src.load(crate::sync::atomic::Ordering::Acquire)
11322    )
11323}
11324#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
11325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"]
11326#[doc = "## Safety"]
11327#[doc = "  * Neon intrinsic unsafe"]
11328#[inline]
11329#[target_feature(enable = "neon,rcpc3")]
11330#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
11331#[rustc_legacy_const_generics(2)]
11332#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
11333#[cfg(target_has_atomic = "64")]
11334pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
11335    static_assert_uimm_bits!(LANE, 1);
11336    let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64);
11337    simd_insert!(
11338        src,
11339        LANE as u32,
11340        atomic_src.load(crate::sync::atomic::Ordering::Acquire)
11341    )
11342}
11343#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
11344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"]
11345#[doc = "## Safety"]
11346#[doc = "  * Neon intrinsic unsafe"]
11347#[inline]
11348#[rustc_legacy_const_generics(2)]
11349#[target_feature(enable = "neon,rcpc3")]
11350#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
11351#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
11352#[cfg(target_has_atomic = "64")]
11353pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_t) -> float64x2_t {
11354    static_assert_uimm_bits!(LANE, 1);
11355    transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
11356}
11357#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
11358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"]
11359#[doc = "## Safety"]
11360#[doc = "  * Neon intrinsic unsafe"]
11361#[inline]
11362#[rustc_legacy_const_generics(2)]
11363#[target_feature(enable = "neon,rcpc3")]
11364#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
11365#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
11366#[cfg(target_has_atomic = "64")]
11367pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
11368    static_assert!(LANE == 0);
11369    transmute(vldap1_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
11370}
11371#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
11372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"]
11373#[doc = "## Safety"]
11374#[doc = "  * Neon intrinsic unsafe"]
11375#[inline]
11376#[rustc_legacy_const_generics(2)]
11377#[target_feature(enable = "neon,rcpc3")]
11378#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
11379#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
11380#[cfg(target_has_atomic = "64")]
11381pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
11382    static_assert_uimm_bits!(LANE, 1);
11383    transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
11384}
11385#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
11386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"]
11387#[doc = "## Safety"]
11388#[doc = "  * Neon intrinsic unsafe"]
11389#[inline]
11390#[rustc_legacy_const_generics(2)]
11391#[target_feature(enable = "neon,rcpc3")]
11392#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
11393#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
11394#[cfg(target_has_atomic = "64")]
11395pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
11396    static_assert!(LANE == 0);
11397    transmute(vldap1_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
11398}
11399#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
11400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"]
11401#[doc = "## Safety"]
11402#[doc = "  * Neon intrinsic unsafe"]
11403#[inline]
11404#[rustc_legacy_const_generics(2)]
11405#[target_feature(enable = "neon,rcpc3")]
11406#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
11407#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
11408#[cfg(target_has_atomic = "64")]
11409pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
11410    static_assert_uimm_bits!(LANE, 1);
11411    transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
11412}
11413#[doc = "Lookup table read with 2-bit indices"]
11414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"]
11415#[doc = "## Safety"]
11416#[doc = "  * Neon intrinsic unsafe"]
11417#[inline]
11418#[target_feature(enable = "neon,lut")]
11419#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11420#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11421#[rustc_legacy_const_generics(2)]
11422pub unsafe fn vluti2_lane_f16<const INDEX: i32>(a: float16x4_t, b: uint8x8_t) -> float16x8_t {
11423    static_assert!(INDEX >= 0 && INDEX <= 3);
11424    transmute(vluti2_lane_s16::<INDEX>(transmute(a), b))
11425}
11426#[doc = "Lookup table read with 2-bit indices"]
11427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"]
11428#[doc = "## Safety"]
11429#[doc = "  * Neon intrinsic unsafe"]
11430#[inline]
11431#[target_feature(enable = "neon,lut")]
11432#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11433#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11434#[rustc_legacy_const_generics(2)]
11435pub unsafe fn vluti2q_lane_f16<const INDEX: i32>(a: float16x8_t, b: uint8x8_t) -> float16x8_t {
11436    static_assert!(INDEX >= 0 && INDEX <= 3);
11437    transmute(vluti2q_lane_s16::<INDEX>(transmute(a), b))
11438}
11439#[doc = "Lookup table read with 2-bit indices"]
11440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
11441#[doc = "## Safety"]
11442#[doc = "  * Neon intrinsic unsafe"]
11443#[inline]
11444#[target_feature(enable = "neon,lut")]
11445#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11446#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11447#[rustc_legacy_const_generics(2)]
11448pub unsafe fn vluti2_lane_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
11449    static_assert!(INDEX >= 0 && INDEX <= 1);
11450    transmute(vluti2_lane_s8::<INDEX>(transmute(a), b))
11451}
11452#[doc = "Lookup table read with 2-bit indices"]
11453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
11454#[doc = "## Safety"]
11455#[doc = "  * Neon intrinsic unsafe"]
11456#[inline]
11457#[target_feature(enable = "neon,lut")]
11458#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11459#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11460#[rustc_legacy_const_generics(2)]
11461pub unsafe fn vluti2q_lane_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t {
11462    static_assert!(INDEX >= 0 && INDEX <= 1);
11463    transmute(vluti2q_lane_s8::<INDEX>(transmute(a), b))
11464}
11465#[doc = "Lookup table read with 2-bit indices"]
11466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
11467#[doc = "## Safety"]
11468#[doc = "  * Neon intrinsic unsafe"]
11469#[inline]
11470#[target_feature(enable = "neon,lut")]
11471#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11472#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11473#[rustc_legacy_const_generics(2)]
11474pub unsafe fn vluti2_lane_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t {
11475    static_assert!(INDEX >= 0 && INDEX <= 3);
11476    transmute(vluti2_lane_s16::<INDEX>(transmute(a), b))
11477}
11478#[doc = "Lookup table read with 2-bit indices"]
11479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
11480#[doc = "## Safety"]
11481#[doc = "  * Neon intrinsic unsafe"]
11482#[inline]
11483#[target_feature(enable = "neon,lut")]
11484#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11485#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11486#[rustc_legacy_const_generics(2)]
11487pub unsafe fn vluti2q_lane_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
11488    static_assert!(INDEX >= 0 && INDEX <= 3);
11489    transmute(vluti2q_lane_s16::<INDEX>(transmute(a), b))
11490}
11491#[doc = "Lookup table read with 2-bit indices"]
11492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
11493#[doc = "## Safety"]
11494#[doc = "  * Neon intrinsic unsafe"]
11495#[inline]
11496#[target_feature(enable = "neon,lut")]
11497#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11498#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11499#[rustc_legacy_const_generics(2)]
11500pub unsafe fn vluti2_lane_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t {
11501    static_assert!(INDEX >= 0 && INDEX <= 1);
11502    transmute(vluti2_lane_s8::<INDEX>(transmute(a), b))
11503}
11504#[doc = "Lookup table read with 2-bit indices"]
11505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
11506#[doc = "## Safety"]
11507#[doc = "  * Neon intrinsic unsafe"]
11508#[inline]
11509#[target_feature(enable = "neon,lut")]
11510#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11511#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11512#[rustc_legacy_const_generics(2)]
11513pub unsafe fn vluti2q_lane_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t {
11514    static_assert!(INDEX >= 0 && INDEX <= 1);
11515    transmute(vluti2q_lane_s8::<INDEX>(transmute(a), b))
11516}
11517#[doc = "Lookup table read with 2-bit indices"]
11518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
11519#[doc = "## Safety"]
11520#[doc = "  * Neon intrinsic unsafe"]
11521#[inline]
11522#[target_feature(enable = "neon,lut")]
11523#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11524#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11525#[rustc_legacy_const_generics(2)]
11526pub unsafe fn vluti2_lane_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t {
11527    static_assert!(INDEX >= 0 && INDEX <= 3);
11528    transmute(vluti2_lane_s16::<INDEX>(transmute(a), b))
11529}
11530#[doc = "Lookup table read with 2-bit indices"]
11531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
11532#[doc = "## Safety"]
11533#[doc = "  * Neon intrinsic unsafe"]
11534#[inline]
11535#[target_feature(enable = "neon,lut")]
11536#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11537#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11538#[rustc_legacy_const_generics(2)]
11539pub unsafe fn vluti2q_lane_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t {
11540    static_assert!(INDEX >= 0 && INDEX <= 3);
11541    transmute(vluti2q_lane_s16::<INDEX>(transmute(a), b))
11542}
11543#[doc = "Lookup table read with 2-bit indices"]
11544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"]
11545#[doc = "## Safety"]
11546#[doc = "  * Neon intrinsic unsafe"]
11547#[inline]
11548#[target_feature(enable = "neon,lut")]
11549#[cfg_attr(test, assert_instr(nop, LANE = 1))]
11550#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11551#[rustc_legacy_const_generics(2)]
11552pub unsafe fn vluti2_lane_s8<const LANE: i32>(a: int8x8_t, b: uint8x8_t) -> int8x16_t {
11553    static_assert!(LANE >= 0 && LANE <= 1);
11554    unsafe extern "unadjusted" {
11555        #[cfg_attr(
11556            any(target_arch = "aarch64", target_arch = "arm64ec"),
11557            link_name = "llvm.aarch64.neon.vluti2.lane.v16i8.v8i8"
11558        )]
11559        fn _vluti2_lane_s8(a: int8x8_t, b: uint8x8_t, n: i32) -> int8x16_t;
11560    }
11561    _vluti2_lane_s8(a, b, LANE)
11562}
11563#[doc = "Lookup table read with 2-bit indices"]
11564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"]
11565#[doc = "## Safety"]
11566#[doc = "  * Neon intrinsic unsafe"]
11567#[inline]
11568#[target_feature(enable = "neon,lut")]
11569#[cfg_attr(test, assert_instr(nop, LANE = 1))]
11570#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11571#[rustc_legacy_const_generics(2)]
11572pub unsafe fn vluti2q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> int8x16_t {
11573    static_assert!(LANE >= 0 && LANE <= 1);
11574    unsafe extern "unadjusted" {
11575        #[cfg_attr(
11576            any(target_arch = "aarch64", target_arch = "arm64ec"),
11577            link_name = "llvm.aarch64.neon.vluti2.lane.v16i8.v16i8"
11578        )]
11579        fn _vluti2q_lane_s8(a: int8x16_t, b: uint8x8_t, n: i32) -> int8x16_t;
11580    }
11581    _vluti2q_lane_s8(a, b, LANE)
11582}
11583#[doc = "Lookup table read with 2-bit indices"]
11584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"]
11585#[doc = "## Safety"]
11586#[doc = "  * Neon intrinsic unsafe"]
11587#[inline]
11588#[target_feature(enable = "neon,lut")]
11589#[cfg_attr(test, assert_instr(nop, LANE = 1))]
11590#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11591#[rustc_legacy_const_generics(2)]
11592pub unsafe fn vluti2_lane_s16<const LANE: i32>(a: int16x4_t, b: uint8x8_t) -> int16x8_t {
11593    static_assert!(LANE >= 0 && LANE <= 3);
11594    unsafe extern "unadjusted" {
11595        #[cfg_attr(
11596            any(target_arch = "aarch64", target_arch = "arm64ec"),
11597            link_name = "llvm.aarch64.neon.vluti2.lane.v8i16.v4i16"
11598        )]
11599        fn _vluti2_lane_s16(a: int16x4_t, b: uint8x8_t, n: i32) -> int16x8_t;
11600    }
11601    _vluti2_lane_s16(a, b, LANE)
11602}
11603#[doc = "Lookup table read with 2-bit indices"]
11604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"]
11605#[doc = "## Safety"]
11606#[doc = "  * Neon intrinsic unsafe"]
11607#[inline]
11608#[target_feature(enable = "neon,lut")]
11609#[cfg_attr(test, assert_instr(nop, LANE = 1))]
11610#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11611#[rustc_legacy_const_generics(2)]
11612pub unsafe fn vluti2q_lane_s16<const LANE: i32>(a: int16x8_t, b: uint8x8_t) -> int16x8_t {
11613    static_assert!(LANE >= 0 && LANE <= 3);
11614    unsafe extern "unadjusted" {
11615        #[cfg_attr(
11616            any(target_arch = "aarch64", target_arch = "arm64ec"),
11617            link_name = "llvm.aarch64.neon.vluti2.lane.v8i16.v8i16"
11618        )]
11619        fn _vluti2q_lane_s16(a: int16x8_t, b: uint8x8_t, n: i32) -> int16x8_t;
11620    }
11621    _vluti2q_lane_s16(a, b, LANE)
11622}
11623#[doc = "Lookup table read with 2-bit indices"]
11624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"]
11625#[doc = "## Safety"]
11626#[doc = "  * Neon intrinsic unsafe"]
11627#[inline]
11628#[target_feature(enable = "neon,lut")]
11629#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11630#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11631#[rustc_legacy_const_generics(2)]
11632pub unsafe fn vluti2_laneq_f16<const INDEX: i32>(a: float16x4_t, b: uint8x16_t) -> float16x8_t {
11633    static_assert!(INDEX >= 0 && INDEX <= 7);
11634    transmute(vluti2_laneq_s16::<INDEX>(transmute(a), b))
11635}
11636#[doc = "Lookup table read with 2-bit indices"]
11637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"]
11638#[doc = "## Safety"]
11639#[doc = "  * Neon intrinsic unsafe"]
11640#[inline]
11641#[target_feature(enable = "neon,lut")]
11642#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11643#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11644#[rustc_legacy_const_generics(2)]
11645pub unsafe fn vluti2q_laneq_f16<const INDEX: i32>(a: float16x8_t, b: uint8x16_t) -> float16x8_t {
11646    static_assert!(INDEX >= 0 && INDEX <= 7);
11647    transmute(vluti2q_laneq_s16::<INDEX>(transmute(a), b))
11648}
11649#[doc = "Lookup table read with 2-bit indices"]
11650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"]
11651#[doc = "## Safety"]
11652#[doc = "  * Neon intrinsic unsafe"]
11653#[inline]
11654#[target_feature(enable = "neon,lut")]
11655#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11656#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11657#[rustc_legacy_const_generics(2)]
11658pub unsafe fn vluti2_laneq_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x16_t) -> uint8x16_t {
11659    static_assert!(INDEX >= 0 && INDEX <= 3);
11660    transmute(vluti2_laneq_s8::<INDEX>(transmute(a), b))
11661}
11662#[doc = "Lookup table read with 2-bit indices"]
11663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"]
11664#[doc = "## Safety"]
11665#[doc = "  * Neon intrinsic unsafe"]
11666#[inline]
11667#[target_feature(enable = "neon,lut")]
11668#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11669#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11670#[rustc_legacy_const_generics(2)]
11671pub unsafe fn vluti2q_laneq_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
11672    static_assert!(INDEX >= 0 && INDEX <= 3);
11673    transmute(vluti2q_laneq_s8::<INDEX>(transmute(a), b))
11674}
11675#[doc = "Lookup table read with 2-bit indices"]
11676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"]
11677#[doc = "## Safety"]
11678#[doc = "  * Neon intrinsic unsafe"]
11679#[inline]
11680#[target_feature(enable = "neon,lut")]
11681#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11682#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11683#[rustc_legacy_const_generics(2)]
11684pub unsafe fn vluti2_laneq_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x16_t) -> uint16x8_t {
11685    static_assert!(INDEX >= 0 && INDEX <= 7);
11686    transmute(vluti2_laneq_s16::<INDEX>(transmute(a), b))
11687}
11688#[doc = "Lookup table read with 2-bit indices"]
11689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"]
11690#[doc = "## Safety"]
11691#[doc = "  * Neon intrinsic unsafe"]
11692#[inline]
11693#[target_feature(enable = "neon,lut")]
11694#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11695#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11696#[rustc_legacy_const_generics(2)]
11697pub unsafe fn vluti2q_laneq_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
11698    static_assert!(INDEX >= 0 && INDEX <= 7);
11699    transmute(vluti2q_laneq_s16::<INDEX>(transmute(a), b))
11700}
11701#[doc = "Lookup table read with 2-bit indices"]
11702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"]
11703#[doc = "## Safety"]
11704#[doc = "  * Neon intrinsic unsafe"]
11705#[inline]
11706#[target_feature(enable = "neon,lut")]
11707#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11708#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11709#[rustc_legacy_const_generics(2)]
11710pub unsafe fn vluti2_laneq_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x16_t) -> poly8x16_t {
11711    static_assert!(INDEX >= 0 && INDEX <= 3);
11712    transmute(vluti2_laneq_s8::<INDEX>(transmute(a), b))
11713}
11714#[doc = "Lookup table read with 2-bit indices"]
11715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"]
11716#[doc = "## Safety"]
11717#[doc = "  * Neon intrinsic unsafe"]
11718#[inline]
11719#[target_feature(enable = "neon,lut")]
11720#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11721#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11722#[rustc_legacy_const_generics(2)]
11723pub unsafe fn vluti2q_laneq_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
11724    static_assert!(INDEX >= 0 && INDEX <= 3);
11725    transmute(vluti2q_laneq_s8::<INDEX>(transmute(a), b))
11726}
11727#[doc = "Lookup table read with 2-bit indices"]
11728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"]
11729#[doc = "## Safety"]
11730#[doc = "  * Neon intrinsic unsafe"]
11731#[inline]
11732#[target_feature(enable = "neon,lut")]
11733#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11734#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11735#[rustc_legacy_const_generics(2)]
11736pub unsafe fn vluti2_laneq_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x16_t) -> poly16x8_t {
11737    static_assert!(INDEX >= 0 && INDEX <= 7);
11738    transmute(vluti2_laneq_s16::<INDEX>(transmute(a), b))
11739}
11740#[doc = "Lookup table read with 2-bit indices"]
11741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"]
11742#[doc = "## Safety"]
11743#[doc = "  * Neon intrinsic unsafe"]
11744#[inline]
11745#[target_feature(enable = "neon,lut")]
11746#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11747#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11748#[rustc_legacy_const_generics(2)]
11749pub unsafe fn vluti2q_laneq_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x16_t) -> poly16x8_t {
11750    static_assert!(INDEX >= 0 && INDEX <= 7);
11751    transmute(vluti2q_laneq_s16::<INDEX>(transmute(a), b))
11752}
11753#[doc = "Lookup table read with 2-bit indices"]
11754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"]
11755#[doc = "## Safety"]
11756#[doc = "  * Neon intrinsic unsafe"]
11757#[inline]
11758#[target_feature(enable = "neon,lut")]
11759#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11760#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11761#[rustc_legacy_const_generics(2)]
11762pub unsafe fn vluti2_laneq_s8<const INDEX: i32>(a: int8x8_t, b: uint8x16_t) -> int8x16_t {
11763    static_assert!(INDEX >= 0 && INDEX <= 3);
11764    unsafe extern "unadjusted" {
11765        #[cfg_attr(
11766            any(target_arch = "aarch64", target_arch = "arm64ec"),
11767            link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v8i8"
11768        )]
11769        fn _vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t, n: i32) -> int8x16_t;
11770    }
11771    _vluti2_laneq_s8(a, b, INDEX)
11772}
11773#[doc = "Lookup table read with 2-bit indices"]
11774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"]
11775#[doc = "## Safety"]
11776#[doc = "  * Neon intrinsic unsafe"]
11777#[inline]
11778#[target_feature(enable = "neon,lut")]
11779#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11780#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11781#[rustc_legacy_const_generics(2)]
11782pub unsafe fn vluti2q_laneq_s8<const INDEX: i32>(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
11783    static_assert!(INDEX >= 0 && INDEX <= 3);
11784    unsafe extern "unadjusted" {
11785        #[cfg_attr(
11786            any(target_arch = "aarch64", target_arch = "arm64ec"),
11787            link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v16i8"
11788        )]
11789        fn _vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t, n: i32) -> int8x16_t;
11790    }
11791    _vluti2q_laneq_s8(a, b, INDEX)
11792}
11793#[doc = "Lookup table read with 2-bit indices"]
11794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"]
11795#[doc = "## Safety"]
11796#[doc = "  * Neon intrinsic unsafe"]
11797#[inline]
11798#[target_feature(enable = "neon,lut")]
11799#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11800#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11801#[rustc_legacy_const_generics(2)]
11802pub unsafe fn vluti2_laneq_s16<const INDEX: i32>(a: int16x4_t, b: uint8x16_t) -> int16x8_t {
11803    static_assert!(INDEX >= 0 && INDEX <= 7);
11804    unsafe extern "unadjusted" {
11805        #[cfg_attr(
11806            any(target_arch = "aarch64", target_arch = "arm64ec"),
11807            link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v4i16"
11808        )]
11809        fn _vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t, n: i32) -> int16x8_t;
11810    }
11811    _vluti2_laneq_s16(a, b, INDEX)
11812}
11813#[doc = "Lookup table read with 2-bit indices"]
11814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"]
11815#[doc = "## Safety"]
11816#[doc = "  * Neon intrinsic unsafe"]
11817#[inline]
11818#[target_feature(enable = "neon,lut")]
11819#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
11820#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11821#[rustc_legacy_const_generics(2)]
11822pub unsafe fn vluti2q_laneq_s16<const INDEX: i32>(a: int16x8_t, b: uint8x16_t) -> int16x8_t {
11823    static_assert!(INDEX >= 0 && INDEX <= 7);
11824    unsafe extern "unadjusted" {
11825        #[cfg_attr(
11826            any(target_arch = "aarch64", target_arch = "arm64ec"),
11827            link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v8i16"
11828        )]
11829        fn _vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t, n: i32) -> int16x8_t;
11830    }
11831    _vluti2q_laneq_s16(a, b, INDEX)
11832}
11833#[doc = "Lookup table read with 4-bit indices"]
11834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"]
11835#[doc = "## Safety"]
11836#[doc = "  * Neon intrinsic unsafe"]
11837#[inline]
11838#[target_feature(enable = "neon,lut,fp16")]
11839#[cfg_attr(test, assert_instr(nop, LANE = 0))]
11840#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11841#[rustc_legacy_const_generics(2)]
11842pub unsafe fn vluti4q_lane_f16_x2<const LANE: i32>(a: float16x8x2_t, b: uint8x8_t) -> float16x8_t {
11843    static_assert!(LANE >= 0 && LANE <= 1);
11844    transmute(vluti4q_lane_s16_x2::<LANE>(transmute(a), b))
11845}
11846#[doc = "Lookup table read with 4-bit indices"]
11847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"]
11848#[doc = "## Safety"]
11849#[doc = "  * Neon intrinsic unsafe"]
11850#[inline]
11851#[target_feature(enable = "neon,lut")]
11852#[cfg_attr(test, assert_instr(nop, LANE = 0))]
11853#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11854#[rustc_legacy_const_generics(2)]
11855pub unsafe fn vluti4q_lane_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x8_t) -> uint16x8_t {
11856    static_assert!(LANE >= 0 && LANE <= 1);
11857    transmute(vluti4q_lane_s16_x2::<LANE>(transmute(a), b))
11858}
11859#[doc = "Lookup table read with 4-bit indices"]
11860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"]
11861#[doc = "## Safety"]
11862#[doc = "  * Neon intrinsic unsafe"]
11863#[inline]
11864#[target_feature(enable = "neon,lut")]
11865#[cfg_attr(test, assert_instr(nop, LANE = 0))]
11866#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11867#[rustc_legacy_const_generics(2)]
11868pub unsafe fn vluti4q_lane_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x8_t) -> poly16x8_t {
11869    static_assert!(LANE >= 0 && LANE <= 1);
11870    transmute(vluti4q_lane_s16_x2::<LANE>(transmute(a), b))
11871}
11872#[doc = "Lookup table read with 4-bit indices"]
11873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"]
11874#[doc = "## Safety"]
11875#[doc = "  * Neon intrinsic unsafe"]
11876#[inline]
11877#[target_feature(enable = "neon,lut")]
11878#[cfg_attr(test, assert_instr(nop, LANE = 0))]
11879#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11880#[rustc_legacy_const_generics(2)]
11881pub unsafe fn vluti4q_lane_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x8_t) -> int16x8_t {
11882    static_assert!(LANE >= 0 && LANE <= 1);
11883    unsafe extern "unadjusted" {
11884        #[cfg_attr(
11885            any(target_arch = "aarch64", target_arch = "arm64ec"),
11886            link_name = "llvm.aarch64.neon.vluti4q.lane.x2.v8i16"
11887        )]
11888        fn _vluti4q_lane_s16_x2(a: int16x8_t, a: int16x8_t, b: uint8x8_t, n: i32) -> int16x8_t;
11889    }
11890    _vluti4q_lane_s16_x2(a.0, a.1, b, LANE)
11891}
11892#[doc = "Lookup table read with 4-bit indices"]
11893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"]
11894#[doc = "## Safety"]
11895#[doc = "  * Neon intrinsic unsafe"]
11896#[inline]
11897#[target_feature(enable = "neon,lut")]
11898#[cfg_attr(test, assert_instr(nop, LANE = 0))]
11899#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11900#[rustc_legacy_const_generics(2)]
11901pub unsafe fn vluti4q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> int8x16_t {
11902    static_assert!(LANE == 0);
11903    unsafe extern "unadjusted" {
11904        #[cfg_attr(
11905            any(target_arch = "aarch64", target_arch = "arm64ec"),
11906            link_name = "llvm.aarch64.neon.vluti4q.lane.v8i8"
11907        )]
11908        fn _vluti4q_lane_s8(a: int8x16_t, b: uint8x8_t, n: i32) -> int8x16_t;
11909    }
11910    _vluti4q_lane_s8(a, b, LANE)
11911}
11912#[doc = "Lookup table read with 4-bit indices"]
11913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"]
11914#[doc = "## Safety"]
11915#[doc = "  * Neon intrinsic unsafe"]
11916#[inline]
11917#[target_feature(enable = "neon,lut")]
11918#[cfg_attr(test, assert_instr(nop, LANE = 0))]
11919#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11920#[rustc_legacy_const_generics(2)]
11921pub unsafe fn vluti4q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t {
11922    static_assert!(LANE == 0);
11923    transmute(vluti4q_lane_s8::<LANE>(transmute(a), b))
11924}
11925#[doc = "Lookup table read with 4-bit indices"]
11926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"]
11927#[doc = "## Safety"]
11928#[doc = "  * Neon intrinsic unsafe"]
11929#[inline]
11930#[target_feature(enable = "neon,lut")]
11931#[cfg_attr(test, assert_instr(nop, LANE = 0))]
11932#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11933#[rustc_legacy_const_generics(2)]
11934pub unsafe fn vluti4q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t {
11935    static_assert!(LANE == 0);
11936    transmute(vluti4q_lane_s8::<LANE>(transmute(a), b))
11937}
11938#[doc = "Lookup table read with 4-bit indices"]
11939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"]
11940#[doc = "## Safety"]
11941#[doc = "  * Neon intrinsic unsafe"]
11942#[inline]
11943#[target_feature(enable = "neon,lut,fp16")]
11944#[cfg_attr(test, assert_instr(nop, LANE = 3))]
11945#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11946#[rustc_legacy_const_generics(2)]
11947pub unsafe fn vluti4q_laneq_f16_x2<const LANE: i32>(
11948    a: float16x8x2_t,
11949    b: uint8x16_t,
11950) -> float16x8_t {
11951    static_assert!(LANE >= 0 && LANE <= 3);
11952    transmute(vluti4q_laneq_s16_x2::<LANE>(transmute(a), b))
11953}
11954#[doc = "Lookup table read with 4-bit indices"]
11955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"]
11956#[doc = "## Safety"]
11957#[doc = "  * Neon intrinsic unsafe"]
11958#[inline]
11959#[target_feature(enable = "neon,lut")]
11960#[cfg_attr(test, assert_instr(nop, LANE = 3))]
11961#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11962#[rustc_legacy_const_generics(2)]
11963pub unsafe fn vluti4q_laneq_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x16_t) -> uint16x8_t {
11964    static_assert!(LANE >= 0 && LANE <= 3);
11965    transmute(vluti4q_laneq_s16_x2::<LANE>(transmute(a), b))
11966}
11967#[doc = "Lookup table read with 4-bit indices"]
11968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"]
11969#[doc = "## Safety"]
11970#[doc = "  * Neon intrinsic unsafe"]
11971#[inline]
11972#[target_feature(enable = "neon,lut")]
11973#[cfg_attr(test, assert_instr(nop, LANE = 3))]
11974#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11975#[rustc_legacy_const_generics(2)]
11976pub unsafe fn vluti4q_laneq_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x16_t) -> poly16x8_t {
11977    static_assert!(LANE >= 0 && LANE <= 3);
11978    transmute(vluti4q_laneq_s16_x2::<LANE>(transmute(a), b))
11979}
11980#[doc = "Lookup table read with 4-bit indices"]
11981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"]
11982#[doc = "## Safety"]
11983#[doc = "  * Neon intrinsic unsafe"]
11984#[inline]
11985#[target_feature(enable = "neon,lut")]
11986#[cfg_attr(test, assert_instr(nop, LANE = 3))]
11987#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
11988#[rustc_legacy_const_generics(2)]
11989pub unsafe fn vluti4q_laneq_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x16_t) -> int16x8_t {
11990    static_assert!(LANE >= 0 && LANE <= 3);
11991    unsafe extern "unadjusted" {
11992        #[cfg_attr(
11993            any(target_arch = "aarch64", target_arch = "arm64ec"),
11994            link_name = "llvm.aarch64.neon.vluti4q.laneq.x2.v8i16"
11995        )]
11996        fn _vluti4q_laneq_s16_x2(a: int16x8_t, b: int16x8_t, c: uint8x16_t, n: i32) -> int16x8_t;
11997    }
11998    _vluti4q_laneq_s16_x2(a.0, a.1, b, LANE)
11999}
12000#[doc = "Lookup table read with 4-bit indices"]
12001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"]
12002#[doc = "## Safety"]
12003#[doc = "  * Neon intrinsic unsafe"]
12004#[inline]
12005#[target_feature(enable = "neon,lut")]
12006#[cfg_attr(test, assert_instr(nop, LANE = 0))]
12007#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
12008#[rustc_legacy_const_generics(2)]
12009pub unsafe fn vluti4q_laneq_s8<const LANE: i32>(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
12010    static_assert!(LANE >= 0 && LANE <= 1);
12011    unsafe extern "unadjusted" {
12012        #[cfg_attr(
12013            any(target_arch = "aarch64", target_arch = "arm64ec"),
12014            link_name = "llvm.aarch64.neon.vluti4q.laneq.v16i8"
12015        )]
12016        fn _vluti4q_laneq_s8(a: int8x16_t, b: uint8x16_t, n: i32) -> int8x16_t;
12017    }
12018    _vluti4q_laneq_s8(a, b, LANE)
12019}
12020#[doc = "Lookup table read with 4-bit indices"]
12021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"]
12022#[doc = "## Safety"]
12023#[doc = "  * Neon intrinsic unsafe"]
12024#[inline]
12025#[target_feature(enable = "neon,lut")]
12026#[cfg_attr(test, assert_instr(nop, LANE = 0))]
12027#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
12028#[rustc_legacy_const_generics(2)]
12029pub unsafe fn vluti4q_laneq_u8<const LANE: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
12030    static_assert!(LANE >= 0 && LANE <= 1);
12031    transmute(vluti4q_laneq_s8::<LANE>(transmute(a), b))
12032}
12033#[doc = "Lookup table read with 4-bit indices"]
12034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"]
12035#[doc = "## Safety"]
12036#[doc = "  * Neon intrinsic unsafe"]
12037#[inline]
12038#[target_feature(enable = "neon,lut")]
12039#[cfg_attr(test, assert_instr(nop, LANE = 0))]
12040#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
12041#[rustc_legacy_const_generics(2)]
12042pub unsafe fn vluti4q_laneq_p8<const LANE: i32>(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
12043    static_assert!(LANE >= 0 && LANE <= 1);
12044    transmute(vluti4q_laneq_s8::<LANE>(transmute(a), b))
12045}
12046#[doc = "Maximum (vector)"]
12047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"]
12048#[inline]
12049#[target_feature(enable = "neon")]
12050#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12051#[cfg_attr(test, assert_instr(fmax))]
12052pub fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
12053    unsafe extern "unadjusted" {
12054        #[cfg_attr(
12055            any(target_arch = "aarch64", target_arch = "arm64ec"),
12056            link_name = "llvm.aarch64.neon.fmax.v1f64"
12057        )]
12058        fn _vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
12059    }
12060    unsafe { _vmax_f64(a, b) }
12061}
12062#[doc = "Maximum (vector)"]
12063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)"]
12064#[inline]
12065#[target_feature(enable = "neon")]
12066#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12067#[cfg_attr(test, assert_instr(fmax))]
12068pub fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
12069    unsafe extern "unadjusted" {
12070        #[cfg_attr(
12071            any(target_arch = "aarch64", target_arch = "arm64ec"),
12072            link_name = "llvm.aarch64.neon.fmax.v2f64"
12073        )]
12074        fn _vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
12075    }
12076    unsafe { _vmaxq_f64(a, b) }
12077}
12078#[doc = "Maximum (vector)"]
12079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxh_f16)"]
12080#[inline]
12081#[target_feature(enable = "neon,fp16")]
12082#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12083#[cfg(not(target_arch = "arm64ec"))]
12084#[cfg_attr(test, assert_instr(fmax))]
12085pub fn vmaxh_f16(a: f16, b: f16) -> f16 {
12086    unsafe extern "unadjusted" {
12087        #[cfg_attr(
12088            any(target_arch = "aarch64", target_arch = "arm64ec"),
12089            link_name = "llvm.aarch64.neon.fmax.f16"
12090        )]
12091        fn _vmaxh_f16(a: f16, b: f16) -> f16;
12092    }
12093    unsafe { _vmaxh_f16(a, b) }
12094}
12095#[doc = "Floating-point Maximum Number (vector)"]
12096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)"]
12097#[inline]
12098#[target_feature(enable = "neon")]
12099#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12100#[cfg_attr(test, assert_instr(fmaxnm))]
12101pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
12102    unsafe extern "unadjusted" {
12103        #[cfg_attr(
12104            any(target_arch = "aarch64", target_arch = "arm64ec"),
12105            link_name = "llvm.aarch64.neon.fmaxnm.v1f64"
12106        )]
12107        fn _vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
12108    }
12109    unsafe { _vmaxnm_f64(a, b) }
12110}
12111#[doc = "Floating-point Maximum Number (vector)"]
12112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"]
12113#[inline]
12114#[target_feature(enable = "neon")]
12115#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12116#[cfg_attr(test, assert_instr(fmaxnm))]
12117pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
12118    unsafe extern "unadjusted" {
12119        #[cfg_attr(
12120            any(target_arch = "aarch64", target_arch = "arm64ec"),
12121            link_name = "llvm.aarch64.neon.fmaxnm.v2f64"
12122        )]
12123        fn _vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
12124    }
12125    unsafe { _vmaxnmq_f64(a, b) }
12126}
12127#[doc = "Floating-point Maximum Number"]
12128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"]
12129#[inline]
12130#[target_feature(enable = "neon,fp16")]
12131#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12132#[cfg(not(target_arch = "arm64ec"))]
12133#[cfg_attr(test, assert_instr(fmaxnm))]
12134pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 {
12135    unsafe extern "unadjusted" {
12136        #[cfg_attr(
12137            any(target_arch = "aarch64", target_arch = "arm64ec"),
12138            link_name = "llvm.aarch64.neon.fmaxnm.f16"
12139        )]
12140        fn _vmaxnmh_f16(a: f16, b: f16) -> f16;
12141    }
12142    unsafe { _vmaxnmh_f16(a, b) }
12143}
12144#[doc = "Floating-point maximum number across vector"]
12145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"]
12146#[inline]
12147#[target_feature(enable = "neon,fp16")]
12148#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12149#[cfg(not(target_arch = "arm64ec"))]
12150#[cfg_attr(test, assert_instr(fmaxnmv))]
12151pub fn vmaxnmv_f16(a: float16x4_t) -> f16 {
12152    unsafe extern "unadjusted" {
12153        #[cfg_attr(
12154            any(target_arch = "aarch64", target_arch = "arm64ec"),
12155            link_name = "llvm.aarch64.neon.fmaxnmv.f16.v4f16"
12156        )]
12157        fn _vmaxnmv_f16(a: float16x4_t) -> f16;
12158    }
12159    unsafe { _vmaxnmv_f16(a) }
12160}
12161#[doc = "Floating-point maximum number across vector"]
12162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"]
12163#[inline]
12164#[target_feature(enable = "neon,fp16")]
12165#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12166#[cfg(not(target_arch = "arm64ec"))]
12167#[cfg_attr(test, assert_instr(fmaxnmv))]
12168pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 {
12169    unsafe extern "unadjusted" {
12170        #[cfg_attr(
12171            any(target_arch = "aarch64", target_arch = "arm64ec"),
12172            link_name = "llvm.aarch64.neon.fmaxnmv.f16.v8f16"
12173        )]
12174        fn _vmaxnmvq_f16(a: float16x8_t) -> f16;
12175    }
12176    unsafe { _vmaxnmvq_f16(a) }
12177}
12178#[doc = "Floating-point maximum number across vector"]
12179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"]
12180#[inline]
12181#[target_feature(enable = "neon")]
12182#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12183#[cfg_attr(test, assert_instr(fmaxnmp))]
12184pub fn vmaxnmv_f32(a: float32x2_t) -> f32 {
12185    unsafe extern "unadjusted" {
12186        #[cfg_attr(
12187            any(target_arch = "aarch64", target_arch = "arm64ec"),
12188            link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32"
12189        )]
12190        fn _vmaxnmv_f32(a: float32x2_t) -> f32;
12191    }
12192    unsafe { _vmaxnmv_f32(a) }
12193}
12194#[doc = "Floating-point maximum number across vector"]
12195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"]
12196#[inline]
12197#[target_feature(enable = "neon")]
12198#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12199#[cfg_attr(test, assert_instr(fmaxnmp))]
12200pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 {
12201    unsafe extern "unadjusted" {
12202        #[cfg_attr(
12203            any(target_arch = "aarch64", target_arch = "arm64ec"),
12204            link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64"
12205        )]
12206        fn _vmaxnmvq_f64(a: float64x2_t) -> f64;
12207    }
12208    unsafe { _vmaxnmvq_f64(a) }
12209}
12210#[doc = "Floating-point maximum number across vector"]
12211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"]
12212#[inline]
12213#[target_feature(enable = "neon")]
12214#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12215#[cfg_attr(test, assert_instr(fmaxnmv))]
12216pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 {
12217    unsafe extern "unadjusted" {
12218        #[cfg_attr(
12219            any(target_arch = "aarch64", target_arch = "arm64ec"),
12220            link_name = "llvm.aarch64.neon.fmaxnmv.f32.v4f32"
12221        )]
12222        fn _vmaxnmvq_f32(a: float32x4_t) -> f32;
12223    }
12224    unsafe { _vmaxnmvq_f32(a) }
12225}
12226#[doc = "Floating-point maximum number across vector"]
12227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"]
12228#[inline]
12229#[target_feature(enable = "neon,fp16")]
12230#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12231#[cfg(not(target_arch = "arm64ec"))]
12232#[cfg_attr(test, assert_instr(fmaxv))]
12233pub fn vmaxv_f16(a: float16x4_t) -> f16 {
12234    unsafe extern "unadjusted" {
12235        #[cfg_attr(
12236            any(target_arch = "aarch64", target_arch = "arm64ec"),
12237            link_name = "llvm.aarch64.neon.fmaxv.f16.v4f16"
12238        )]
12239        fn _vmaxv_f16(a: float16x4_t) -> f16;
12240    }
12241    unsafe { _vmaxv_f16(a) }
12242}
12243#[doc = "Floating-point maximum number across vector"]
12244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f16)"]
12245#[inline]
12246#[target_feature(enable = "neon,fp16")]
12247#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12248#[cfg(not(target_arch = "arm64ec"))]
12249#[cfg_attr(test, assert_instr(fmaxv))]
12250pub fn vmaxvq_f16(a: float16x8_t) -> f16 {
12251    unsafe extern "unadjusted" {
12252        #[cfg_attr(
12253            any(target_arch = "aarch64", target_arch = "arm64ec"),
12254            link_name = "llvm.aarch64.neon.fmaxv.f16.v8f16"
12255        )]
12256        fn _vmaxvq_f16(a: float16x8_t) -> f16;
12257    }
12258    unsafe { _vmaxvq_f16(a) }
12259}
12260#[doc = "Horizontal vector max."]
12261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f32)"]
12262#[inline]
12263#[target_feature(enable = "neon")]
12264#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12265#[cfg_attr(test, assert_instr(fmaxp))]
12266pub fn vmaxv_f32(a: float32x2_t) -> f32 {
12267    unsafe extern "unadjusted" {
12268        #[cfg_attr(
12269            any(target_arch = "aarch64", target_arch = "arm64ec"),
12270            link_name = "llvm.aarch64.neon.fmaxv.f32.v2f32"
12271        )]
12272        fn _vmaxv_f32(a: float32x2_t) -> f32;
12273    }
12274    unsafe { _vmaxv_f32(a) }
12275}
12276#[doc = "Horizontal vector max."]
12277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f32)"]
12278#[inline]
12279#[target_feature(enable = "neon")]
12280#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12281#[cfg_attr(test, assert_instr(fmaxv))]
12282pub fn vmaxvq_f32(a: float32x4_t) -> f32 {
12283    unsafe extern "unadjusted" {
12284        #[cfg_attr(
12285            any(target_arch = "aarch64", target_arch = "arm64ec"),
12286            link_name = "llvm.aarch64.neon.fmaxv.f32.v4f32"
12287        )]
12288        fn _vmaxvq_f32(a: float32x4_t) -> f32;
12289    }
12290    unsafe { _vmaxvq_f32(a) }
12291}
12292#[doc = "Horizontal vector max."]
12293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f64)"]
12294#[inline]
12295#[target_feature(enable = "neon")]
12296#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12297#[cfg_attr(test, assert_instr(fmaxp))]
12298pub fn vmaxvq_f64(a: float64x2_t) -> f64 {
12299    unsafe extern "unadjusted" {
12300        #[cfg_attr(
12301            any(target_arch = "aarch64", target_arch = "arm64ec"),
12302            link_name = "llvm.aarch64.neon.fmaxv.f64.v2f64"
12303        )]
12304        fn _vmaxvq_f64(a: float64x2_t) -> f64;
12305    }
12306    unsafe { _vmaxvq_f64(a) }
12307}
12308#[doc = "Horizontal vector max."]
12309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s8)"]
12310#[inline]
12311#[target_feature(enable = "neon")]
12312#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12313#[cfg_attr(test, assert_instr(smaxv))]
12314pub fn vmaxv_s8(a: int8x8_t) -> i8 {
12315    unsafe { simd_reduce_max(a) }
12316}
12317#[doc = "Horizontal vector max."]
12318#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"]
12319#[inline]
12320#[target_feature(enable = "neon")]
12321#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12322#[cfg_attr(test, assert_instr(smaxv))]
12323pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
12324    unsafe { simd_reduce_max(a) }
12325}
12326#[doc = "Horizontal vector max."]
12327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"]
12328#[inline]
12329#[target_feature(enable = "neon")]
12330#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12331#[cfg_attr(test, assert_instr(smaxv))]
12332pub fn vmaxv_s16(a: int16x4_t) -> i16 {
12333    unsafe { simd_reduce_max(a) }
12334}
12335#[doc = "Horizontal vector max."]
12336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"]
12337#[inline]
12338#[target_feature(enable = "neon")]
12339#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12340#[cfg_attr(test, assert_instr(smaxv))]
12341pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
12342    unsafe { simd_reduce_max(a) }
12343}
12344#[doc = "Horizontal vector max."]
12345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"]
12346#[inline]
12347#[target_feature(enable = "neon")]
12348#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12349#[cfg_attr(test, assert_instr(smaxp))]
12350pub fn vmaxv_s32(a: int32x2_t) -> i32 {
12351    unsafe { simd_reduce_max(a) }
12352}
12353#[doc = "Horizontal vector max."]
12354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"]
12355#[inline]
12356#[target_feature(enable = "neon")]
12357#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12358#[cfg_attr(test, assert_instr(smaxv))]
12359pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
12360    unsafe { simd_reduce_max(a) }
12361}
12362#[doc = "Horizontal vector max."]
12363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"]
12364#[inline]
12365#[target_feature(enable = "neon")]
12366#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12367#[cfg_attr(test, assert_instr(umaxv))]
12368pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
12369    unsafe { simd_reduce_max(a) }
12370}
12371#[doc = "Horizontal vector max."]
12372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"]
12373#[inline]
12374#[target_feature(enable = "neon")]
12375#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12376#[cfg_attr(test, assert_instr(umaxv))]
12377pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
12378    unsafe { simd_reduce_max(a) }
12379}
12380#[doc = "Horizontal vector max."]
12381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"]
12382#[inline]
12383#[target_feature(enable = "neon")]
12384#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12385#[cfg_attr(test, assert_instr(umaxv))]
12386pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
12387    unsafe { simd_reduce_max(a) }
12388}
12389#[doc = "Horizontal vector max."]
12390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"]
12391#[inline]
12392#[target_feature(enable = "neon")]
12393#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12394#[cfg_attr(test, assert_instr(umaxv))]
12395pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
12396    unsafe { simd_reduce_max(a) }
12397}
12398#[doc = "Horizontal vector max."]
12399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"]
12400#[inline]
12401#[target_feature(enable = "neon")]
12402#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12403#[cfg_attr(test, assert_instr(umaxp))]
12404pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
12405    unsafe { simd_reduce_max(a) }
12406}
12407#[doc = "Horizontal vector max."]
12408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"]
12409#[inline]
12410#[target_feature(enable = "neon")]
12411#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12412#[cfg_attr(test, assert_instr(umaxv))]
12413pub fn vmaxvq_u32(a: uint32x4_t) -> u32 {
12414    unsafe { simd_reduce_max(a) }
12415}
12416#[doc = "Minimum (vector)"]
12417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"]
12418#[inline]
12419#[target_feature(enable = "neon")]
12420#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12421#[cfg_attr(test, assert_instr(fmin))]
12422pub fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
12423    unsafe extern "unadjusted" {
12424        #[cfg_attr(
12425            any(target_arch = "aarch64", target_arch = "arm64ec"),
12426            link_name = "llvm.aarch64.neon.fmin.v1f64"
12427        )]
12428        fn _vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
12429    }
12430    unsafe { _vmin_f64(a, b) }
12431}
12432#[doc = "Minimum (vector)"]
12433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)"]
12434#[inline]
12435#[target_feature(enable = "neon")]
12436#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12437#[cfg_attr(test, assert_instr(fmin))]
12438pub fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
12439    unsafe extern "unadjusted" {
12440        #[cfg_attr(
12441            any(target_arch = "aarch64", target_arch = "arm64ec"),
12442            link_name = "llvm.aarch64.neon.fmin.v2f64"
12443        )]
12444        fn _vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
12445    }
12446    unsafe { _vminq_f64(a, b) }
12447}
12448#[doc = "Minimum (vector)"]
12449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminh_f16)"]
12450#[inline]
12451#[target_feature(enable = "neon,fp16")]
12452#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12453#[cfg(not(target_arch = "arm64ec"))]
12454#[cfg_attr(test, assert_instr(fmin))]
12455pub fn vminh_f16(a: f16, b: f16) -> f16 {
12456    unsafe extern "unadjusted" {
12457        #[cfg_attr(
12458            any(target_arch = "aarch64", target_arch = "arm64ec"),
12459            link_name = "llvm.aarch64.neon.fmin.f16"
12460        )]
12461        fn _vminh_f16(a: f16, b: f16) -> f16;
12462    }
12463    unsafe { _vminh_f16(a, b) }
12464}
12465#[doc = "Floating-point Minimum Number (vector)"]
12466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)"]
12467#[inline]
12468#[target_feature(enable = "neon")]
12469#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12470#[cfg_attr(test, assert_instr(fminnm))]
12471pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
12472    unsafe extern "unadjusted" {
12473        #[cfg_attr(
12474            any(target_arch = "aarch64", target_arch = "arm64ec"),
12475            link_name = "llvm.aarch64.neon.fminnm.v1f64"
12476        )]
12477        fn _vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
12478    }
12479    unsafe { _vminnm_f64(a, b) }
12480}
12481#[doc = "Floating-point Minimum Number (vector)"]
12482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"]
12483#[inline]
12484#[target_feature(enable = "neon")]
12485#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12486#[cfg_attr(test, assert_instr(fminnm))]
12487pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
12488    unsafe extern "unadjusted" {
12489        #[cfg_attr(
12490            any(target_arch = "aarch64", target_arch = "arm64ec"),
12491            link_name = "llvm.aarch64.neon.fminnm.v2f64"
12492        )]
12493        fn _vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
12494    }
12495    unsafe { _vminnmq_f64(a, b) }
12496}
12497#[doc = "Floating-point Minimum Number"]
12498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"]
12499#[inline]
12500#[target_feature(enable = "neon,fp16")]
12501#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12502#[cfg(not(target_arch = "arm64ec"))]
12503#[cfg_attr(test, assert_instr(fminnm))]
12504pub fn vminnmh_f16(a: f16, b: f16) -> f16 {
12505    unsafe extern "unadjusted" {
12506        #[cfg_attr(
12507            any(target_arch = "aarch64", target_arch = "arm64ec"),
12508            link_name = "llvm.aarch64.neon.fminnm.f16"
12509        )]
12510        fn _vminnmh_f16(a: f16, b: f16) -> f16;
12511    }
12512    unsafe { _vminnmh_f16(a, b) }
12513}
12514#[doc = "Floating-point minimum number across vector"]
12515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"]
12516#[inline]
12517#[target_feature(enable = "neon,fp16")]
12518#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12519#[cfg(not(target_arch = "arm64ec"))]
12520#[cfg_attr(test, assert_instr(fminnmv))]
12521pub fn vminnmv_f16(a: float16x4_t) -> f16 {
12522    unsafe extern "unadjusted" {
12523        #[cfg_attr(
12524            any(target_arch = "aarch64", target_arch = "arm64ec"),
12525            link_name = "llvm.aarch64.neon.fminnmv.f16.v4f16"
12526        )]
12527        fn _vminnmv_f16(a: float16x4_t) -> f16;
12528    }
12529    unsafe { _vminnmv_f16(a) }
12530}
12531#[doc = "Floating-point minimum number across vector"]
12532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"]
12533#[inline]
12534#[target_feature(enable = "neon,fp16")]
12535#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12536#[cfg(not(target_arch = "arm64ec"))]
12537#[cfg_attr(test, assert_instr(fminnmv))]
12538pub fn vminnmvq_f16(a: float16x8_t) -> f16 {
12539    unsafe extern "unadjusted" {
12540        #[cfg_attr(
12541            any(target_arch = "aarch64", target_arch = "arm64ec"),
12542            link_name = "llvm.aarch64.neon.fminnmv.f16.v8f16"
12543        )]
12544        fn _vminnmvq_f16(a: float16x8_t) -> f16;
12545    }
12546    unsafe { _vminnmvq_f16(a) }
12547}
12548#[doc = "Floating-point minimum number across vector"]
12549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"]
12550#[inline]
12551#[target_feature(enable = "neon")]
12552#[cfg_attr(test, assert_instr(fminnmp))]
12553#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12554pub fn vminnmv_f32(a: float32x2_t) -> f32 {
12555    unsafe extern "unadjusted" {
12556        #[cfg_attr(
12557            any(target_arch = "aarch64", target_arch = "arm64ec"),
12558            link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32"
12559        )]
12560        fn _vminnmv_f32(a: float32x2_t) -> f32;
12561    }
12562    unsafe { _vminnmv_f32(a) }
12563}
12564#[doc = "Floating-point minimum number across vector"]
12565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"]
12566#[inline]
12567#[target_feature(enable = "neon")]
12568#[cfg_attr(test, assert_instr(fminnmp))]
12569#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12570pub fn vminnmvq_f64(a: float64x2_t) -> f64 {
12571    unsafe extern "unadjusted" {
12572        #[cfg_attr(
12573            any(target_arch = "aarch64", target_arch = "arm64ec"),
12574            link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64"
12575        )]
12576        fn _vminnmvq_f64(a: float64x2_t) -> f64;
12577    }
12578    unsafe { _vminnmvq_f64(a) }
12579}
12580#[doc = "Floating-point minimum number across vector"]
12581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"]
12582#[inline]
12583#[target_feature(enable = "neon")]
12584#[cfg_attr(test, assert_instr(fminnmv))]
12585#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12586pub fn vminnmvq_f32(a: float32x4_t) -> f32 {
12587    unsafe extern "unadjusted" {
12588        #[cfg_attr(
12589            any(target_arch = "aarch64", target_arch = "arm64ec"),
12590            link_name = "llvm.aarch64.neon.fminnmv.f32.v4f32"
12591        )]
12592        fn _vminnmvq_f32(a: float32x4_t) -> f32;
12593    }
12594    unsafe { _vminnmvq_f32(a) }
12595}
12596#[doc = "Floating-point minimum number across vector"]
12597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"]
12598#[inline]
12599#[target_feature(enable = "neon,fp16")]
12600#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12601#[cfg(not(target_arch = "arm64ec"))]
12602#[cfg_attr(test, assert_instr(fminv))]
12603pub fn vminv_f16(a: float16x4_t) -> f16 {
12604    unsafe extern "unadjusted" {
12605        #[cfg_attr(
12606            any(target_arch = "aarch64", target_arch = "arm64ec"),
12607            link_name = "llvm.aarch64.neon.fminv.f16.v4f16"
12608        )]
12609        fn _vminv_f16(a: float16x4_t) -> f16;
12610    }
12611    unsafe { _vminv_f16(a) }
12612}
12613#[doc = "Floating-point minimum number across vector"]
12614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f16)"]
12615#[inline]
12616#[target_feature(enable = "neon,fp16")]
12617#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12618#[cfg(not(target_arch = "arm64ec"))]
12619#[cfg_attr(test, assert_instr(fminv))]
12620pub fn vminvq_f16(a: float16x8_t) -> f16 {
12621    unsafe extern "unadjusted" {
12622        #[cfg_attr(
12623            any(target_arch = "aarch64", target_arch = "arm64ec"),
12624            link_name = "llvm.aarch64.neon.fminv.f16.v8f16"
12625        )]
12626        fn _vminvq_f16(a: float16x8_t) -> f16;
12627    }
12628    unsafe { _vminvq_f16(a) }
12629}
12630#[doc = "Horizontal vector min."]
12631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f32)"]
12632#[inline]
12633#[target_feature(enable = "neon")]
12634#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12635#[cfg_attr(test, assert_instr(fminp))]
12636pub fn vminv_f32(a: float32x2_t) -> f32 {
12637    unsafe extern "unadjusted" {
12638        #[cfg_attr(
12639            any(target_arch = "aarch64", target_arch = "arm64ec"),
12640            link_name = "llvm.aarch64.neon.fminv.f32.v2f32"
12641        )]
12642        fn _vminv_f32(a: float32x2_t) -> f32;
12643    }
12644    unsafe { _vminv_f32(a) }
12645}
12646#[doc = "Horizontal vector min."]
12647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f32)"]
12648#[inline]
12649#[target_feature(enable = "neon")]
12650#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12651#[cfg_attr(test, assert_instr(fminv))]
12652pub fn vminvq_f32(a: float32x4_t) -> f32 {
12653    unsafe extern "unadjusted" {
12654        #[cfg_attr(
12655            any(target_arch = "aarch64", target_arch = "arm64ec"),
12656            link_name = "llvm.aarch64.neon.fminv.f32.v4f32"
12657        )]
12658        fn _vminvq_f32(a: float32x4_t) -> f32;
12659    }
12660    unsafe { _vminvq_f32(a) }
12661}
12662#[doc = "Horizontal vector min."]
12663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f64)"]
12664#[inline]
12665#[target_feature(enable = "neon")]
12666#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12667#[cfg_attr(test, assert_instr(fminp))]
12668pub fn vminvq_f64(a: float64x2_t) -> f64 {
12669    unsafe extern "unadjusted" {
12670        #[cfg_attr(
12671            any(target_arch = "aarch64", target_arch = "arm64ec"),
12672            link_name = "llvm.aarch64.neon.fminv.f64.v2f64"
12673        )]
12674        fn _vminvq_f64(a: float64x2_t) -> f64;
12675    }
12676    unsafe { _vminvq_f64(a) }
12677}
12678#[doc = "Horizontal vector min."]
12679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s8)"]
12680#[inline]
12681#[target_feature(enable = "neon")]
12682#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12683#[cfg_attr(test, assert_instr(sminv))]
12684pub fn vminv_s8(a: int8x8_t) -> i8 {
12685    unsafe { simd_reduce_min(a) }
12686}
12687#[doc = "Horizontal vector min."]
12688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"]
12689#[inline]
12690#[target_feature(enable = "neon")]
12691#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12692#[cfg_attr(test, assert_instr(sminv))]
12693pub fn vminvq_s8(a: int8x16_t) -> i8 {
12694    unsafe { simd_reduce_min(a) }
12695}
12696#[doc = "Horizontal vector min."]
12697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"]
12698#[inline]
12699#[target_feature(enable = "neon")]
12700#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12701#[cfg_attr(test, assert_instr(sminv))]
12702pub fn vminv_s16(a: int16x4_t) -> i16 {
12703    unsafe { simd_reduce_min(a) }
12704}
12705#[doc = "Horizontal vector min."]
12706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"]
12707#[inline]
12708#[target_feature(enable = "neon")]
12709#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12710#[cfg_attr(test, assert_instr(sminv))]
12711pub fn vminvq_s16(a: int16x8_t) -> i16 {
12712    unsafe { simd_reduce_min(a) }
12713}
12714#[doc = "Horizontal vector min."]
12715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"]
12716#[inline]
12717#[target_feature(enable = "neon")]
12718#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12719#[cfg_attr(test, assert_instr(sminp))]
12720pub fn vminv_s32(a: int32x2_t) -> i32 {
12721    unsafe { simd_reduce_min(a) }
12722}
12723#[doc = "Horizontal vector min."]
12724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"]
12725#[inline]
12726#[target_feature(enable = "neon")]
12727#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12728#[cfg_attr(test, assert_instr(sminv))]
12729pub fn vminvq_s32(a: int32x4_t) -> i32 {
12730    unsafe { simd_reduce_min(a) }
12731}
12732#[doc = "Horizontal vector min."]
12733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"]
12734#[inline]
12735#[target_feature(enable = "neon")]
12736#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12737#[cfg_attr(test, assert_instr(uminv))]
12738pub fn vminv_u8(a: uint8x8_t) -> u8 {
12739    unsafe { simd_reduce_min(a) }
12740}
12741#[doc = "Horizontal vector min."]
12742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"]
12743#[inline]
12744#[target_feature(enable = "neon")]
12745#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12746#[cfg_attr(test, assert_instr(uminv))]
12747pub fn vminvq_u8(a: uint8x16_t) -> u8 {
12748    unsafe { simd_reduce_min(a) }
12749}
12750#[doc = "Horizontal vector min."]
12751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"]
12752#[inline]
12753#[target_feature(enable = "neon")]
12754#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12755#[cfg_attr(test, assert_instr(uminv))]
12756pub fn vminv_u16(a: uint16x4_t) -> u16 {
12757    unsafe { simd_reduce_min(a) }
12758}
12759#[doc = "Horizontal vector min."]
12760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"]
12761#[inline]
12762#[target_feature(enable = "neon")]
12763#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12764#[cfg_attr(test, assert_instr(uminv))]
12765pub fn vminvq_u16(a: uint16x8_t) -> u16 {
12766    unsafe { simd_reduce_min(a) }
12767}
12768#[doc = "Horizontal vector min."]
12769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"]
12770#[inline]
12771#[target_feature(enable = "neon")]
12772#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12773#[cfg_attr(test, assert_instr(uminp))]
12774pub fn vminv_u32(a: uint32x2_t) -> u32 {
12775    unsafe { simd_reduce_min(a) }
12776}
12777#[doc = "Horizontal vector min."]
12778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"]
12779#[inline]
12780#[target_feature(enable = "neon")]
12781#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12782#[cfg_attr(test, assert_instr(uminv))]
12783pub fn vminvq_u32(a: uint32x4_t) -> u32 {
12784    unsafe { simd_reduce_min(a) }
12785}
12786#[doc = "Floating-point multiply-add to accumulator"]
12787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"]
12788#[inline]
12789#[target_feature(enable = "neon")]
12790#[cfg_attr(test, assert_instr(fmul))]
12791#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12792pub fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
12793    unsafe { simd_add(a, simd_mul(b, c)) }
12794}
12795#[doc = "Floating-point multiply-add to accumulator"]
12796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64)"]
12797#[inline]
12798#[target_feature(enable = "neon")]
12799#[cfg_attr(test, assert_instr(fmul))]
12800#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12801pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
12802    unsafe { simd_add(a, simd_mul(b, c)) }
12803}
12804#[doc = "Multiply-add long"]
12805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"]
12806#[inline]
12807#[target_feature(enable = "neon")]
12808#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
12809#[rustc_legacy_const_generics(3)]
12810#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12811pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
12812    static_assert_uimm_bits!(LANE, 2);
12813    vmlal_high_s16(a, b, vdupq_lane_s16::<LANE>(c))
12814}
12815#[doc = "Multiply-add long"]
12816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"]
12817#[inline]
12818#[target_feature(enable = "neon")]
12819#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
12820#[rustc_legacy_const_generics(3)]
12821#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12822pub fn vmlal_high_laneq_s16<const LANE: i32>(
12823    a: int32x4_t,
12824    b: int16x8_t,
12825    c: int16x8_t,
12826) -> int32x4_t {
12827    static_assert_uimm_bits!(LANE, 3);
12828    vmlal_high_s16(a, b, vdupq_laneq_s16::<LANE>(c))
12829}
12830#[doc = "Multiply-add long"]
12831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"]
12832#[inline]
12833#[target_feature(enable = "neon")]
12834#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
12835#[rustc_legacy_const_generics(3)]
12836#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12837pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
12838    static_assert_uimm_bits!(LANE, 1);
12839    vmlal_high_s32(a, b, vdupq_lane_s32::<LANE>(c))
12840}
12841#[doc = "Multiply-add long"]
12842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"]
12843#[inline]
12844#[target_feature(enable = "neon")]
12845#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
12846#[rustc_legacy_const_generics(3)]
12847#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12848pub fn vmlal_high_laneq_s32<const LANE: i32>(
12849    a: int64x2_t,
12850    b: int32x4_t,
12851    c: int32x4_t,
12852) -> int64x2_t {
12853    static_assert_uimm_bits!(LANE, 2);
12854    vmlal_high_s32(a, b, vdupq_laneq_s32::<LANE>(c))
12855}
12856#[doc = "Multiply-add long"]
12857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"]
12858#[inline]
12859#[target_feature(enable = "neon")]
12860#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
12861#[rustc_legacy_const_generics(3)]
12862#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12863pub fn vmlal_high_lane_u16<const LANE: i32>(
12864    a: uint32x4_t,
12865    b: uint16x8_t,
12866    c: uint16x4_t,
12867) -> uint32x4_t {
12868    static_assert_uimm_bits!(LANE, 2);
12869    vmlal_high_u16(a, b, vdupq_lane_u16::<LANE>(c))
12870}
12871#[doc = "Multiply-add long"]
12872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"]
12873#[inline]
12874#[target_feature(enable = "neon")]
12875#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
12876#[rustc_legacy_const_generics(3)]
12877#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12878pub fn vmlal_high_laneq_u16<const LANE: i32>(
12879    a: uint32x4_t,
12880    b: uint16x8_t,
12881    c: uint16x8_t,
12882) -> uint32x4_t {
12883    static_assert_uimm_bits!(LANE, 3);
12884    vmlal_high_u16(a, b, vdupq_laneq_u16::<LANE>(c))
12885}
12886#[doc = "Multiply-add long"]
12887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"]
12888#[inline]
12889#[target_feature(enable = "neon")]
12890#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
12891#[rustc_legacy_const_generics(3)]
12892#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12893pub fn vmlal_high_lane_u32<const LANE: i32>(
12894    a: uint64x2_t,
12895    b: uint32x4_t,
12896    c: uint32x2_t,
12897) -> uint64x2_t {
12898    static_assert_uimm_bits!(LANE, 1);
12899    vmlal_high_u32(a, b, vdupq_lane_u32::<LANE>(c))
12900}
12901#[doc = "Multiply-add long"]
12902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"]
12903#[inline]
12904#[target_feature(enable = "neon")]
12905#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
12906#[rustc_legacy_const_generics(3)]
12907#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12908pub fn vmlal_high_laneq_u32<const LANE: i32>(
12909    a: uint64x2_t,
12910    b: uint32x4_t,
12911    c: uint32x4_t,
12912) -> uint64x2_t {
12913    static_assert_uimm_bits!(LANE, 2);
12914    vmlal_high_u32(a, b, vdupq_laneq_u32::<LANE>(c))
12915}
12916#[doc = "Multiply-add long"]
12917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"]
12918#[inline]
12919#[target_feature(enable = "neon")]
12920#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
12921#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12922pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
12923    vmlal_high_s16(a, b, vdupq_n_s16(c))
12924}
12925#[doc = "Multiply-add long"]
12926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"]
12927#[inline]
12928#[target_feature(enable = "neon")]
12929#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
12930#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12931pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
12932    vmlal_high_s32(a, b, vdupq_n_s32(c))
12933}
12934#[doc = "Multiply-add long"]
12935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"]
12936#[inline]
12937#[target_feature(enable = "neon")]
12938#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
12939#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12940pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
12941    vmlal_high_u16(a, b, vdupq_n_u16(c))
12942}
12943#[doc = "Multiply-add long"]
12944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"]
12945#[inline]
12946#[target_feature(enable = "neon")]
12947#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
12948#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12949pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
12950    vmlal_high_u32(a, b, vdupq_n_u32(c))
12951}
12952#[doc = "Signed multiply-add long"]
12953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"]
12954#[inline]
12955#[target_feature(enable = "neon")]
12956#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
12957#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12958pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
12959    let b = vget_high_s8(b);
12960    let c = vget_high_s8(c);
12961    vmlal_s8(a, b, c)
12962}
12963#[doc = "Signed multiply-add long"]
12964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"]
12965#[inline]
12966#[target_feature(enable = "neon")]
12967#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
12968#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12969pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
12970    let b = vget_high_s16(b);
12971    let c = vget_high_s16(c);
12972    vmlal_s16(a, b, c)
12973}
12974#[doc = "Signed multiply-add long"]
12975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"]
12976#[inline]
12977#[target_feature(enable = "neon")]
12978#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
12979#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12980pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
12981    let b = vget_high_s32(b);
12982    let c = vget_high_s32(c);
12983    vmlal_s32(a, b, c)
12984}
12985#[doc = "Unsigned multiply-add long"]
12986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"]
12987#[inline]
12988#[target_feature(enable = "neon")]
12989#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
12990#[stable(feature = "neon_intrinsics", since = "1.59.0")]
12991pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
12992    let b = vget_high_u8(b);
12993    let c = vget_high_u8(c);
12994    vmlal_u8(a, b, c)
12995}
12996#[doc = "Unsigned multiply-add long"]
12997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"]
12998#[inline]
12999#[target_feature(enable = "neon")]
13000#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
13001#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13002pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
13003    let b = vget_high_u16(b);
13004    let c = vget_high_u16(c);
13005    vmlal_u16(a, b, c)
13006}
13007#[doc = "Unsigned multiply-add long"]
13008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"]
13009#[inline]
13010#[target_feature(enable = "neon")]
13011#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
13012#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13013pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
13014    let b = vget_high_u32(b);
13015    let c = vget_high_u32(c);
13016    vmlal_u32(a, b, c)
13017}
13018#[doc = "Floating-point multiply-subtract from accumulator"]
13019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"]
13020#[inline]
13021#[target_feature(enable = "neon")]
13022#[cfg_attr(test, assert_instr(fmul))]
13023#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13024pub fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
13025    unsafe { simd_sub(a, simd_mul(b, c)) }
13026}
13027#[doc = "Floating-point multiply-subtract from accumulator"]
13028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64)"]
13029#[inline]
13030#[target_feature(enable = "neon")]
13031#[cfg_attr(test, assert_instr(fmul))]
13032#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13033pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
13034    unsafe { simd_sub(a, simd_mul(b, c)) }
13035}
13036#[doc = "Multiply-subtract long"]
13037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"]
13038#[inline]
13039#[target_feature(enable = "neon")]
13040#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
13041#[rustc_legacy_const_generics(3)]
13042#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13043pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
13044    static_assert_uimm_bits!(LANE, 2);
13045    vmlsl_high_s16(a, b, vdupq_lane_s16::<LANE>(c))
13046}
13047#[doc = "Multiply-subtract long"]
13048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"]
13049#[inline]
13050#[target_feature(enable = "neon")]
13051#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
13052#[rustc_legacy_const_generics(3)]
13053#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13054pub fn vmlsl_high_laneq_s16<const LANE: i32>(
13055    a: int32x4_t,
13056    b: int16x8_t,
13057    c: int16x8_t,
13058) -> int32x4_t {
13059    static_assert_uimm_bits!(LANE, 3);
13060    vmlsl_high_s16(a, b, vdupq_laneq_s16::<LANE>(c))
13061}
13062#[doc = "Multiply-subtract long"]
13063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"]
13064#[inline]
13065#[target_feature(enable = "neon")]
13066#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
13067#[rustc_legacy_const_generics(3)]
13068#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13069pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
13070    static_assert_uimm_bits!(LANE, 1);
13071    vmlsl_high_s32(a, b, vdupq_lane_s32::<LANE>(c))
13072}
13073#[doc = "Multiply-subtract long"]
13074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"]
13075#[inline]
13076#[target_feature(enable = "neon")]
13077#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
13078#[rustc_legacy_const_generics(3)]
13079#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13080pub fn vmlsl_high_laneq_s32<const LANE: i32>(
13081    a: int64x2_t,
13082    b: int32x4_t,
13083    c: int32x4_t,
13084) -> int64x2_t {
13085    static_assert_uimm_bits!(LANE, 2);
13086    vmlsl_high_s32(a, b, vdupq_laneq_s32::<LANE>(c))
13087}
13088#[doc = "Multiply-subtract long"]
13089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"]
13090#[inline]
13091#[target_feature(enable = "neon")]
13092#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
13093#[rustc_legacy_const_generics(3)]
13094#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13095pub fn vmlsl_high_lane_u16<const LANE: i32>(
13096    a: uint32x4_t,
13097    b: uint16x8_t,
13098    c: uint16x4_t,
13099) -> uint32x4_t {
13100    static_assert_uimm_bits!(LANE, 2);
13101    vmlsl_high_u16(a, b, vdupq_lane_u16::<LANE>(c))
13102}
13103#[doc = "Multiply-subtract long"]
13104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"]
13105#[inline]
13106#[target_feature(enable = "neon")]
13107#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
13108#[rustc_legacy_const_generics(3)]
13109#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13110pub fn vmlsl_high_laneq_u16<const LANE: i32>(
13111    a: uint32x4_t,
13112    b: uint16x8_t,
13113    c: uint16x8_t,
13114) -> uint32x4_t {
13115    static_assert_uimm_bits!(LANE, 3);
13116    vmlsl_high_u16(a, b, vdupq_laneq_u16::<LANE>(c))
13117}
13118#[doc = "Multiply-subtract long"]
13119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"]
13120#[inline]
13121#[target_feature(enable = "neon")]
13122#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
13123#[rustc_legacy_const_generics(3)]
13124#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13125pub fn vmlsl_high_lane_u32<const LANE: i32>(
13126    a: uint64x2_t,
13127    b: uint32x4_t,
13128    c: uint32x2_t,
13129) -> uint64x2_t {
13130    static_assert_uimm_bits!(LANE, 1);
13131    vmlsl_high_u32(a, b, vdupq_lane_u32::<LANE>(c))
13132}
13133#[doc = "Multiply-subtract long"]
13134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"]
13135#[inline]
13136#[target_feature(enable = "neon")]
13137#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
13138#[rustc_legacy_const_generics(3)]
13139#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13140pub fn vmlsl_high_laneq_u32<const LANE: i32>(
13141    a: uint64x2_t,
13142    b: uint32x4_t,
13143    c: uint32x4_t,
13144) -> uint64x2_t {
13145    static_assert_uimm_bits!(LANE, 2);
13146    vmlsl_high_u32(a, b, vdupq_laneq_u32::<LANE>(c))
13147}
13148#[doc = "Multiply-subtract long"]
13149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"]
13150#[inline]
13151#[target_feature(enable = "neon")]
13152#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
13153#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13154pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
13155    vmlsl_high_s16(a, b, vdupq_n_s16(c))
13156}
13157#[doc = "Multiply-subtract long"]
13158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"]
13159#[inline]
13160#[target_feature(enable = "neon")]
13161#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
13162#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13163pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
13164    vmlsl_high_s32(a, b, vdupq_n_s32(c))
13165}
13166#[doc = "Multiply-subtract long"]
13167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"]
13168#[inline]
13169#[target_feature(enable = "neon")]
13170#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
13171#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13172pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
13173    vmlsl_high_u16(a, b, vdupq_n_u16(c))
13174}
13175#[doc = "Multiply-subtract long"]
13176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"]
13177#[inline]
13178#[target_feature(enable = "neon")]
13179#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
13180#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13181pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
13182    vmlsl_high_u32(a, b, vdupq_n_u32(c))
13183}
13184#[doc = "Signed multiply-subtract long"]
13185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"]
13186#[inline]
13187#[target_feature(enable = "neon")]
13188#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
13189#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13190pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
13191    let b = vget_high_s8(b);
13192    let c = vget_high_s8(c);
13193    vmlsl_s8(a, b, c)
13194}
13195#[doc = "Signed multiply-subtract long"]
13196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"]
13197#[inline]
13198#[target_feature(enable = "neon")]
13199#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
13200#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13201pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
13202    let b = vget_high_s16(b);
13203    let c = vget_high_s16(c);
13204    vmlsl_s16(a, b, c)
13205}
13206#[doc = "Signed multiply-subtract long"]
13207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"]
13208#[inline]
13209#[target_feature(enable = "neon")]
13210#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
13211#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13212pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
13213    let b = vget_high_s32(b);
13214    let c = vget_high_s32(c);
13215    vmlsl_s32(a, b, c)
13216}
13217#[doc = "Unsigned multiply-subtract long"]
13218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"]
13219#[inline]
13220#[target_feature(enable = "neon")]
13221#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
13222#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13223pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
13224    let b = vget_high_u8(b);
13225    let c = vget_high_u8(c);
13226    vmlsl_u8(a, b, c)
13227}
13228#[doc = "Unsigned multiply-subtract long"]
13229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"]
13230#[inline]
13231#[target_feature(enable = "neon")]
13232#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
13233#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13234pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
13235    let b = vget_high_u16(b);
13236    let c = vget_high_u16(c);
13237    vmlsl_u16(a, b, c)
13238}
13239#[doc = "Unsigned multiply-subtract long"]
13240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"]
13241#[inline]
13242#[target_feature(enable = "neon")]
13243#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
13244#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13245pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
13246    let b = vget_high_u32(b);
13247    let c = vget_high_u32(c);
13248    vmlsl_u32(a, b, c)
13249}
13250#[doc = "Vector move"]
13251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"]
13252#[inline]
13253#[target_feature(enable = "neon")]
13254#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13255#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
13256pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
13257    let a = vget_high_s8(a);
13258    vmovl_s8(a)
13259}
13260#[doc = "Vector move"]
13261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"]
13262#[inline]
13263#[target_feature(enable = "neon")]
13264#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13265#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
13266pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
13267    let a = vget_high_s16(a);
13268    vmovl_s16(a)
13269}
13270#[doc = "Vector move"]
13271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"]
13272#[inline]
13273#[target_feature(enable = "neon")]
13274#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13275#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
13276pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
13277    let a = vget_high_s32(a);
13278    vmovl_s32(a)
13279}
13280#[doc = "Vector move"]
13281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"]
13282#[inline]
13283#[target_feature(enable = "neon")]
13284#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13285#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
13286pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
13287    let a = vget_high_u8(a);
13288    vmovl_u8(a)
13289}
13290#[doc = "Vector move"]
13291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"]
13292#[inline]
13293#[target_feature(enable = "neon")]
13294#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13295#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
13296pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
13297    let a = vget_high_u16(a);
13298    vmovl_u16(a)
13299}
13300#[doc = "Vector move"]
13301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"]
13302#[inline]
13303#[target_feature(enable = "neon")]
13304#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13305#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
13306pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
13307    let a = vget_high_u32(a);
13308    vmovl_u32(a)
13309}
13310#[doc = "Extract narrow"]
13311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"]
13312#[inline]
13313#[target_feature(enable = "neon")]
13314#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13315#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
13316pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
13317    unsafe { vcombine_s8(a, simd_cast(b)) }
13318}
13319#[doc = "Extract narrow"]
13320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"]
13321#[inline]
13322#[target_feature(enable = "neon")]
13323#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13324#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
13325pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
13326    unsafe { vcombine_s16(a, simd_cast(b)) }
13327}
13328#[doc = "Extract narrow"]
13329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"]
13330#[inline]
13331#[target_feature(enable = "neon")]
13332#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13333#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
13334pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
13335    unsafe { vcombine_s32(a, simd_cast(b)) }
13336}
13337#[doc = "Extract narrow"]
13338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"]
13339#[inline]
13340#[target_feature(enable = "neon")]
13341#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13342#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
13343pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
13344    unsafe { vcombine_u8(a, simd_cast(b)) }
13345}
13346#[doc = "Extract narrow"]
13347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"]
13348#[inline]
13349#[target_feature(enable = "neon")]
13350#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13351#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
13352pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
13353    unsafe { vcombine_u16(a, simd_cast(b)) }
13354}
13355#[doc = "Extract narrow"]
13356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"]
13357#[inline]
13358#[target_feature(enable = "neon")]
13359#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13360#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
13361pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
13362    unsafe { vcombine_u32(a, simd_cast(b)) }
13363}
13364#[doc = "Multiply"]
13365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"]
13366#[inline]
13367#[target_feature(enable = "neon")]
13368#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13369#[cfg_attr(test, assert_instr(fmul))]
13370pub fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
13371    unsafe { simd_mul(a, b) }
13372}
13373#[doc = "Multiply"]
13374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)"]
13375#[inline]
13376#[target_feature(enable = "neon")]
13377#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13378#[cfg_attr(test, assert_instr(fmul))]
13379pub fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
13380    unsafe { simd_mul(a, b) }
13381}
13382#[doc = "Floating-point multiply"]
13383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64)"]
13384#[inline]
13385#[target_feature(enable = "neon")]
13386#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13387#[rustc_legacy_const_generics(2)]
13388#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13389pub fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64x1_t {
13390    static_assert!(LANE == 0);
13391    unsafe { simd_mul(a, transmute::<f64, _>(vget_lane_f64::<LANE>(b))) }
13392}
13393#[doc = "Floating-point multiply"]
13394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f16)"]
13395#[inline]
13396#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13397#[rustc_legacy_const_generics(2)]
13398#[target_feature(enable = "neon,fp16")]
13399#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
13400#[cfg(not(target_arch = "arm64ec"))]
13401pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
13402    static_assert_uimm_bits!(LANE, 3);
13403    unsafe { simd_mul(a, vdup_laneq_f16::<LANE>(b)) }
13404}
13405#[doc = "Floating-point multiply"]
13406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"]
13407#[inline]
13408#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13409#[rustc_legacy_const_generics(2)]
13410#[target_feature(enable = "neon,fp16")]
13411#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
13412#[cfg(not(target_arch = "arm64ec"))]
13413pub fn vmulq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
13414    static_assert_uimm_bits!(LANE, 3);
13415    unsafe { simd_mul(a, vdupq_laneq_f16::<LANE>(b)) }
13416}
13417#[doc = "Floating-point multiply"]
13418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"]
13419#[inline]
13420#[target_feature(enable = "neon")]
13421#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13422#[rustc_legacy_const_generics(2)]
13423#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13424pub fn vmul_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float64x1_t {
13425    static_assert_uimm_bits!(LANE, 1);
13426    unsafe { simd_mul(a, transmute::<f64, _>(vgetq_lane_f64::<LANE>(b))) }
13427}
13428#[doc = "Vector multiply by scalar"]
13429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"]
13430#[inline]
13431#[target_feature(enable = "neon")]
13432#[cfg_attr(test, assert_instr(fmul))]
13433#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13434pub fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t {
13435    unsafe { simd_mul(a, vdup_n_f64(b)) }
13436}
13437#[doc = "Vector multiply by scalar"]
13438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)"]
13439#[inline]
13440#[target_feature(enable = "neon")]
13441#[cfg_attr(test, assert_instr(fmul))]
13442#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13443pub fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t {
13444    unsafe { simd_mul(a, vdupq_n_f64(b)) }
13445}
13446#[doc = "Floating-point multiply"]
13447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64)"]
13448#[inline]
13449#[target_feature(enable = "neon")]
13450#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13451#[rustc_legacy_const_generics(2)]
13452#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13453pub fn vmuld_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
13454    static_assert!(LANE == 0);
13455    let b: f64 = vget_lane_f64::<LANE>(b);
13456    a * b
13457}
13458#[doc = "Add"]
13459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_f16)"]
13460#[inline]
13461#[target_feature(enable = "neon,fp16")]
13462#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
13463#[cfg(not(target_arch = "arm64ec"))]
13464#[cfg_attr(test, assert_instr(fmul))]
13465pub fn vmulh_f16(a: f16, b: f16) -> f16 {
13466    a * b
13467}
13468#[doc = "Floating-point multiply"]
13469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_lane_f16)"]
13470#[inline]
13471#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13472#[rustc_legacy_const_generics(2)]
13473#[target_feature(enable = "neon,fp16")]
13474#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
13475#[cfg(not(target_arch = "arm64ec"))]
13476pub fn vmulh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
13477    static_assert_uimm_bits!(LANE, 2);
13478    let b: f16 = vget_lane_f16::<LANE>(b);
13479    a * b
13480}
13481#[doc = "Floating-point multiply"]
13482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_laneq_f16)"]
13483#[inline]
13484#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13485#[rustc_legacy_const_generics(2)]
13486#[target_feature(enable = "neon,fp16")]
13487#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
13488#[cfg(not(target_arch = "arm64ec"))]
13489pub fn vmulh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
13490    static_assert_uimm_bits!(LANE, 3);
13491    let b: f16 = vgetq_lane_f16::<LANE>(b);
13492    a * b
13493}
13494#[doc = "Multiply long"]
13495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"]
13496#[inline]
13497#[target_feature(enable = "neon")]
13498#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
13499#[rustc_legacy_const_generics(2)]
13500#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13501pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t {
13502    static_assert_uimm_bits!(LANE, 2);
13503    vmull_high_s16(a, vdupq_lane_s16::<LANE>(b))
13504}
13505#[doc = "Multiply long"]
13506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"]
13507#[inline]
13508#[target_feature(enable = "neon")]
13509#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
13510#[rustc_legacy_const_generics(2)]
13511#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13512pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t {
13513    static_assert_uimm_bits!(LANE, 3);
13514    vmull_high_s16(a, vdupq_laneq_s16::<LANE>(b))
13515}
13516#[doc = "Multiply long"]
13517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"]
13518#[inline]
13519#[target_feature(enable = "neon")]
13520#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
13521#[rustc_legacy_const_generics(2)]
13522#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13523pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t {
13524    static_assert_uimm_bits!(LANE, 1);
13525    vmull_high_s32(a, vdupq_lane_s32::<LANE>(b))
13526}
13527#[doc = "Multiply long"]
13528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"]
13529#[inline]
13530#[target_feature(enable = "neon")]
13531#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
13532#[rustc_legacy_const_generics(2)]
13533#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13534pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t {
13535    static_assert_uimm_bits!(LANE, 2);
13536    vmull_high_s32(a, vdupq_laneq_s32::<LANE>(b))
13537}
13538#[doc = "Multiply long"]
13539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"]
13540#[inline]
13541#[target_feature(enable = "neon")]
13542#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
13543#[rustc_legacy_const_generics(2)]
13544#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13545pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t {
13546    static_assert_uimm_bits!(LANE, 2);
13547    vmull_high_u16(a, vdupq_lane_u16::<LANE>(b))
13548}
13549#[doc = "Multiply long"]
13550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"]
13551#[inline]
13552#[target_feature(enable = "neon")]
13553#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
13554#[rustc_legacy_const_generics(2)]
13555#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13556pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
13557    static_assert_uimm_bits!(LANE, 3);
13558    vmull_high_u16(a, vdupq_laneq_u16::<LANE>(b))
13559}
13560#[doc = "Multiply long"]
13561#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"]
13562#[inline]
13563#[target_feature(enable = "neon")]
13564#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
13565#[rustc_legacy_const_generics(2)]
13566#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13567pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t {
13568    static_assert_uimm_bits!(LANE, 1);
13569    vmull_high_u32(a, vdupq_lane_u32::<LANE>(b))
13570}
13571#[doc = "Multiply long"]
13572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"]
13573#[inline]
13574#[target_feature(enable = "neon")]
13575#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
13576#[rustc_legacy_const_generics(2)]
13577#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13578pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
13579    static_assert_uimm_bits!(LANE, 2);
13580    vmull_high_u32(a, vdupq_laneq_u32::<LANE>(b))
13581}
13582#[doc = "Multiply long"]
13583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"]
13584#[inline]
13585#[target_feature(enable = "neon")]
13586#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
13587#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13588pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
13589    vmull_high_s16(a, vdupq_n_s16(b))
13590}
13591#[doc = "Multiply long"]
13592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"]
13593#[inline]
13594#[target_feature(enable = "neon")]
13595#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
13596#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13597pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
13598    vmull_high_s32(a, vdupq_n_s32(b))
13599}
13600#[doc = "Multiply long"]
13601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"]
13602#[inline]
13603#[target_feature(enable = "neon")]
13604#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
13605#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13606pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t {
13607    vmull_high_u16(a, vdupq_n_u16(b))
13608}
13609#[doc = "Multiply long"]
13610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"]
13611#[inline]
13612#[target_feature(enable = "neon")]
13613#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
13614#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13615pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
13616    vmull_high_u32(a, vdupq_n_u32(b))
13617}
13618#[doc = "Polynomial multiply long"]
13619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)"]
13620#[inline]
13621#[target_feature(enable = "neon,aes")]
13622#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13623#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))]
13624pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
13625    vmull_p64(vgetq_lane_p64::<1>(a), vgetq_lane_p64::<1>(b))
13626}
13627#[doc = "Polynomial multiply long"]
13628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"]
13629#[inline]
13630#[target_feature(enable = "neon")]
13631#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13632#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))]
13633pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
13634    let a = vget_high_p8(a);
13635    let b = vget_high_p8(b);
13636    vmull_p8(a, b)
13637}
13638#[doc = "Signed multiply long"]
13639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"]
13640#[inline]
13641#[target_feature(enable = "neon")]
13642#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13643#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
13644pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
13645    let a = vget_high_s8(a);
13646    let b = vget_high_s8(b);
13647    vmull_s8(a, b)
13648}
13649#[doc = "Signed multiply long"]
13650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"]
13651#[inline]
13652#[target_feature(enable = "neon")]
13653#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13654#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
13655pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
13656    let a = vget_high_s16(a);
13657    let b = vget_high_s16(b);
13658    vmull_s16(a, b)
13659}
13660#[doc = "Signed multiply long"]
13661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"]
13662#[inline]
13663#[target_feature(enable = "neon")]
13664#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13665#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
13666pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
13667    let a = vget_high_s32(a);
13668    let b = vget_high_s32(b);
13669    vmull_s32(a, b)
13670}
13671#[doc = "Unsigned multiply long"]
13672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"]
13673#[inline]
13674#[target_feature(enable = "neon")]
13675#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13676#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
13677pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
13678    let a = vget_high_u8(a);
13679    let b = vget_high_u8(b);
13680    vmull_u8(a, b)
13681}
13682#[doc = "Unsigned multiply long"]
13683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"]
13684#[inline]
13685#[target_feature(enable = "neon")]
13686#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13687#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
13688pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
13689    let a = vget_high_u16(a);
13690    let b = vget_high_u16(b);
13691    vmull_u16(a, b)
13692}
13693#[doc = "Unsigned multiply long"]
13694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"]
13695#[inline]
13696#[target_feature(enable = "neon")]
13697#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13698#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
13699pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
13700    let a = vget_high_u32(a);
13701    let b = vget_high_u32(b);
13702    vmull_u32(a, b)
13703}
13704#[doc = "Polynomial multiply long"]
13705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"]
13706#[inline]
13707#[target_feature(enable = "neon,aes")]
13708#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13709#[cfg_attr(test, assert_instr(pmull))]
13710pub fn vmull_p64(a: p64, b: p64) -> p128 {
13711    unsafe extern "unadjusted" {
13712        #[cfg_attr(
13713            any(target_arch = "aarch64", target_arch = "arm64ec"),
13714            link_name = "llvm.aarch64.neon.pmull64"
13715        )]
13716        fn _vmull_p64(a: p64, b: p64) -> int8x16_t;
13717    }
13718    unsafe { transmute(_vmull_p64(a, b)) }
13719}
13720#[doc = "Floating-point multiply"]
13721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64)"]
13722#[inline]
13723#[target_feature(enable = "neon")]
13724#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13725#[rustc_legacy_const_generics(2)]
13726#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13727pub fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t {
13728    static_assert!(LANE == 0);
13729    unsafe { simd_mul(a, vdupq_lane_f64::<LANE>(b)) }
13730}
13731#[doc = "Floating-point multiply"]
13732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"]
13733#[inline]
13734#[target_feature(enable = "neon")]
13735#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13736#[rustc_legacy_const_generics(2)]
13737#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13738pub fn vmulq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
13739    static_assert_uimm_bits!(LANE, 1);
13740    unsafe { simd_mul(a, vdupq_laneq_f64::<LANE>(b)) }
13741}
13742#[doc = "Floating-point multiply"]
13743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"]
13744#[inline]
13745#[target_feature(enable = "neon")]
13746#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13747#[rustc_legacy_const_generics(2)]
13748#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13749pub fn vmuls_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
13750    static_assert_uimm_bits!(LANE, 1);
13751    let b: f32 = vget_lane_f32::<LANE>(b);
13752    a * b
13753}
13754#[doc = "Floating-point multiply"]
13755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"]
13756#[inline]
13757#[target_feature(enable = "neon")]
13758#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13759#[rustc_legacy_const_generics(2)]
13760#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13761pub fn vmuls_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
13762    static_assert_uimm_bits!(LANE, 2);
13763    let b: f32 = vgetq_lane_f32::<LANE>(b);
13764    a * b
13765}
13766#[doc = "Floating-point multiply"]
13767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"]
13768#[inline]
13769#[target_feature(enable = "neon")]
13770#[cfg_attr(test, assert_instr(fmul, LANE = 0))]
13771#[rustc_legacy_const_generics(2)]
13772#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13773pub fn vmuld_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
13774    static_assert_uimm_bits!(LANE, 1);
13775    let b: f64 = vgetq_lane_f64::<LANE>(b);
13776    a * b
13777}
13778#[doc = "Floating-point multiply extended"]
13779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"]
13780#[inline]
13781#[target_feature(enable = "neon,fp16")]
13782#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
13783#[cfg(not(target_arch = "arm64ec"))]
13784#[cfg_attr(test, assert_instr(fmulx))]
13785pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
13786    unsafe extern "unadjusted" {
13787        #[cfg_attr(
13788            any(target_arch = "aarch64", target_arch = "arm64ec"),
13789            link_name = "llvm.aarch64.neon.fmulx.v4f16"
13790        )]
13791        fn _vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
13792    }
13793    unsafe { _vmulx_f16(a, b) }
13794}
13795#[doc = "Floating-point multiply extended"]
13796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"]
13797#[inline]
13798#[target_feature(enable = "neon,fp16")]
13799#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
13800#[cfg(not(target_arch = "arm64ec"))]
13801#[cfg_attr(test, assert_instr(fmulx))]
13802pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
13803    unsafe extern "unadjusted" {
13804        #[cfg_attr(
13805            any(target_arch = "aarch64", target_arch = "arm64ec"),
13806            link_name = "llvm.aarch64.neon.fmulx.v8f16"
13807        )]
13808        fn _vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
13809    }
13810    unsafe { _vmulxq_f16(a, b) }
13811}
13812#[doc = "Floating-point multiply extended"]
13813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)"]
13814#[inline]
13815#[target_feature(enable = "neon")]
13816#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13817#[cfg_attr(test, assert_instr(fmulx))]
13818pub fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
13819    unsafe extern "unadjusted" {
13820        #[cfg_attr(
13821            any(target_arch = "aarch64", target_arch = "arm64ec"),
13822            link_name = "llvm.aarch64.neon.fmulx.v2f32"
13823        )]
13824        fn _vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
13825    }
13826    unsafe { _vmulx_f32(a, b) }
13827}
13828#[doc = "Floating-point multiply extended"]
13829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)"]
13830#[inline]
13831#[target_feature(enable = "neon")]
13832#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13833#[cfg_attr(test, assert_instr(fmulx))]
13834pub fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
13835    unsafe extern "unadjusted" {
13836        #[cfg_attr(
13837            any(target_arch = "aarch64", target_arch = "arm64ec"),
13838            link_name = "llvm.aarch64.neon.fmulx.v4f32"
13839        )]
13840        fn _vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
13841    }
13842    unsafe { _vmulxq_f32(a, b) }
13843}
13844#[doc = "Floating-point multiply extended"]
13845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)"]
13846#[inline]
13847#[target_feature(enable = "neon")]
13848#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13849#[cfg_attr(test, assert_instr(fmulx))]
13850pub fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
13851    unsafe extern "unadjusted" {
13852        #[cfg_attr(
13853            any(target_arch = "aarch64", target_arch = "arm64ec"),
13854            link_name = "llvm.aarch64.neon.fmulx.v1f64"
13855        )]
13856        fn _vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
13857    }
13858    unsafe { _vmulx_f64(a, b) }
13859}
13860#[doc = "Floating-point multiply extended"]
13861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)"]
13862#[inline]
13863#[target_feature(enable = "neon")]
13864#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13865#[cfg_attr(test, assert_instr(fmulx))]
13866pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
13867    unsafe extern "unadjusted" {
13868        #[cfg_attr(
13869            any(target_arch = "aarch64", target_arch = "arm64ec"),
13870            link_name = "llvm.aarch64.neon.fmulx.v2f64"
13871        )]
13872        fn _vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
13873    }
13874    unsafe { _vmulxq_f64(a, b) }
13875}
13876#[doc = "Floating-point multiply extended"]
13877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f16)"]
13878#[inline]
13879#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13880#[rustc_legacy_const_generics(2)]
13881#[target_feature(enable = "neon,fp16")]
13882#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
13883#[cfg(not(target_arch = "arm64ec"))]
13884pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
13885    static_assert_uimm_bits!(LANE, 2);
13886    vmulx_f16(a, vdup_lane_f16::<LANE>(b))
13887}
13888#[doc = "Floating-point multiply extended"]
13889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"]
13890#[inline]
13891#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13892#[rustc_legacy_const_generics(2)]
13893#[target_feature(enable = "neon,fp16")]
13894#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
13895#[cfg(not(target_arch = "arm64ec"))]
13896pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float16x4_t {
13897    static_assert_uimm_bits!(LANE, 3);
13898    vmulx_f16(a, vdup_laneq_f16::<LANE>(b))
13899}
13900#[doc = "Floating-point multiply extended"]
13901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"]
13902#[inline]
13903#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13904#[rustc_legacy_const_generics(2)]
13905#[target_feature(enable = "neon,fp16")]
13906#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
13907#[cfg(not(target_arch = "arm64ec"))]
13908pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float16x8_t {
13909    static_assert_uimm_bits!(LANE, 2);
13910    vmulxq_f16(a, vdupq_lane_f16::<LANE>(b))
13911}
13912#[doc = "Floating-point multiply extended"]
13913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"]
13914#[inline]
13915#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13916#[rustc_legacy_const_generics(2)]
13917#[target_feature(enable = "neon,fp16")]
13918#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
13919#[cfg(not(target_arch = "arm64ec"))]
13920pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
13921    static_assert_uimm_bits!(LANE, 3);
13922    vmulxq_f16(a, vdupq_laneq_f16::<LANE>(b))
13923}
13924#[doc = "Floating-point multiply extended"]
13925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"]
13926#[inline]
13927#[target_feature(enable = "neon")]
13928#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13929#[rustc_legacy_const_generics(2)]
13930#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13931pub fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
13932    static_assert_uimm_bits!(LANE, 1);
13933    vmulx_f32(a, vdup_lane_f32::<LANE>(b))
13934}
13935#[doc = "Floating-point multiply extended"]
13936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"]
13937#[inline]
13938#[target_feature(enable = "neon")]
13939#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13940#[rustc_legacy_const_generics(2)]
13941#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13942pub fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
13943    static_assert_uimm_bits!(LANE, 2);
13944    vmulx_f32(a, vdup_laneq_f32::<LANE>(b))
13945}
13946#[doc = "Floating-point multiply extended"]
13947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"]
13948#[inline]
13949#[target_feature(enable = "neon")]
13950#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13951#[rustc_legacy_const_generics(2)]
13952#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13953pub fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
13954    static_assert_uimm_bits!(LANE, 1);
13955    vmulxq_f32(a, vdupq_lane_f32::<LANE>(b))
13956}
13957#[doc = "Floating-point multiply extended"]
13958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"]
13959#[inline]
13960#[target_feature(enable = "neon")]
13961#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13962#[rustc_legacy_const_generics(2)]
13963#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13964pub fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
13965    static_assert_uimm_bits!(LANE, 2);
13966    vmulxq_f32(a, vdupq_laneq_f32::<LANE>(b))
13967}
13968#[doc = "Floating-point multiply extended"]
13969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"]
13970#[inline]
13971#[target_feature(enable = "neon")]
13972#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13973#[rustc_legacy_const_generics(2)]
13974#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13975pub fn vmulxq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
13976    static_assert_uimm_bits!(LANE, 1);
13977    vmulxq_f64(a, vdupq_laneq_f64::<LANE>(b))
13978}
13979#[doc = "Floating-point multiply extended"]
13980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"]
13981#[inline]
13982#[target_feature(enable = "neon")]
13983#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13984#[rustc_legacy_const_generics(2)]
13985#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13986pub fn vmulx_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64x1_t {
13987    static_assert!(LANE == 0);
13988    unsafe { vmulx_f64(a, transmute(vget_lane_f64::<LANE>(b))) }
13989}
13990#[doc = "Floating-point multiply extended"]
13991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"]
13992#[inline]
13993#[target_feature(enable = "neon")]
13994#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
13995#[rustc_legacy_const_generics(2)]
13996#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13997pub fn vmulx_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float64x1_t {
13998    static_assert_uimm_bits!(LANE, 1);
13999    unsafe { vmulx_f64(a, transmute(vgetq_lane_f64::<LANE>(b))) }
14000}
14001#[doc = "Vector multiply by scalar"]
14002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_n_f16)"]
14003#[inline]
14004#[cfg_attr(test, assert_instr(fmulx))]
14005#[target_feature(enable = "neon,fp16")]
14006#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14007#[cfg(not(target_arch = "arm64ec"))]
14008pub fn vmulx_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
14009    vmulx_f16(a, vdup_n_f16(b))
14010}
14011#[doc = "Vector multiply by scalar"]
14012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_n_f16)"]
14013#[inline]
14014#[cfg_attr(test, assert_instr(fmulx))]
14015#[target_feature(enable = "neon,fp16")]
14016#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14017#[cfg(not(target_arch = "arm64ec"))]
14018pub fn vmulxq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
14019    vmulxq_f16(a, vdupq_n_f16(b))
14020}
14021#[doc = "Floating-point multiply extended"]
14022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64)"]
14023#[inline]
14024#[target_feature(enable = "neon")]
14025#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14026#[cfg_attr(test, assert_instr(fmulx))]
14027pub fn vmulxd_f64(a: f64, b: f64) -> f64 {
14028    unsafe extern "unadjusted" {
14029        #[cfg_attr(
14030            any(target_arch = "aarch64", target_arch = "arm64ec"),
14031            link_name = "llvm.aarch64.neon.fmulx.f64"
14032        )]
14033        fn _vmulxd_f64(a: f64, b: f64) -> f64;
14034    }
14035    unsafe { _vmulxd_f64(a, b) }
14036}
14037#[doc = "Floating-point multiply extended"]
14038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)"]
14039#[inline]
14040#[target_feature(enable = "neon")]
14041#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14042#[cfg_attr(test, assert_instr(fmulx))]
14043pub fn vmulxs_f32(a: f32, b: f32) -> f32 {
14044    unsafe extern "unadjusted" {
14045        #[cfg_attr(
14046            any(target_arch = "aarch64", target_arch = "arm64ec"),
14047            link_name = "llvm.aarch64.neon.fmulx.f32"
14048        )]
14049        fn _vmulxs_f32(a: f32, b: f32) -> f32;
14050    }
14051    unsafe { _vmulxs_f32(a, b) }
14052}
14053#[doc = "Floating-point multiply extended"]
14054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64)"]
14055#[inline]
14056#[target_feature(enable = "neon")]
14057#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
14058#[rustc_legacy_const_generics(2)]
14059#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14060pub fn vmulxd_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
14061    static_assert!(LANE == 0);
14062    vmulxd_f64(a, vget_lane_f64::<LANE>(b))
14063}
14064#[doc = "Floating-point multiply extended"]
14065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"]
14066#[inline]
14067#[target_feature(enable = "neon")]
14068#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
14069#[rustc_legacy_const_generics(2)]
14070#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14071pub fn vmulxd_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
14072    static_assert_uimm_bits!(LANE, 1);
14073    vmulxd_f64(a, vgetq_lane_f64::<LANE>(b))
14074}
14075#[doc = "Floating-point multiply extended"]
14076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"]
14077#[inline]
14078#[target_feature(enable = "neon")]
14079#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
14080#[rustc_legacy_const_generics(2)]
14081#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14082pub fn vmulxs_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
14083    static_assert_uimm_bits!(LANE, 1);
14084    vmulxs_f32(a, vget_lane_f32::<LANE>(b))
14085}
14086#[doc = "Floating-point multiply extended"]
14087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"]
14088#[inline]
14089#[target_feature(enable = "neon")]
14090#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
14091#[rustc_legacy_const_generics(2)]
14092#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14093pub fn vmulxs_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
14094    static_assert_uimm_bits!(LANE, 2);
14095    vmulxs_f32(a, vgetq_lane_f32::<LANE>(b))
14096}
14097#[doc = "Floating-point multiply extended"]
14098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_f16)"]
14099#[inline]
14100#[target_feature(enable = "neon,fp16")]
14101#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14102#[cfg(not(target_arch = "arm64ec"))]
14103#[cfg_attr(test, assert_instr(fmulx))]
14104pub fn vmulxh_f16(a: f16, b: f16) -> f16 {
14105    unsafe extern "unadjusted" {
14106        #[cfg_attr(
14107            any(target_arch = "aarch64", target_arch = "arm64ec"),
14108            link_name = "llvm.aarch64.neon.fmulx.f16"
14109        )]
14110        fn _vmulxh_f16(a: f16, b: f16) -> f16;
14111    }
14112    unsafe { _vmulxh_f16(a, b) }
14113}
14114#[doc = "Floating-point multiply extended"]
14115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_lane_f16)"]
14116#[inline]
14117#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
14118#[rustc_legacy_const_generics(2)]
14119#[target_feature(enable = "neon,fp16")]
14120#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14121#[cfg(not(target_arch = "arm64ec"))]
14122pub fn vmulxh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
14123    static_assert_uimm_bits!(LANE, 2);
14124    vmulxh_f16(a, vget_lane_f16::<LANE>(b))
14125}
14126#[doc = "Floating-point multiply extended"]
14127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_laneq_f16)"]
14128#[inline]
14129#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
14130#[rustc_legacy_const_generics(2)]
14131#[target_feature(enable = "neon,fp16")]
14132#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14133#[cfg(not(target_arch = "arm64ec"))]
14134pub fn vmulxh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
14135    static_assert_uimm_bits!(LANE, 3);
14136    vmulxh_f16(a, vgetq_lane_f16::<LANE>(b))
14137}
14138#[doc = "Floating-point multiply extended"]
14139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"]
14140#[inline]
14141#[target_feature(enable = "neon")]
14142#[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
14143#[rustc_legacy_const_generics(2)]
14144#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14145pub fn vmulxq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t {
14146    static_assert!(LANE == 0);
14147    vmulxq_f64(a, vdupq_lane_f64::<LANE>(b))
14148}
14149#[doc = "Negate"]
14150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"]
14151#[inline]
14152#[target_feature(enable = "neon")]
14153#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14154#[cfg_attr(test, assert_instr(fneg))]
14155pub fn vneg_f64(a: float64x1_t) -> float64x1_t {
14156    unsafe { simd_neg(a) }
14157}
14158#[doc = "Negate"]
14159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)"]
14160#[inline]
14161#[target_feature(enable = "neon")]
14162#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14163#[cfg_attr(test, assert_instr(fneg))]
14164pub fn vnegq_f64(a: float64x2_t) -> float64x2_t {
14165    unsafe { simd_neg(a) }
14166}
14167#[doc = "Negate"]
14168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)"]
14169#[inline]
14170#[target_feature(enable = "neon")]
14171#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14172#[cfg_attr(test, assert_instr(neg))]
14173pub fn vneg_s64(a: int64x1_t) -> int64x1_t {
14174    unsafe { simd_neg(a) }
14175}
14176#[doc = "Negate"]
14177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)"]
14178#[inline]
14179#[target_feature(enable = "neon")]
14180#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14181#[cfg_attr(test, assert_instr(neg))]
14182pub fn vnegq_s64(a: int64x2_t) -> int64x2_t {
14183    unsafe { simd_neg(a) }
14184}
14185#[doc = "Negate"]
14186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64)"]
14187#[inline]
14188#[target_feature(enable = "neon")]
14189#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14190#[cfg_attr(test, assert_instr(neg))]
14191pub fn vnegd_s64(a: i64) -> i64 {
14192    a.wrapping_neg()
14193}
14194#[doc = "Negate"]
14195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegh_f16)"]
14196#[inline]
14197#[target_feature(enable = "neon,fp16")]
14198#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14199#[cfg(not(target_arch = "arm64ec"))]
14200#[cfg_attr(test, assert_instr(fneg))]
14201pub fn vnegh_f16(a: f16) -> f16 {
14202    -a
14203}
14204#[doc = "Floating-point add pairwise"]
14205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)"]
14206#[inline]
14207#[target_feature(enable = "neon")]
14208#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14209#[cfg_attr(test, assert_instr(nop))]
14210pub fn vpaddd_f64(a: float64x2_t) -> f64 {
14211    let a1: f64 = vgetq_lane_f64::<0>(a);
14212    let a2: f64 = vgetq_lane_f64::<1>(a);
14213    a1 + a2
14214}
14215#[doc = "Floating-point add pairwise"]
14216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"]
14217#[inline]
14218#[target_feature(enable = "neon")]
14219#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14220#[cfg_attr(test, assert_instr(nop))]
14221pub fn vpadds_f32(a: float32x2_t) -> f32 {
14222    let a1: f32 = vget_lane_f32::<0>(a);
14223    let a2: f32 = vget_lane_f32::<1>(a);
14224    a1 + a2
14225}
14226#[doc = "Add pairwise"]
14227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"]
14228#[inline]
14229#[target_feature(enable = "neon")]
14230#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14231#[cfg_attr(test, assert_instr(addp))]
14232pub fn vpaddd_s64(a: int64x2_t) -> i64 {
14233    unsafe { simd_reduce_add_ordered(a, 0) }
14234}
14235#[doc = "Add pairwise"]
14236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)"]
14237#[inline]
14238#[target_feature(enable = "neon")]
14239#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14240#[cfg_attr(test, assert_instr(addp))]
14241pub fn vpaddd_u64(a: uint64x2_t) -> u64 {
14242    unsafe { simd_reduce_add_ordered(a, 0) }
14243}
14244#[doc = "Floating-point add pairwise"]
14245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"]
14246#[inline]
14247#[cfg(target_endian = "little")]
14248#[target_feature(enable = "neon,fp16")]
14249#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14250#[cfg(not(target_arch = "arm64ec"))]
14251#[cfg_attr(test, assert_instr(faddp))]
14252pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
14253    unsafe {
14254        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>());
14255        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>());
14256        simd_add(even, odd)
14257    }
14258}
14259#[doc = "Floating-point add pairwise"]
14260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"]
14261#[inline]
14262#[cfg(target_endian = "big")]
14263#[target_feature(enable = "neon,fp16")]
14264#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14265#[cfg(not(target_arch = "arm64ec"))]
14266#[cfg_attr(test, assert_instr(faddp))]
14267pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
14268    unsafe {
14269        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
14270        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
14271        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>());
14272        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>());
14273        let ret_val: float16x8_t = simd_add(even, odd);
14274        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
14275    }
14276}
14277#[doc = "Floating-point add pairwise"]
14278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"]
14279#[inline]
14280#[cfg(target_endian = "little")]
14281#[target_feature(enable = "neon")]
14282#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14283#[cfg_attr(test, assert_instr(faddp))]
14284pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
14285    unsafe {
14286        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>());
14287        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>());
14288        simd_add(even, odd)
14289    }
14290}
14291#[doc = "Floating-point add pairwise"]
14292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"]
14293#[inline]
14294#[cfg(target_endian = "big")]
14295#[target_feature(enable = "neon")]
14296#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14297#[cfg_attr(test, assert_instr(faddp))]
14298pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
14299    unsafe {
14300        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
14301        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
14302        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>());
14303        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>());
14304        let ret_val: float32x4_t = simd_add(even, odd);
14305        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14306    }
14307}
14308#[doc = "Floating-point add pairwise"]
14309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"]
14310#[inline]
14311#[cfg(target_endian = "little")]
14312#[target_feature(enable = "neon")]
14313#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14314#[cfg_attr(test, assert_instr(faddp))]
14315pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
14316    unsafe {
14317        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>());
14318        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>());
14319        simd_add(even, odd)
14320    }
14321}
14322#[doc = "Floating-point add pairwise"]
14323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"]
14324#[inline]
14325#[cfg(target_endian = "big")]
14326#[target_feature(enable = "neon")]
14327#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14328#[cfg_attr(test, assert_instr(faddp))]
14329pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
14330    unsafe {
14331        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
14332        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
14333        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>());
14334        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>());
14335        let ret_val: float64x2_t = simd_add(even, odd);
14336        simd_shuffle!(ret_val, ret_val, [1, 0])
14337    }
14338}
14339#[doc = "Add Pairwise"]
14340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"]
14341#[inline]
14342#[cfg(target_endian = "little")]
14343#[target_feature(enable = "neon")]
14344#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14345#[cfg_attr(test, assert_instr(addp))]
14346pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
14347    unsafe {
14348        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>());
14349        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>());
14350        simd_add(even, odd)
14351    }
14352}
14353#[doc = "Add Pairwise"]
14354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"]
14355#[inline]
14356#[cfg(target_endian = "big")]
14357#[target_feature(enable = "neon")]
14358#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14359#[cfg_attr(test, assert_instr(addp))]
14360pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
14361    unsafe {
14362        let a: int8x16_t =
14363            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
14364        let b: int8x16_t =
14365            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
14366        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>());
14367        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>());
14368        let ret_val: int8x16_t = simd_add(even, odd);
14369        simd_shuffle!(
14370            ret_val,
14371            ret_val,
14372            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
14373        )
14374    }
14375}
14376#[doc = "Add Pairwise"]
14377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"]
14378#[inline]
14379#[cfg(target_endian = "little")]
14380#[target_feature(enable = "neon")]
14381#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14382#[cfg_attr(test, assert_instr(addp))]
14383pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
14384    unsafe {
14385        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>());
14386        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>());
14387        simd_add(even, odd)
14388    }
14389}
14390#[doc = "Add Pairwise"]
14391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"]
14392#[inline]
14393#[cfg(target_endian = "big")]
14394#[target_feature(enable = "neon")]
14395#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14396#[cfg_attr(test, assert_instr(addp))]
14397pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
14398    unsafe {
14399        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
14400        let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
14401        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>());
14402        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>());
14403        let ret_val: int16x8_t = simd_add(even, odd);
14404        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
14405    }
14406}
14407#[doc = "Add Pairwise"]
14408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"]
14409#[inline]
14410#[cfg(target_endian = "little")]
14411#[target_feature(enable = "neon")]
14412#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14413#[cfg_attr(test, assert_instr(addp))]
14414pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
14415    unsafe {
14416        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>());
14417        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>());
14418        simd_add(even, odd)
14419    }
14420}
14421#[doc = "Add Pairwise"]
14422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"]
14423#[inline]
14424#[cfg(target_endian = "big")]
14425#[target_feature(enable = "neon")]
14426#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14427#[cfg_attr(test, assert_instr(addp))]
14428pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
14429    unsafe {
14430        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
14431        let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
14432        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>());
14433        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>());
14434        let ret_val: int32x4_t = simd_add(even, odd);
14435        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14436    }
14437}
14438#[doc = "Add Pairwise"]
14439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"]
14440#[inline]
14441#[cfg(target_endian = "little")]
14442#[target_feature(enable = "neon")]
14443#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14444#[cfg_attr(test, assert_instr(addp))]
14445pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
14446    unsafe {
14447        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>());
14448        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>());
14449        simd_add(even, odd)
14450    }
14451}
14452#[doc = "Add Pairwise"]
14453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"]
14454#[inline]
14455#[cfg(target_endian = "big")]
14456#[target_feature(enable = "neon")]
14457#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14458#[cfg_attr(test, assert_instr(addp))]
14459pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
14460    unsafe {
14461        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
14462        let b: int64x2_t = simd_shuffle!(b, b, [1, 0]);
14463        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>());
14464        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>());
14465        let ret_val: int64x2_t = simd_add(even, odd);
14466        simd_shuffle!(ret_val, ret_val, [1, 0])
14467    }
14468}
14469#[doc = "Add Pairwise"]
14470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"]
14471#[inline]
14472#[cfg(target_endian = "little")]
14473#[target_feature(enable = "neon")]
14474#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14475#[cfg_attr(test, assert_instr(addp))]
14476pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
14477    unsafe {
14478        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>());
14479        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>());
14480        simd_add(even, odd)
14481    }
14482}
14483#[doc = "Add Pairwise"]
14484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"]
14485#[inline]
14486#[cfg(target_endian = "big")]
14487#[target_feature(enable = "neon")]
14488#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14489#[cfg_attr(test, assert_instr(addp))]
14490pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
14491    unsafe {
14492        let a: uint8x16_t =
14493            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
14494        let b: uint8x16_t =
14495            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
14496        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>());
14497        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>());
14498        let ret_val: uint8x16_t = simd_add(even, odd);
14499        simd_shuffle!(
14500            ret_val,
14501            ret_val,
14502            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
14503        )
14504    }
14505}
14506#[doc = "Add Pairwise"]
14507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"]
14508#[inline]
14509#[cfg(target_endian = "little")]
14510#[target_feature(enable = "neon")]
14511#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14512#[cfg_attr(test, assert_instr(addp))]
14513pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
14514    unsafe {
14515        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>());
14516        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>());
14517        simd_add(even, odd)
14518    }
14519}
14520#[doc = "Add Pairwise"]
14521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"]
14522#[inline]
14523#[cfg(target_endian = "big")]
14524#[target_feature(enable = "neon")]
14525#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14526#[cfg_attr(test, assert_instr(addp))]
14527pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
14528    unsafe {
14529        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
14530        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
14531        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>());
14532        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>());
14533        let ret_val: uint16x8_t = simd_add(even, odd);
14534        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
14535    }
14536}
14537#[doc = "Add Pairwise"]
14538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"]
14539#[inline]
14540#[cfg(target_endian = "little")]
14541#[target_feature(enable = "neon")]
14542#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14543#[cfg_attr(test, assert_instr(addp))]
14544pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
14545    unsafe {
14546        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>());
14547        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>());
14548        simd_add(even, odd)
14549    }
14550}
14551#[doc = "Add Pairwise"]
14552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"]
14553#[inline]
14554#[cfg(target_endian = "big")]
14555#[target_feature(enable = "neon")]
14556#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14557#[cfg_attr(test, assert_instr(addp))]
14558pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
14559    unsafe {
14560        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
14561        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
14562        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>());
14563        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>());
14564        let ret_val: uint32x4_t = simd_add(even, odd);
14565        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14566    }
14567}
14568#[doc = "Add Pairwise"]
14569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"]
14570#[inline]
14571#[cfg(target_endian = "little")]
14572#[target_feature(enable = "neon")]
14573#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14574#[cfg_attr(test, assert_instr(addp))]
14575pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
14576    unsafe {
14577        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>());
14578        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>());
14579        simd_add(even, odd)
14580    }
14581}
14582#[doc = "Add Pairwise"]
14583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"]
14584#[inline]
14585#[cfg(target_endian = "big")]
14586#[target_feature(enable = "neon")]
14587#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14588#[cfg_attr(test, assert_instr(addp))]
14589pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
14590    unsafe {
14591        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
14592        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
14593        let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>());
14594        let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>());
14595        let ret_val: uint64x2_t = simd_add(even, odd);
14596        simd_shuffle!(ret_val, ret_val, [1, 0])
14597    }
14598}
14599#[doc = "Floating-point add pairwise"]
14600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"]
14601#[inline]
14602#[cfg(target_endian = "little")]
14603#[target_feature(enable = "neon,fp16")]
14604#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14605#[cfg(not(target_arch = "arm64ec"))]
14606#[cfg_attr(test, assert_instr(fmaxp))]
14607pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
14608    unsafe extern "unadjusted" {
14609        #[cfg_attr(
14610            any(target_arch = "aarch64", target_arch = "arm64ec"),
14611            link_name = "llvm.aarch64.neon.fmaxp.v4f16"
14612        )]
14613        fn _vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
14614    }
14615    unsafe { _vpmax_f16(a, b) }
14616}
14617#[doc = "Floating-point add pairwise"]
14618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"]
14619#[inline]
14620#[cfg(target_endian = "big")]
14621#[target_feature(enable = "neon,fp16")]
14622#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14623#[cfg(not(target_arch = "arm64ec"))]
14624#[cfg_attr(test, assert_instr(fmaxp))]
14625pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
14626    unsafe extern "unadjusted" {
14627        #[cfg_attr(
14628            any(target_arch = "aarch64", target_arch = "arm64ec"),
14629            link_name = "llvm.aarch64.neon.fmaxp.v4f16"
14630        )]
14631        fn _vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
14632    }
14633    unsafe {
14634        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
14635        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
14636        let ret_val: float16x4_t = _vpmax_f16(a, b);
14637        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14638    }
14639}
14640#[doc = "Floating-point add pairwise"]
14641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"]
14642#[inline]
14643#[cfg(target_endian = "little")]
14644#[target_feature(enable = "neon,fp16")]
14645#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14646#[cfg(not(target_arch = "arm64ec"))]
14647#[cfg_attr(test, assert_instr(fmaxp))]
14648pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
14649    unsafe extern "unadjusted" {
14650        #[cfg_attr(
14651            any(target_arch = "aarch64", target_arch = "arm64ec"),
14652            link_name = "llvm.aarch64.neon.fmaxp.v8f16"
14653        )]
14654        fn _vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
14655    }
14656    unsafe { _vpmaxq_f16(a, b) }
14657}
14658#[doc = "Floating-point add pairwise"]
14659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"]
14660#[inline]
14661#[cfg(target_endian = "big")]
14662#[target_feature(enable = "neon,fp16")]
14663#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14664#[cfg(not(target_arch = "arm64ec"))]
14665#[cfg_attr(test, assert_instr(fmaxp))]
14666pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
14667    unsafe extern "unadjusted" {
14668        #[cfg_attr(
14669            any(target_arch = "aarch64", target_arch = "arm64ec"),
14670            link_name = "llvm.aarch64.neon.fmaxp.v8f16"
14671        )]
14672        fn _vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
14673    }
14674    unsafe {
14675        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
14676        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
14677        let ret_val: float16x8_t = _vpmaxq_f16(a, b);
14678        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
14679    }
14680}
14681#[doc = "Floating-point add pairwise"]
14682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"]
14683#[inline]
14684#[cfg(target_endian = "little")]
14685#[target_feature(enable = "neon,fp16")]
14686#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14687#[cfg(not(target_arch = "arm64ec"))]
14688#[cfg_attr(test, assert_instr(fmaxnmp))]
14689pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
14690    unsafe extern "unadjusted" {
14691        #[cfg_attr(
14692            any(target_arch = "aarch64", target_arch = "arm64ec"),
14693            link_name = "llvm.aarch64.neon.fmaxnmp.v4f16"
14694        )]
14695        fn _vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
14696    }
14697    unsafe { _vpmaxnm_f16(a, b) }
14698}
14699#[doc = "Floating-point add pairwise"]
14700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"]
14701#[inline]
14702#[cfg(target_endian = "big")]
14703#[target_feature(enable = "neon,fp16")]
14704#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14705#[cfg(not(target_arch = "arm64ec"))]
14706#[cfg_attr(test, assert_instr(fmaxnmp))]
14707pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
14708    unsafe extern "unadjusted" {
14709        #[cfg_attr(
14710            any(target_arch = "aarch64", target_arch = "arm64ec"),
14711            link_name = "llvm.aarch64.neon.fmaxnmp.v4f16"
14712        )]
14713        fn _vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
14714    }
14715    unsafe {
14716        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
14717        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
14718        let ret_val: float16x4_t = _vpmaxnm_f16(a, b);
14719        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14720    }
14721}
14722#[doc = "Floating-point add pairwise"]
14723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"]
14724#[inline]
14725#[cfg(target_endian = "little")]
14726#[target_feature(enable = "neon,fp16")]
14727#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14728#[cfg(not(target_arch = "arm64ec"))]
14729#[cfg_attr(test, assert_instr(fmaxnmp))]
14730pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
14731    unsafe extern "unadjusted" {
14732        #[cfg_attr(
14733            any(target_arch = "aarch64", target_arch = "arm64ec"),
14734            link_name = "llvm.aarch64.neon.fmaxnmp.v8f16"
14735        )]
14736        fn _vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
14737    }
14738    unsafe { _vpmaxnmq_f16(a, b) }
14739}
14740#[doc = "Floating-point add pairwise"]
14741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"]
14742#[inline]
14743#[cfg(target_endian = "big")]
14744#[target_feature(enable = "neon,fp16")]
14745#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
14746#[cfg(not(target_arch = "arm64ec"))]
14747#[cfg_attr(test, assert_instr(fmaxnmp))]
14748pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
14749    unsafe extern "unadjusted" {
14750        #[cfg_attr(
14751            any(target_arch = "aarch64", target_arch = "arm64ec"),
14752            link_name = "llvm.aarch64.neon.fmaxnmp.v8f16"
14753        )]
14754        fn _vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
14755    }
14756    unsafe {
14757        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
14758        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
14759        let ret_val: float16x8_t = _vpmaxnmq_f16(a, b);
14760        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
14761    }
14762}
14763#[doc = "Floating-point Maximum Number Pairwise (vector)."]
14764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"]
14765#[inline]
14766#[cfg(target_endian = "little")]
14767#[target_feature(enable = "neon")]
14768#[cfg_attr(test, assert_instr(fmaxnmp))]
14769#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14770pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
14771    unsafe extern "unadjusted" {
14772        #[cfg_attr(
14773            any(target_arch = "aarch64", target_arch = "arm64ec"),
14774            link_name = "llvm.aarch64.neon.fmaxnmp.v2f32"
14775        )]
14776        fn _vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
14777    }
14778    unsafe { _vpmaxnm_f32(a, b) }
14779}
14780#[doc = "Floating-point Maximum Number Pairwise (vector)."]
14781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"]
14782#[inline]
14783#[cfg(target_endian = "big")]
14784#[target_feature(enable = "neon")]
14785#[cfg_attr(test, assert_instr(fmaxnmp))]
14786#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14787pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
14788    unsafe extern "unadjusted" {
14789        #[cfg_attr(
14790            any(target_arch = "aarch64", target_arch = "arm64ec"),
14791            link_name = "llvm.aarch64.neon.fmaxnmp.v2f32"
14792        )]
14793        fn _vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
14794    }
14795    unsafe {
14796        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
14797        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
14798        let ret_val: float32x2_t = _vpmaxnm_f32(a, b);
14799        simd_shuffle!(ret_val, ret_val, [1, 0])
14800    }
14801}
14802#[doc = "Floating-point Maximum Number Pairwise (vector)."]
14803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"]
14804#[inline]
14805#[cfg(target_endian = "little")]
14806#[target_feature(enable = "neon")]
14807#[cfg_attr(test, assert_instr(fmaxnmp))]
14808#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14809pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
14810    unsafe extern "unadjusted" {
14811        #[cfg_attr(
14812            any(target_arch = "aarch64", target_arch = "arm64ec"),
14813            link_name = "llvm.aarch64.neon.fmaxnmp.v4f32"
14814        )]
14815        fn _vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
14816    }
14817    unsafe { _vpmaxnmq_f32(a, b) }
14818}
14819#[doc = "Floating-point Maximum Number Pairwise (vector)."]
14820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"]
14821#[inline]
14822#[cfg(target_endian = "big")]
14823#[target_feature(enable = "neon")]
14824#[cfg_attr(test, assert_instr(fmaxnmp))]
14825#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14826pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
14827    unsafe extern "unadjusted" {
14828        #[cfg_attr(
14829            any(target_arch = "aarch64", target_arch = "arm64ec"),
14830            link_name = "llvm.aarch64.neon.fmaxnmp.v4f32"
14831        )]
14832        fn _vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
14833    }
14834    unsafe {
14835        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
14836        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
14837        let ret_val: float32x4_t = _vpmaxnmq_f32(a, b);
14838        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14839    }
14840}
14841#[doc = "Floating-point Maximum Number Pairwise (vector)."]
14842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"]
14843#[inline]
14844#[cfg(target_endian = "little")]
14845#[target_feature(enable = "neon")]
14846#[cfg_attr(test, assert_instr(fmaxnmp))]
14847#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14848pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
14849    unsafe extern "unadjusted" {
14850        #[cfg_attr(
14851            any(target_arch = "aarch64", target_arch = "arm64ec"),
14852            link_name = "llvm.aarch64.neon.fmaxnmp.v2f64"
14853        )]
14854        fn _vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
14855    }
14856    unsafe { _vpmaxnmq_f64(a, b) }
14857}
14858#[doc = "Floating-point Maximum Number Pairwise (vector)."]
14859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"]
14860#[inline]
14861#[cfg(target_endian = "big")]
14862#[target_feature(enable = "neon")]
14863#[cfg_attr(test, assert_instr(fmaxnmp))]
14864#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14865pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
14866    unsafe extern "unadjusted" {
14867        #[cfg_attr(
14868            any(target_arch = "aarch64", target_arch = "arm64ec"),
14869            link_name = "llvm.aarch64.neon.fmaxnmp.v2f64"
14870        )]
14871        fn _vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
14872    }
14873    unsafe {
14874        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
14875        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
14876        let ret_val: float64x2_t = _vpmaxnmq_f64(a, b);
14877        simd_shuffle!(ret_val, ret_val, [1, 0])
14878    }
14879}
14880#[doc = "Floating-point maximum number pairwise"]
14881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"]
14882#[inline]
14883#[cfg(target_endian = "little")]
14884#[target_feature(enable = "neon")]
14885#[cfg_attr(test, assert_instr(fmaxnmp))]
14886#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14887pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 {
14888    unsafe extern "unadjusted" {
14889        #[cfg_attr(
14890            any(target_arch = "aarch64", target_arch = "arm64ec"),
14891            link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64"
14892        )]
14893        fn _vpmaxnmqd_f64(a: float64x2_t) -> f64;
14894    }
14895    unsafe { _vpmaxnmqd_f64(a) }
14896}
14897#[doc = "Floating-point maximum number pairwise"]
14898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"]
14899#[inline]
14900#[cfg(target_endian = "big")]
14901#[target_feature(enable = "neon")]
14902#[cfg_attr(test, assert_instr(fmaxnmp))]
14903#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14904pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 {
14905    unsafe extern "unadjusted" {
14906        #[cfg_attr(
14907            any(target_arch = "aarch64", target_arch = "arm64ec"),
14908            link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64"
14909        )]
14910        fn _vpmaxnmqd_f64(a: float64x2_t) -> f64;
14911    }
14912    unsafe {
14913        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
14914        _vpmaxnmqd_f64(a)
14915    }
14916}
14917#[doc = "Floating-point maximum number pairwise"]
14918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"]
14919#[inline]
14920#[cfg(target_endian = "little")]
14921#[target_feature(enable = "neon")]
14922#[cfg_attr(test, assert_instr(fmaxnmp))]
14923#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14924pub fn vpmaxnms_f32(a: float32x2_t) -> f32 {
14925    unsafe extern "unadjusted" {
14926        #[cfg_attr(
14927            any(target_arch = "aarch64", target_arch = "arm64ec"),
14928            link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32"
14929        )]
14930        fn _vpmaxnms_f32(a: float32x2_t) -> f32;
14931    }
14932    unsafe { _vpmaxnms_f32(a) }
14933}
14934#[doc = "Floating-point maximum number pairwise"]
14935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"]
14936#[inline]
14937#[cfg(target_endian = "big")]
14938#[target_feature(enable = "neon")]
14939#[cfg_attr(test, assert_instr(fmaxnmp))]
14940#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14941pub fn vpmaxnms_f32(a: float32x2_t) -> f32 {
14942    unsafe extern "unadjusted" {
14943        #[cfg_attr(
14944            any(target_arch = "aarch64", target_arch = "arm64ec"),
14945            link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32"
14946        )]
14947        fn _vpmaxnms_f32(a: float32x2_t) -> f32;
14948    }
14949    unsafe {
14950        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
14951        _vpmaxnms_f32(a)
14952    }
14953}
14954#[doc = "Folding maximum of adjacent pairs"]
14955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"]
14956#[inline]
14957#[cfg(target_endian = "little")]
14958#[target_feature(enable = "neon")]
14959#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14960#[cfg_attr(test, assert_instr(fmaxp))]
14961pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
14962    unsafe extern "unadjusted" {
14963        #[cfg_attr(
14964            any(target_arch = "aarch64", target_arch = "arm64ec"),
14965            link_name = "llvm.aarch64.neon.fmaxp.v4f32"
14966        )]
14967        fn _vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
14968    }
14969    unsafe { _vpmaxq_f32(a, b) }
14970}
14971#[doc = "Folding maximum of adjacent pairs"]
14972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"]
14973#[inline]
14974#[cfg(target_endian = "big")]
14975#[target_feature(enable = "neon")]
14976#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14977#[cfg_attr(test, assert_instr(fmaxp))]
14978pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
14979    unsafe extern "unadjusted" {
14980        #[cfg_attr(
14981            any(target_arch = "aarch64", target_arch = "arm64ec"),
14982            link_name = "llvm.aarch64.neon.fmaxp.v4f32"
14983        )]
14984        fn _vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
14985    }
14986    unsafe {
14987        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
14988        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
14989        let ret_val: float32x4_t = _vpmaxq_f32(a, b);
14990        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14991    }
14992}
14993#[doc = "Folding maximum of adjacent pairs"]
14994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"]
14995#[inline]
14996#[cfg(target_endian = "little")]
14997#[target_feature(enable = "neon")]
14998#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14999#[cfg_attr(test, assert_instr(fmaxp))]
15000pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
15001    unsafe extern "unadjusted" {
15002        #[cfg_attr(
15003            any(target_arch = "aarch64", target_arch = "arm64ec"),
15004            link_name = "llvm.aarch64.neon.fmaxp.v2f64"
15005        )]
15006        fn _vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
15007    }
15008    unsafe { _vpmaxq_f64(a, b) }
15009}
15010#[doc = "Folding maximum of adjacent pairs"]
15011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"]
15012#[inline]
15013#[cfg(target_endian = "big")]
15014#[target_feature(enable = "neon")]
15015#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15016#[cfg_attr(test, assert_instr(fmaxp))]
15017pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
15018    unsafe extern "unadjusted" {
15019        #[cfg_attr(
15020            any(target_arch = "aarch64", target_arch = "arm64ec"),
15021            link_name = "llvm.aarch64.neon.fmaxp.v2f64"
15022        )]
15023        fn _vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
15024    }
15025    unsafe {
15026        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
15027        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
15028        let ret_val: float64x2_t = _vpmaxq_f64(a, b);
15029        simd_shuffle!(ret_val, ret_val, [1, 0])
15030    }
15031}
15032#[doc = "Folding maximum of adjacent pairs"]
15033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"]
15034#[inline]
15035#[cfg(target_endian = "little")]
15036#[target_feature(enable = "neon")]
15037#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15038#[cfg_attr(test, assert_instr(smaxp))]
15039pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
15040    unsafe extern "unadjusted" {
15041        #[cfg_attr(
15042            any(target_arch = "aarch64", target_arch = "arm64ec"),
15043            link_name = "llvm.aarch64.neon.smaxp.v16i8"
15044        )]
15045        fn _vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
15046    }
15047    unsafe { _vpmaxq_s8(a, b) }
15048}
15049#[doc = "Folding maximum of adjacent pairs"]
15050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"]
15051#[inline]
15052#[cfg(target_endian = "big")]
15053#[target_feature(enable = "neon")]
15054#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15055#[cfg_attr(test, assert_instr(smaxp))]
15056pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
15057    unsafe extern "unadjusted" {
15058        #[cfg_attr(
15059            any(target_arch = "aarch64", target_arch = "arm64ec"),
15060            link_name = "llvm.aarch64.neon.smaxp.v16i8"
15061        )]
15062        fn _vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
15063    }
15064    unsafe {
15065        let a: int8x16_t =
15066            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
15067        let b: int8x16_t =
15068            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
15069        let ret_val: int8x16_t = _vpmaxq_s8(a, b);
15070        simd_shuffle!(
15071            ret_val,
15072            ret_val,
15073            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15074        )
15075    }
15076}
15077#[doc = "Folding maximum of adjacent pairs"]
15078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"]
15079#[inline]
15080#[cfg(target_endian = "little")]
15081#[target_feature(enable = "neon")]
15082#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15083#[cfg_attr(test, assert_instr(smaxp))]
15084pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
15085    unsafe extern "unadjusted" {
15086        #[cfg_attr(
15087            any(target_arch = "aarch64", target_arch = "arm64ec"),
15088            link_name = "llvm.aarch64.neon.smaxp.v8i16"
15089        )]
15090        fn _vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
15091    }
15092    unsafe { _vpmaxq_s16(a, b) }
15093}
15094#[doc = "Folding maximum of adjacent pairs"]
15095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"]
15096#[inline]
15097#[cfg(target_endian = "big")]
15098#[target_feature(enable = "neon")]
15099#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15100#[cfg_attr(test, assert_instr(smaxp))]
15101pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
15102    unsafe extern "unadjusted" {
15103        #[cfg_attr(
15104            any(target_arch = "aarch64", target_arch = "arm64ec"),
15105            link_name = "llvm.aarch64.neon.smaxp.v8i16"
15106        )]
15107        fn _vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
15108    }
15109    unsafe {
15110        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
15111        let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
15112        let ret_val: int16x8_t = _vpmaxq_s16(a, b);
15113        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15114    }
15115}
15116#[doc = "Folding maximum of adjacent pairs"]
15117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"]
15118#[inline]
15119#[cfg(target_endian = "little")]
15120#[target_feature(enable = "neon")]
15121#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15122#[cfg_attr(test, assert_instr(smaxp))]
15123pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
15124    unsafe extern "unadjusted" {
15125        #[cfg_attr(
15126            any(target_arch = "aarch64", target_arch = "arm64ec"),
15127            link_name = "llvm.aarch64.neon.smaxp.v4i32"
15128        )]
15129        fn _vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
15130    }
15131    unsafe { _vpmaxq_s32(a, b) }
15132}
15133#[doc = "Folding maximum of adjacent pairs"]
15134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"]
15135#[inline]
15136#[cfg(target_endian = "big")]
15137#[target_feature(enable = "neon")]
15138#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15139#[cfg_attr(test, assert_instr(smaxp))]
15140pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
15141    unsafe extern "unadjusted" {
15142        #[cfg_attr(
15143            any(target_arch = "aarch64", target_arch = "arm64ec"),
15144            link_name = "llvm.aarch64.neon.smaxp.v4i32"
15145        )]
15146        fn _vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
15147    }
15148    unsafe {
15149        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
15150        let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
15151        let ret_val: int32x4_t = _vpmaxq_s32(a, b);
15152        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15153    }
15154}
15155#[doc = "Folding maximum of adjacent pairs"]
15156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"]
15157#[inline]
15158#[cfg(target_endian = "little")]
15159#[target_feature(enable = "neon")]
15160#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15161#[cfg_attr(test, assert_instr(umaxp))]
15162pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
15163    unsafe extern "unadjusted" {
15164        #[cfg_attr(
15165            any(target_arch = "aarch64", target_arch = "arm64ec"),
15166            link_name = "llvm.aarch64.neon.umaxp.v16i8"
15167        )]
15168        fn _vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
15169    }
15170    unsafe { _vpmaxq_u8(a, b) }
15171}
15172#[doc = "Folding maximum of adjacent pairs"]
15173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"]
15174#[inline]
15175#[cfg(target_endian = "big")]
15176#[target_feature(enable = "neon")]
15177#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15178#[cfg_attr(test, assert_instr(umaxp))]
15179pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
15180    unsafe extern "unadjusted" {
15181        #[cfg_attr(
15182            any(target_arch = "aarch64", target_arch = "arm64ec"),
15183            link_name = "llvm.aarch64.neon.umaxp.v16i8"
15184        )]
15185        fn _vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
15186    }
15187    unsafe {
15188        let a: uint8x16_t =
15189            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
15190        let b: uint8x16_t =
15191            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
15192        let ret_val: uint8x16_t = _vpmaxq_u8(a, b);
15193        simd_shuffle!(
15194            ret_val,
15195            ret_val,
15196            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15197        )
15198    }
15199}
15200#[doc = "Folding maximum of adjacent pairs"]
15201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"]
15202#[inline]
15203#[cfg(target_endian = "little")]
15204#[target_feature(enable = "neon")]
15205#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15206#[cfg_attr(test, assert_instr(umaxp))]
15207pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
15208    unsafe extern "unadjusted" {
15209        #[cfg_attr(
15210            any(target_arch = "aarch64", target_arch = "arm64ec"),
15211            link_name = "llvm.aarch64.neon.umaxp.v8i16"
15212        )]
15213        fn _vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
15214    }
15215    unsafe { _vpmaxq_u16(a, b) }
15216}
15217#[doc = "Folding maximum of adjacent pairs"]
15218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"]
15219#[inline]
15220#[cfg(target_endian = "big")]
15221#[target_feature(enable = "neon")]
15222#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15223#[cfg_attr(test, assert_instr(umaxp))]
15224pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
15225    unsafe extern "unadjusted" {
15226        #[cfg_attr(
15227            any(target_arch = "aarch64", target_arch = "arm64ec"),
15228            link_name = "llvm.aarch64.neon.umaxp.v8i16"
15229        )]
15230        fn _vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
15231    }
15232    unsafe {
15233        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
15234        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
15235        let ret_val: uint16x8_t = _vpmaxq_u16(a, b);
15236        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15237    }
15238}
15239#[doc = "Folding maximum of adjacent pairs"]
15240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"]
15241#[inline]
15242#[cfg(target_endian = "little")]
15243#[target_feature(enable = "neon")]
15244#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15245#[cfg_attr(test, assert_instr(umaxp))]
15246pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
15247    unsafe extern "unadjusted" {
15248        #[cfg_attr(
15249            any(target_arch = "aarch64", target_arch = "arm64ec"),
15250            link_name = "llvm.aarch64.neon.umaxp.v4i32"
15251        )]
15252        fn _vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
15253    }
15254    unsafe { _vpmaxq_u32(a, b) }
15255}
15256#[doc = "Folding maximum of adjacent pairs"]
15257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"]
15258#[inline]
15259#[cfg(target_endian = "big")]
15260#[target_feature(enable = "neon")]
15261#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15262#[cfg_attr(test, assert_instr(umaxp))]
15263pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
15264    unsafe extern "unadjusted" {
15265        #[cfg_attr(
15266            any(target_arch = "aarch64", target_arch = "arm64ec"),
15267            link_name = "llvm.aarch64.neon.umaxp.v4i32"
15268        )]
15269        fn _vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
15270    }
15271    unsafe {
15272        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
15273        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
15274        let ret_val: uint32x4_t = _vpmaxq_u32(a, b);
15275        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15276    }
15277}
15278#[doc = "Floating-point maximum pairwise"]
15279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)"]
15280#[inline]
15281#[target_feature(enable = "neon")]
15282#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15283#[cfg_attr(test, assert_instr(fmaxp))]
15284pub fn vpmaxqd_f64(a: float64x2_t) -> f64 {
15285    unsafe extern "unadjusted" {
15286        #[cfg_attr(
15287            any(target_arch = "aarch64", target_arch = "arm64ec"),
15288            link_name = "llvm.aarch64.neon.fmaxv.f64.v2f64"
15289        )]
15290        fn _vpmaxqd_f64(a: float64x2_t) -> f64;
15291    }
15292    unsafe { _vpmaxqd_f64(a) }
15293}
15294#[doc = "Floating-point maximum pairwise"]
15295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)"]
15296#[inline]
15297#[target_feature(enable = "neon")]
15298#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15299#[cfg_attr(test, assert_instr(fmaxp))]
15300pub fn vpmaxs_f32(a: float32x2_t) -> f32 {
15301    unsafe extern "unadjusted" {
15302        #[cfg_attr(
15303            any(target_arch = "aarch64", target_arch = "arm64ec"),
15304            link_name = "llvm.aarch64.neon.fmaxv.f32.v2f32"
15305        )]
15306        fn _vpmaxs_f32(a: float32x2_t) -> f32;
15307    }
15308    unsafe { _vpmaxs_f32(a) }
15309}
15310#[doc = "Floating-point add pairwise"]
15311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"]
15312#[inline]
15313#[cfg(target_endian = "little")]
15314#[target_feature(enable = "neon,fp16")]
15315#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
15316#[cfg(not(target_arch = "arm64ec"))]
15317#[cfg_attr(test, assert_instr(fminp))]
15318pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
15319    unsafe extern "unadjusted" {
15320        #[cfg_attr(
15321            any(target_arch = "aarch64", target_arch = "arm64ec"),
15322            link_name = "llvm.aarch64.neon.fminp.v4f16"
15323        )]
15324        fn _vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
15325    }
15326    unsafe { _vpmin_f16(a, b) }
15327}
15328#[doc = "Floating-point add pairwise"]
15329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"]
15330#[inline]
15331#[cfg(target_endian = "big")]
15332#[target_feature(enable = "neon,fp16")]
15333#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
15334#[cfg(not(target_arch = "arm64ec"))]
15335#[cfg_attr(test, assert_instr(fminp))]
15336pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
15337    unsafe extern "unadjusted" {
15338        #[cfg_attr(
15339            any(target_arch = "aarch64", target_arch = "arm64ec"),
15340            link_name = "llvm.aarch64.neon.fminp.v4f16"
15341        )]
15342        fn _vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
15343    }
15344    unsafe {
15345        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
15346        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
15347        let ret_val: float16x4_t = _vpmin_f16(a, b);
15348        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15349    }
15350}
15351#[doc = "Floating-point add pairwise"]
15352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"]
15353#[inline]
15354#[cfg(target_endian = "little")]
15355#[target_feature(enable = "neon,fp16")]
15356#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
15357#[cfg(not(target_arch = "arm64ec"))]
15358#[cfg_attr(test, assert_instr(fminp))]
15359pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
15360    unsafe extern "unadjusted" {
15361        #[cfg_attr(
15362            any(target_arch = "aarch64", target_arch = "arm64ec"),
15363            link_name = "llvm.aarch64.neon.fminp.v8f16"
15364        )]
15365        fn _vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
15366    }
15367    unsafe { _vpminq_f16(a, b) }
15368}
15369#[doc = "Floating-point add pairwise"]
15370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"]
15371#[inline]
15372#[cfg(target_endian = "big")]
15373#[target_feature(enable = "neon,fp16")]
15374#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
15375#[cfg(not(target_arch = "arm64ec"))]
15376#[cfg_attr(test, assert_instr(fminp))]
15377pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
15378    unsafe extern "unadjusted" {
15379        #[cfg_attr(
15380            any(target_arch = "aarch64", target_arch = "arm64ec"),
15381            link_name = "llvm.aarch64.neon.fminp.v8f16"
15382        )]
15383        fn _vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
15384    }
15385    unsafe {
15386        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
15387        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
15388        let ret_val: float16x8_t = _vpminq_f16(a, b);
15389        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15390    }
15391}
15392#[doc = "Floating-point add pairwise"]
15393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"]
15394#[inline]
15395#[cfg(target_endian = "little")]
15396#[target_feature(enable = "neon,fp16")]
15397#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
15398#[cfg(not(target_arch = "arm64ec"))]
15399#[cfg_attr(test, assert_instr(fminnmp))]
15400pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
15401    unsafe extern "unadjusted" {
15402        #[cfg_attr(
15403            any(target_arch = "aarch64", target_arch = "arm64ec"),
15404            link_name = "llvm.aarch64.neon.fminnmp.v4f16"
15405        )]
15406        fn _vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
15407    }
15408    unsafe { _vpminnm_f16(a, b) }
15409}
15410#[doc = "Floating-point add pairwise"]
15411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"]
15412#[inline]
15413#[cfg(target_endian = "big")]
15414#[target_feature(enable = "neon,fp16")]
15415#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
15416#[cfg(not(target_arch = "arm64ec"))]
15417#[cfg_attr(test, assert_instr(fminnmp))]
15418pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
15419    unsafe extern "unadjusted" {
15420        #[cfg_attr(
15421            any(target_arch = "aarch64", target_arch = "arm64ec"),
15422            link_name = "llvm.aarch64.neon.fminnmp.v4f16"
15423        )]
15424        fn _vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
15425    }
15426    unsafe {
15427        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
15428        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
15429        let ret_val: float16x4_t = _vpminnm_f16(a, b);
15430        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15431    }
15432}
15433#[doc = "Floating-point add pairwise"]
15434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"]
15435#[inline]
15436#[cfg(target_endian = "little")]
15437#[target_feature(enable = "neon,fp16")]
15438#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
15439#[cfg(not(target_arch = "arm64ec"))]
15440#[cfg_attr(test, assert_instr(fminnmp))]
15441pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
15442    unsafe extern "unadjusted" {
15443        #[cfg_attr(
15444            any(target_arch = "aarch64", target_arch = "arm64ec"),
15445            link_name = "llvm.aarch64.neon.fminnmp.v8f16"
15446        )]
15447        fn _vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
15448    }
15449    unsafe { _vpminnmq_f16(a, b) }
15450}
15451#[doc = "Floating-point add pairwise"]
15452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"]
15453#[inline]
15454#[cfg(target_endian = "big")]
15455#[target_feature(enable = "neon,fp16")]
15456#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
15457#[cfg(not(target_arch = "arm64ec"))]
15458#[cfg_attr(test, assert_instr(fminnmp))]
15459pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
15460    unsafe extern "unadjusted" {
15461        #[cfg_attr(
15462            any(target_arch = "aarch64", target_arch = "arm64ec"),
15463            link_name = "llvm.aarch64.neon.fminnmp.v8f16"
15464        )]
15465        fn _vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
15466    }
15467    unsafe {
15468        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
15469        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
15470        let ret_val: float16x8_t = _vpminnmq_f16(a, b);
15471        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15472    }
15473}
15474#[doc = "Floating-point Minimum Number Pairwise (vector)."]
15475#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"]
15476#[inline]
15477#[cfg(target_endian = "little")]
15478#[target_feature(enable = "neon")]
15479#[cfg_attr(test, assert_instr(fminnmp))]
15480#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15481pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
15482    unsafe extern "unadjusted" {
15483        #[cfg_attr(
15484            any(target_arch = "aarch64", target_arch = "arm64ec"),
15485            link_name = "llvm.aarch64.neon.fminnmp.v2f32"
15486        )]
15487        fn _vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
15488    }
15489    unsafe { _vpminnm_f32(a, b) }
15490}
15491#[doc = "Floating-point Minimum Number Pairwise (vector)."]
15492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"]
15493#[inline]
15494#[cfg(target_endian = "big")]
15495#[target_feature(enable = "neon")]
15496#[cfg_attr(test, assert_instr(fminnmp))]
15497#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15498pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
15499    unsafe extern "unadjusted" {
15500        #[cfg_attr(
15501            any(target_arch = "aarch64", target_arch = "arm64ec"),
15502            link_name = "llvm.aarch64.neon.fminnmp.v2f32"
15503        )]
15504        fn _vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
15505    }
15506    unsafe {
15507        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
15508        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
15509        let ret_val: float32x2_t = _vpminnm_f32(a, b);
15510        simd_shuffle!(ret_val, ret_val, [1, 0])
15511    }
15512}
15513#[doc = "Floating-point Minimum Number Pairwise (vector)."]
15514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"]
15515#[inline]
15516#[cfg(target_endian = "little")]
15517#[target_feature(enable = "neon")]
15518#[cfg_attr(test, assert_instr(fminnmp))]
15519#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15520pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
15521    unsafe extern "unadjusted" {
15522        #[cfg_attr(
15523            any(target_arch = "aarch64", target_arch = "arm64ec"),
15524            link_name = "llvm.aarch64.neon.fminnmp.v4f32"
15525        )]
15526        fn _vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
15527    }
15528    unsafe { _vpminnmq_f32(a, b) }
15529}
15530#[doc = "Floating-point Minimum Number Pairwise (vector)."]
15531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"]
15532#[inline]
15533#[cfg(target_endian = "big")]
15534#[target_feature(enable = "neon")]
15535#[cfg_attr(test, assert_instr(fminnmp))]
15536#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15537pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
15538    unsafe extern "unadjusted" {
15539        #[cfg_attr(
15540            any(target_arch = "aarch64", target_arch = "arm64ec"),
15541            link_name = "llvm.aarch64.neon.fminnmp.v4f32"
15542        )]
15543        fn _vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
15544    }
15545    unsafe {
15546        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
15547        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
15548        let ret_val: float32x4_t = _vpminnmq_f32(a, b);
15549        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15550    }
15551}
15552#[doc = "Floating-point Minimum Number Pairwise (vector)."]
15553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"]
15554#[inline]
15555#[cfg(target_endian = "little")]
15556#[target_feature(enable = "neon")]
15557#[cfg_attr(test, assert_instr(fminnmp))]
15558#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15559pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
15560    unsafe extern "unadjusted" {
15561        #[cfg_attr(
15562            any(target_arch = "aarch64", target_arch = "arm64ec"),
15563            link_name = "llvm.aarch64.neon.fminnmp.v2f64"
15564        )]
15565        fn _vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
15566    }
15567    unsafe { _vpminnmq_f64(a, b) }
15568}
15569#[doc = "Floating-point Minimum Number Pairwise (vector)."]
15570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"]
15571#[inline]
15572#[cfg(target_endian = "big")]
15573#[target_feature(enable = "neon")]
15574#[cfg_attr(test, assert_instr(fminnmp))]
15575#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15576pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
15577    unsafe extern "unadjusted" {
15578        #[cfg_attr(
15579            any(target_arch = "aarch64", target_arch = "arm64ec"),
15580            link_name = "llvm.aarch64.neon.fminnmp.v2f64"
15581        )]
15582        fn _vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
15583    }
15584    unsafe {
15585        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
15586        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
15587        let ret_val: float64x2_t = _vpminnmq_f64(a, b);
15588        simd_shuffle!(ret_val, ret_val, [1, 0])
15589    }
15590}
15591#[doc = "Floating-point minimum number pairwise"]
15592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"]
15593#[inline]
15594#[cfg(target_endian = "little")]
15595#[target_feature(enable = "neon")]
15596#[cfg_attr(test, assert_instr(fminnmp))]
15597#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15598pub fn vpminnmqd_f64(a: float64x2_t) -> f64 {
15599    unsafe extern "unadjusted" {
15600        #[cfg_attr(
15601            any(target_arch = "aarch64", target_arch = "arm64ec"),
15602            link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64"
15603        )]
15604        fn _vpminnmqd_f64(a: float64x2_t) -> f64;
15605    }
15606    unsafe { _vpminnmqd_f64(a) }
15607}
15608#[doc = "Floating-point minimum number pairwise"]
15609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"]
15610#[inline]
15611#[cfg(target_endian = "big")]
15612#[target_feature(enable = "neon")]
15613#[cfg_attr(test, assert_instr(fminnmp))]
15614#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15615pub fn vpminnmqd_f64(a: float64x2_t) -> f64 {
15616    unsafe extern "unadjusted" {
15617        #[cfg_attr(
15618            any(target_arch = "aarch64", target_arch = "arm64ec"),
15619            link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64"
15620        )]
15621        fn _vpminnmqd_f64(a: float64x2_t) -> f64;
15622    }
15623    unsafe {
15624        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
15625        _vpminnmqd_f64(a)
15626    }
15627}
15628#[doc = "Floating-point minimum number pairwise"]
15629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"]
15630#[inline]
15631#[cfg(target_endian = "little")]
15632#[target_feature(enable = "neon")]
15633#[cfg_attr(test, assert_instr(fminnmp))]
15634#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15635pub fn vpminnms_f32(a: float32x2_t) -> f32 {
15636    unsafe extern "unadjusted" {
15637        #[cfg_attr(
15638            any(target_arch = "aarch64", target_arch = "arm64ec"),
15639            link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32"
15640        )]
15641        fn _vpminnms_f32(a: float32x2_t) -> f32;
15642    }
15643    unsafe { _vpminnms_f32(a) }
15644}
15645#[doc = "Floating-point minimum number pairwise"]
15646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"]
15647#[inline]
15648#[cfg(target_endian = "big")]
15649#[target_feature(enable = "neon")]
15650#[cfg_attr(test, assert_instr(fminnmp))]
15651#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15652pub fn vpminnms_f32(a: float32x2_t) -> f32 {
15653    unsafe extern "unadjusted" {
15654        #[cfg_attr(
15655            any(target_arch = "aarch64", target_arch = "arm64ec"),
15656            link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32"
15657        )]
15658        fn _vpminnms_f32(a: float32x2_t) -> f32;
15659    }
15660    unsafe {
15661        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
15662        _vpminnms_f32(a)
15663    }
15664}
15665#[doc = "Folding minimum of adjacent pairs"]
15666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"]
15667#[inline]
15668#[cfg(target_endian = "little")]
15669#[target_feature(enable = "neon")]
15670#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15671#[cfg_attr(test, assert_instr(fminp))]
15672pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
15673    unsafe extern "unadjusted" {
15674        #[cfg_attr(
15675            any(target_arch = "aarch64", target_arch = "arm64ec"),
15676            link_name = "llvm.aarch64.neon.fminp.v4f32"
15677        )]
15678        fn _vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
15679    }
15680    unsafe { _vpminq_f32(a, b) }
15681}
15682#[doc = "Folding minimum of adjacent pairs"]
15683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"]
15684#[inline]
15685#[cfg(target_endian = "big")]
15686#[target_feature(enable = "neon")]
15687#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15688#[cfg_attr(test, assert_instr(fminp))]
15689pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
15690    unsafe extern "unadjusted" {
15691        #[cfg_attr(
15692            any(target_arch = "aarch64", target_arch = "arm64ec"),
15693            link_name = "llvm.aarch64.neon.fminp.v4f32"
15694        )]
15695        fn _vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
15696    }
15697    unsafe {
15698        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
15699        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
15700        let ret_val: float32x4_t = _vpminq_f32(a, b);
15701        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15702    }
15703}
15704#[doc = "Folding minimum of adjacent pairs"]
15705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"]
15706#[inline]
15707#[cfg(target_endian = "little")]
15708#[target_feature(enable = "neon")]
15709#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15710#[cfg_attr(test, assert_instr(fminp))]
15711pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
15712    unsafe extern "unadjusted" {
15713        #[cfg_attr(
15714            any(target_arch = "aarch64", target_arch = "arm64ec"),
15715            link_name = "llvm.aarch64.neon.fminp.v2f64"
15716        )]
15717        fn _vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
15718    }
15719    unsafe { _vpminq_f64(a, b) }
15720}
15721#[doc = "Folding minimum of adjacent pairs"]
15722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"]
15723#[inline]
15724#[cfg(target_endian = "big")]
15725#[target_feature(enable = "neon")]
15726#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15727#[cfg_attr(test, assert_instr(fminp))]
15728pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
15729    unsafe extern "unadjusted" {
15730        #[cfg_attr(
15731            any(target_arch = "aarch64", target_arch = "arm64ec"),
15732            link_name = "llvm.aarch64.neon.fminp.v2f64"
15733        )]
15734        fn _vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
15735    }
15736    unsafe {
15737        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
15738        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
15739        let ret_val: float64x2_t = _vpminq_f64(a, b);
15740        simd_shuffle!(ret_val, ret_val, [1, 0])
15741    }
15742}
15743#[doc = "Folding minimum of adjacent pairs"]
15744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"]
15745#[inline]
15746#[cfg(target_endian = "little")]
15747#[target_feature(enable = "neon")]
15748#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15749#[cfg_attr(test, assert_instr(sminp))]
15750pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
15751    unsafe extern "unadjusted" {
15752        #[cfg_attr(
15753            any(target_arch = "aarch64", target_arch = "arm64ec"),
15754            link_name = "llvm.aarch64.neon.sminp.v16i8"
15755        )]
15756        fn _vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
15757    }
15758    unsafe { _vpminq_s8(a, b) }
15759}
15760#[doc = "Folding minimum of adjacent pairs"]
15761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"]
15762#[inline]
15763#[cfg(target_endian = "big")]
15764#[target_feature(enable = "neon")]
15765#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15766#[cfg_attr(test, assert_instr(sminp))]
15767pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
15768    unsafe extern "unadjusted" {
15769        #[cfg_attr(
15770            any(target_arch = "aarch64", target_arch = "arm64ec"),
15771            link_name = "llvm.aarch64.neon.sminp.v16i8"
15772        )]
15773        fn _vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
15774    }
15775    unsafe {
15776        let a: int8x16_t =
15777            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
15778        let b: int8x16_t =
15779            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
15780        let ret_val: int8x16_t = _vpminq_s8(a, b);
15781        simd_shuffle!(
15782            ret_val,
15783            ret_val,
15784            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15785        )
15786    }
15787}
15788#[doc = "Folding minimum of adjacent pairs"]
15789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"]
15790#[inline]
15791#[cfg(target_endian = "little")]
15792#[target_feature(enable = "neon")]
15793#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15794#[cfg_attr(test, assert_instr(sminp))]
15795pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
15796    unsafe extern "unadjusted" {
15797        #[cfg_attr(
15798            any(target_arch = "aarch64", target_arch = "arm64ec"),
15799            link_name = "llvm.aarch64.neon.sminp.v8i16"
15800        )]
15801        fn _vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
15802    }
15803    unsafe { _vpminq_s16(a, b) }
15804}
15805#[doc = "Folding minimum of adjacent pairs"]
15806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"]
15807#[inline]
15808#[cfg(target_endian = "big")]
15809#[target_feature(enable = "neon")]
15810#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15811#[cfg_attr(test, assert_instr(sminp))]
15812pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
15813    unsafe extern "unadjusted" {
15814        #[cfg_attr(
15815            any(target_arch = "aarch64", target_arch = "arm64ec"),
15816            link_name = "llvm.aarch64.neon.sminp.v8i16"
15817        )]
15818        fn _vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
15819    }
15820    unsafe {
15821        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
15822        let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
15823        let ret_val: int16x8_t = _vpminq_s16(a, b);
15824        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15825    }
15826}
15827#[doc = "Folding minimum of adjacent pairs"]
15828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"]
15829#[inline]
15830#[cfg(target_endian = "little")]
15831#[target_feature(enable = "neon")]
15832#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15833#[cfg_attr(test, assert_instr(sminp))]
15834pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
15835    unsafe extern "unadjusted" {
15836        #[cfg_attr(
15837            any(target_arch = "aarch64", target_arch = "arm64ec"),
15838            link_name = "llvm.aarch64.neon.sminp.v4i32"
15839        )]
15840        fn _vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
15841    }
15842    unsafe { _vpminq_s32(a, b) }
15843}
15844#[doc = "Folding minimum of adjacent pairs"]
15845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"]
15846#[inline]
15847#[cfg(target_endian = "big")]
15848#[target_feature(enable = "neon")]
15849#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15850#[cfg_attr(test, assert_instr(sminp))]
15851pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
15852    unsafe extern "unadjusted" {
15853        #[cfg_attr(
15854            any(target_arch = "aarch64", target_arch = "arm64ec"),
15855            link_name = "llvm.aarch64.neon.sminp.v4i32"
15856        )]
15857        fn _vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
15858    }
15859    unsafe {
15860        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
15861        let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
15862        let ret_val: int32x4_t = _vpminq_s32(a, b);
15863        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15864    }
15865}
15866#[doc = "Folding minimum of adjacent pairs"]
15867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"]
15868#[inline]
15869#[cfg(target_endian = "little")]
15870#[target_feature(enable = "neon")]
15871#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15872#[cfg_attr(test, assert_instr(uminp))]
15873pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
15874    unsafe extern "unadjusted" {
15875        #[cfg_attr(
15876            any(target_arch = "aarch64", target_arch = "arm64ec"),
15877            link_name = "llvm.aarch64.neon.uminp.v16i8"
15878        )]
15879        fn _vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
15880    }
15881    unsafe { _vpminq_u8(a, b) }
15882}
15883#[doc = "Folding minimum of adjacent pairs"]
15884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"]
15885#[inline]
15886#[cfg(target_endian = "big")]
15887#[target_feature(enable = "neon")]
15888#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15889#[cfg_attr(test, assert_instr(uminp))]
15890pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
15891    unsafe extern "unadjusted" {
15892        #[cfg_attr(
15893            any(target_arch = "aarch64", target_arch = "arm64ec"),
15894            link_name = "llvm.aarch64.neon.uminp.v16i8"
15895        )]
15896        fn _vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
15897    }
15898    unsafe {
15899        let a: uint8x16_t =
15900            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
15901        let b: uint8x16_t =
15902            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
15903        let ret_val: uint8x16_t = _vpminq_u8(a, b);
15904        simd_shuffle!(
15905            ret_val,
15906            ret_val,
15907            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15908        )
15909    }
15910}
15911#[doc = "Folding minimum of adjacent pairs"]
15912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"]
15913#[inline]
15914#[cfg(target_endian = "little")]
15915#[target_feature(enable = "neon")]
15916#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15917#[cfg_attr(test, assert_instr(uminp))]
15918pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
15919    unsafe extern "unadjusted" {
15920        #[cfg_attr(
15921            any(target_arch = "aarch64", target_arch = "arm64ec"),
15922            link_name = "llvm.aarch64.neon.uminp.v8i16"
15923        )]
15924        fn _vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
15925    }
15926    unsafe { _vpminq_u16(a, b) }
15927}
15928#[doc = "Folding minimum of adjacent pairs"]
15929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"]
15930#[inline]
15931#[cfg(target_endian = "big")]
15932#[target_feature(enable = "neon")]
15933#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15934#[cfg_attr(test, assert_instr(uminp))]
15935pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
15936    unsafe extern "unadjusted" {
15937        #[cfg_attr(
15938            any(target_arch = "aarch64", target_arch = "arm64ec"),
15939            link_name = "llvm.aarch64.neon.uminp.v8i16"
15940        )]
15941        fn _vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
15942    }
15943    unsafe {
15944        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
15945        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
15946        let ret_val: uint16x8_t = _vpminq_u16(a, b);
15947        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15948    }
15949}
15950#[doc = "Folding minimum of adjacent pairs"]
15951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"]
15952#[inline]
15953#[cfg(target_endian = "little")]
15954#[target_feature(enable = "neon")]
15955#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15956#[cfg_attr(test, assert_instr(uminp))]
15957pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
15958    unsafe extern "unadjusted" {
15959        #[cfg_attr(
15960            any(target_arch = "aarch64", target_arch = "arm64ec"),
15961            link_name = "llvm.aarch64.neon.uminp.v4i32"
15962        )]
15963        fn _vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
15964    }
15965    unsafe { _vpminq_u32(a, b) }
15966}
15967#[doc = "Folding minimum of adjacent pairs"]
15968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"]
15969#[inline]
15970#[cfg(target_endian = "big")]
15971#[target_feature(enable = "neon")]
15972#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15973#[cfg_attr(test, assert_instr(uminp))]
15974pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
15975    unsafe extern "unadjusted" {
15976        #[cfg_attr(
15977            any(target_arch = "aarch64", target_arch = "arm64ec"),
15978            link_name = "llvm.aarch64.neon.uminp.v4i32"
15979        )]
15980        fn _vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
15981    }
15982    unsafe {
15983        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
15984        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
15985        let ret_val: uint32x4_t = _vpminq_u32(a, b);
15986        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15987    }
15988}
15989#[doc = "Floating-point minimum pairwise"]
15990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"]
15991#[inline]
15992#[cfg(target_endian = "little")]
15993#[target_feature(enable = "neon")]
15994#[stable(feature = "neon_intrinsics", since = "1.59.0")]
15995#[cfg_attr(test, assert_instr(fminp))]
15996pub fn vpminqd_f64(a: float64x2_t) -> f64 {
15997    unsafe extern "unadjusted" {
15998        #[cfg_attr(
15999            any(target_arch = "aarch64", target_arch = "arm64ec"),
16000            link_name = "llvm.aarch64.neon.fminv.f64.v2f64"
16001        )]
16002        fn _vpminqd_f64(a: float64x2_t) -> f64;
16003    }
16004    unsafe { _vpminqd_f64(a) }
16005}
16006#[doc = "Floating-point minimum pairwise"]
16007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"]
16008#[inline]
16009#[cfg(target_endian = "big")]
16010#[target_feature(enable = "neon")]
16011#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16012#[cfg_attr(test, assert_instr(fminp))]
16013pub fn vpminqd_f64(a: float64x2_t) -> f64 {
16014    unsafe extern "unadjusted" {
16015        #[cfg_attr(
16016            any(target_arch = "aarch64", target_arch = "arm64ec"),
16017            link_name = "llvm.aarch64.neon.fminv.f64.v2f64"
16018        )]
16019        fn _vpminqd_f64(a: float64x2_t) -> f64;
16020    }
16021    unsafe {
16022        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
16023        _vpminqd_f64(a)
16024    }
16025}
16026#[doc = "Floating-point minimum pairwise"]
16027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"]
16028#[inline]
16029#[cfg(target_endian = "little")]
16030#[target_feature(enable = "neon")]
16031#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16032#[cfg_attr(test, assert_instr(fminp))]
16033pub fn vpmins_f32(a: float32x2_t) -> f32 {
16034    unsafe extern "unadjusted" {
16035        #[cfg_attr(
16036            any(target_arch = "aarch64", target_arch = "arm64ec"),
16037            link_name = "llvm.aarch64.neon.fminv.f32.v2f32"
16038        )]
16039        fn _vpmins_f32(a: float32x2_t) -> f32;
16040    }
16041    unsafe { _vpmins_f32(a) }
16042}
16043#[doc = "Floating-point minimum pairwise"]
16044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"]
16045#[inline]
16046#[cfg(target_endian = "big")]
16047#[target_feature(enable = "neon")]
16048#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16049#[cfg_attr(test, assert_instr(fminp))]
16050pub fn vpmins_f32(a: float32x2_t) -> f32 {
16051    unsafe extern "unadjusted" {
16052        #[cfg_attr(
16053            any(target_arch = "aarch64", target_arch = "arm64ec"),
16054            link_name = "llvm.aarch64.neon.fminv.f32.v2f32"
16055        )]
16056        fn _vpmins_f32(a: float32x2_t) -> f32;
16057    }
16058    unsafe {
16059        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
16060        _vpmins_f32(a)
16061    }
16062}
16063#[doc = "Signed saturating Absolute value"]
16064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)"]
16065#[inline]
16066#[target_feature(enable = "neon")]
16067#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16068#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
16069pub fn vqabs_s64(a: int64x1_t) -> int64x1_t {
16070    unsafe extern "unadjusted" {
16071        #[cfg_attr(
16072            any(target_arch = "aarch64", target_arch = "arm64ec"),
16073            link_name = "llvm.aarch64.neon.sqabs.v1i64"
16074        )]
16075        fn _vqabs_s64(a: int64x1_t) -> int64x1_t;
16076    }
16077    unsafe { _vqabs_s64(a) }
16078}
16079#[doc = "Signed saturating Absolute value"]
16080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)"]
16081#[inline]
16082#[target_feature(enable = "neon")]
16083#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16084#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
16085pub fn vqabsq_s64(a: int64x2_t) -> int64x2_t {
16086    unsafe extern "unadjusted" {
16087        #[cfg_attr(
16088            any(target_arch = "aarch64", target_arch = "arm64ec"),
16089            link_name = "llvm.aarch64.neon.sqabs.v2i64"
16090        )]
16091        fn _vqabsq_s64(a: int64x2_t) -> int64x2_t;
16092    }
16093    unsafe { _vqabsq_s64(a) }
16094}
16095#[doc = "Signed saturating absolute value"]
16096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)"]
16097#[inline]
16098#[target_feature(enable = "neon")]
16099#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16100#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
16101pub fn vqabsb_s8(a: i8) -> i8 {
16102    vget_lane_s8::<0>(vqabs_s8(vdup_n_s8(a)))
16103}
16104#[doc = "Signed saturating absolute value"]
16105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"]
16106#[inline]
16107#[target_feature(enable = "neon")]
16108#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16109#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
16110pub fn vqabsh_s16(a: i16) -> i16 {
16111    vget_lane_s16::<0>(vqabs_s16(vdup_n_s16(a)))
16112}
16113#[doc = "Signed saturating absolute value"]
16114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"]
16115#[inline]
16116#[target_feature(enable = "neon")]
16117#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16118#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
16119pub fn vqabss_s32(a: i32) -> i32 {
16120    unsafe extern "unadjusted" {
16121        #[cfg_attr(
16122            any(target_arch = "aarch64", target_arch = "arm64ec"),
16123            link_name = "llvm.aarch64.neon.sqabs.i32"
16124        )]
16125        fn _vqabss_s32(a: i32) -> i32;
16126    }
16127    unsafe { _vqabss_s32(a) }
16128}
16129#[doc = "Signed saturating absolute value"]
16130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)"]
16131#[inline]
16132#[target_feature(enable = "neon")]
16133#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16134#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
16135pub fn vqabsd_s64(a: i64) -> i64 {
16136    unsafe extern "unadjusted" {
16137        #[cfg_attr(
16138            any(target_arch = "aarch64", target_arch = "arm64ec"),
16139            link_name = "llvm.aarch64.neon.sqabs.i64"
16140        )]
16141        fn _vqabsd_s64(a: i64) -> i64;
16142    }
16143    unsafe { _vqabsd_s64(a) }
16144}
16145#[doc = "Saturating add"]
16146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)"]
16147#[inline]
16148#[target_feature(enable = "neon")]
16149#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16150#[cfg_attr(test, assert_instr(sqadd))]
16151pub fn vqaddb_s8(a: i8, b: i8) -> i8 {
16152    let a: int8x8_t = vdup_n_s8(a);
16153    let b: int8x8_t = vdup_n_s8(b);
16154    vget_lane_s8::<0>(vqadd_s8(a, b))
16155}
16156#[doc = "Saturating add"]
16157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"]
16158#[inline]
16159#[target_feature(enable = "neon")]
16160#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16161#[cfg_attr(test, assert_instr(sqadd))]
16162pub fn vqaddh_s16(a: i16, b: i16) -> i16 {
16163    let a: int16x4_t = vdup_n_s16(a);
16164    let b: int16x4_t = vdup_n_s16(b);
16165    vget_lane_s16::<0>(vqadd_s16(a, b))
16166}
16167#[doc = "Saturating add"]
16168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"]
16169#[inline]
16170#[target_feature(enable = "neon")]
16171#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16172#[cfg_attr(test, assert_instr(uqadd))]
16173pub fn vqaddb_u8(a: u8, b: u8) -> u8 {
16174    let a: uint8x8_t = vdup_n_u8(a);
16175    let b: uint8x8_t = vdup_n_u8(b);
16176    vget_lane_u8::<0>(vqadd_u8(a, b))
16177}
16178#[doc = "Saturating add"]
16179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"]
16180#[inline]
16181#[target_feature(enable = "neon")]
16182#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16183#[cfg_attr(test, assert_instr(uqadd))]
16184pub fn vqaddh_u16(a: u16, b: u16) -> u16 {
16185    let a: uint16x4_t = vdup_n_u16(a);
16186    let b: uint16x4_t = vdup_n_u16(b);
16187    vget_lane_u16::<0>(vqadd_u16(a, b))
16188}
16189#[doc = "Saturating add"]
16190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"]
16191#[inline]
16192#[target_feature(enable = "neon")]
16193#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16194#[cfg_attr(test, assert_instr(sqadd))]
16195pub fn vqadds_s32(a: i32, b: i32) -> i32 {
16196    unsafe extern "unadjusted" {
16197        #[cfg_attr(
16198            any(target_arch = "aarch64", target_arch = "arm64ec"),
16199            link_name = "llvm.aarch64.neon.sqadd.i32"
16200        )]
16201        fn _vqadds_s32(a: i32, b: i32) -> i32;
16202    }
16203    unsafe { _vqadds_s32(a, b) }
16204}
16205#[doc = "Saturating add"]
16206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64)"]
16207#[inline]
16208#[target_feature(enable = "neon")]
16209#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16210#[cfg_attr(test, assert_instr(sqadd))]
16211pub fn vqaddd_s64(a: i64, b: i64) -> i64 {
16212    unsafe extern "unadjusted" {
16213        #[cfg_attr(
16214            any(target_arch = "aarch64", target_arch = "arm64ec"),
16215            link_name = "llvm.aarch64.neon.sqadd.i64"
16216        )]
16217        fn _vqaddd_s64(a: i64, b: i64) -> i64;
16218    }
16219    unsafe { _vqaddd_s64(a, b) }
16220}
16221#[doc = "Saturating add"]
16222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)"]
16223#[inline]
16224#[target_feature(enable = "neon")]
16225#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16226#[cfg_attr(test, assert_instr(uqadd))]
16227pub fn vqadds_u32(a: u32, b: u32) -> u32 {
16228    unsafe extern "unadjusted" {
16229        #[cfg_attr(
16230            any(target_arch = "aarch64", target_arch = "arm64ec"),
16231            link_name = "llvm.aarch64.neon.uqadd.i32"
16232        )]
16233        fn _vqadds_u32(a: u32, b: u32) -> u32;
16234    }
16235    unsafe { _vqadds_u32(a, b) }
16236}
16237#[doc = "Saturating add"]
16238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64)"]
16239#[inline]
16240#[target_feature(enable = "neon")]
16241#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16242#[cfg_attr(test, assert_instr(uqadd))]
16243pub fn vqaddd_u64(a: u64, b: u64) -> u64 {
16244    unsafe extern "unadjusted" {
16245        #[cfg_attr(
16246            any(target_arch = "aarch64", target_arch = "arm64ec"),
16247            link_name = "llvm.aarch64.neon.uqadd.i64"
16248        )]
16249        fn _vqaddd_u64(a: u64, b: u64) -> u64;
16250    }
16251    unsafe { _vqaddd_u64(a, b) }
16252}
16253#[doc = "Signed saturating doubling multiply-add long"]
16254#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"]
16255#[inline]
16256#[target_feature(enable = "neon")]
16257#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
16258#[rustc_legacy_const_generics(3)]
16259#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16260pub fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
16261    static_assert_uimm_bits!(N, 2);
16262    vqaddq_s32(a, vqdmull_high_lane_s16::<N>(b, c))
16263}
16264#[doc = "Signed saturating doubling multiply-add long"]
16265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"]
16266#[inline]
16267#[target_feature(enable = "neon")]
16268#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
16269#[rustc_legacy_const_generics(3)]
16270#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16271pub fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
16272    static_assert_uimm_bits!(N, 3);
16273    vqaddq_s32(a, vqdmull_high_laneq_s16::<N>(b, c))
16274}
16275#[doc = "Signed saturating doubling multiply-add long"]
16276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"]
16277#[inline]
16278#[target_feature(enable = "neon")]
16279#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
16280#[rustc_legacy_const_generics(3)]
16281#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16282pub fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
16283    static_assert_uimm_bits!(N, 1);
16284    vqaddq_s64(a, vqdmull_high_lane_s32::<N>(b, c))
16285}
16286#[doc = "Signed saturating doubling multiply-add long"]
16287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"]
16288#[inline]
16289#[target_feature(enable = "neon")]
16290#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
16291#[rustc_legacy_const_generics(3)]
16292#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16293pub fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
16294    static_assert_uimm_bits!(N, 2);
16295    vqaddq_s64(a, vqdmull_high_laneq_s32::<N>(b, c))
16296}
16297#[doc = "Signed saturating doubling multiply-add long"]
16298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"]
16299#[inline]
16300#[target_feature(enable = "neon")]
16301#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
16302#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16303pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
16304    vqaddq_s32(a, vqdmull_high_n_s16(b, c))
16305}
16306#[doc = "Signed saturating doubling multiply-add long"]
16307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"]
16308#[inline]
16309#[target_feature(enable = "neon")]
16310#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
16311#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16312pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
16313    vqaddq_s32(a, vqdmull_high_s16(b, c))
16314}
16315#[doc = "Signed saturating doubling multiply-add long"]
16316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"]
16317#[inline]
16318#[target_feature(enable = "neon")]
16319#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
16320#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16321pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
16322    vqaddq_s64(a, vqdmull_high_n_s32(b, c))
16323}
16324#[doc = "Signed saturating doubling multiply-add long"]
16325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"]
16326#[inline]
16327#[target_feature(enable = "neon")]
16328#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
16329#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16330pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
16331    vqaddq_s64(a, vqdmull_high_s32(b, c))
16332}
16333#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
16334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"]
16335#[inline]
16336#[target_feature(enable = "neon")]
16337#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 2))]
16338#[rustc_legacy_const_generics(3)]
16339#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16340pub fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
16341    static_assert_uimm_bits!(N, 3);
16342    vqaddq_s32(a, vqdmull_laneq_s16::<N>(b, c))
16343}
16344#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
16345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"]
16346#[inline]
16347#[target_feature(enable = "neon")]
16348#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 1))]
16349#[rustc_legacy_const_generics(3)]
16350#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16351pub fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
16352    static_assert_uimm_bits!(N, 2);
16353    vqaddq_s64(a, vqdmull_laneq_s32::<N>(b, c))
16354}
16355#[doc = "Signed saturating doubling multiply-add long"]
16356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"]
16357#[inline]
16358#[target_feature(enable = "neon")]
16359#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
16360#[rustc_legacy_const_generics(3)]
16361#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16362pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
16363    static_assert_uimm_bits!(LANE, 2);
16364    vqdmlalh_s16(a, b, vget_lane_s16::<LANE>(c))
16365}
16366#[doc = "Signed saturating doubling multiply-add long"]
16367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"]
16368#[inline]
16369#[target_feature(enable = "neon")]
16370#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
16371#[rustc_legacy_const_generics(3)]
16372#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16373pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32 {
16374    static_assert_uimm_bits!(LANE, 3);
16375    vqdmlalh_s16(a, b, vgetq_lane_s16::<LANE>(c))
16376}
16377#[doc = "Signed saturating doubling multiply-add long"]
16378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"]
16379#[inline]
16380#[target_feature(enable = "neon")]
16381#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
16382#[rustc_legacy_const_generics(3)]
16383#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16384pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
16385    static_assert_uimm_bits!(LANE, 1);
16386    vqdmlals_s32(a, b, vget_lane_s32::<LANE>(c))
16387}
16388#[doc = "Signed saturating doubling multiply-add long"]
16389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"]
16390#[inline]
16391#[target_feature(enable = "neon")]
16392#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, LANE = 0))]
16393#[rustc_legacy_const_generics(3)]
16394#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16395pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64 {
16396    static_assert_uimm_bits!(LANE, 2);
16397    vqdmlals_s32(a, b, vgetq_lane_s32::<LANE>(c))
16398}
16399#[doc = "Signed saturating doubling multiply-add long"]
16400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"]
16401#[inline]
16402#[target_feature(enable = "neon")]
16403#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal))]
16404#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16405pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 {
16406    let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c));
16407    vqadds_s32(a, vgetq_lane_s32::<0>(x))
16408}
16409#[doc = "Signed saturating doubling multiply-add long"]
16410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"]
16411#[inline]
16412#[target_feature(enable = "neon")]
16413#[cfg_attr(test, assert_instr(sqdmlal))]
16414#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16415pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 {
16416    let x: i64 = vqaddd_s64(a, vqdmulls_s32(b, c));
16417    x
16418}
16419#[doc = "Signed saturating doubling multiply-subtract long"]
16420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"]
16421#[inline]
16422#[target_feature(enable = "neon")]
16423#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
16424#[rustc_legacy_const_generics(3)]
16425#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16426pub fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
16427    static_assert_uimm_bits!(N, 2);
16428    vqsubq_s32(a, vqdmull_high_lane_s16::<N>(b, c))
16429}
16430#[doc = "Signed saturating doubling multiply-subtract long"]
16431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"]
16432#[inline]
16433#[target_feature(enable = "neon")]
16434#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
16435#[rustc_legacy_const_generics(3)]
16436#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16437pub fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
16438    static_assert_uimm_bits!(N, 3);
16439    vqsubq_s32(a, vqdmull_high_laneq_s16::<N>(b, c))
16440}
16441#[doc = "Signed saturating doubling multiply-subtract long"]
16442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"]
16443#[inline]
16444#[target_feature(enable = "neon")]
16445#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
16446#[rustc_legacy_const_generics(3)]
16447#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16448pub fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
16449    static_assert_uimm_bits!(N, 1);
16450    vqsubq_s64(a, vqdmull_high_lane_s32::<N>(b, c))
16451}
16452#[doc = "Signed saturating doubling multiply-subtract long"]
16453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"]
16454#[inline]
16455#[target_feature(enable = "neon")]
16456#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
16457#[rustc_legacy_const_generics(3)]
16458#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16459pub fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
16460    static_assert_uimm_bits!(N, 2);
16461    vqsubq_s64(a, vqdmull_high_laneq_s32::<N>(b, c))
16462}
16463#[doc = "Signed saturating doubling multiply-subtract long"]
16464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"]
16465#[inline]
16466#[target_feature(enable = "neon")]
16467#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
16468#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16469pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
16470    vqsubq_s32(a, vqdmull_high_n_s16(b, c))
16471}
16472#[doc = "Signed saturating doubling multiply-subtract long"]
16473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"]
16474#[inline]
16475#[target_feature(enable = "neon")]
16476#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
16477#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16478pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
16479    vqsubq_s32(a, vqdmull_high_s16(b, c))
16480}
16481#[doc = "Signed saturating doubling multiply-subtract long"]
16482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"]
16483#[inline]
16484#[target_feature(enable = "neon")]
16485#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
16486#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16487pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
16488    vqsubq_s64(a, vqdmull_high_n_s32(b, c))
16489}
16490#[doc = "Signed saturating doubling multiply-subtract long"]
16491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"]
16492#[inline]
16493#[target_feature(enable = "neon")]
16494#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
16495#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16496pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
16497    vqsubq_s64(a, vqdmull_high_s32(b, c))
16498}
16499#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
16500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"]
16501#[inline]
16502#[target_feature(enable = "neon")]
16503#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 2))]
16504#[rustc_legacy_const_generics(3)]
16505#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16506pub fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
16507    static_assert_uimm_bits!(N, 3);
16508    vqsubq_s32(a, vqdmull_laneq_s16::<N>(b, c))
16509}
16510#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
16511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"]
16512#[inline]
16513#[target_feature(enable = "neon")]
16514#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 1))]
16515#[rustc_legacy_const_generics(3)]
16516#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16517pub fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
16518    static_assert_uimm_bits!(N, 2);
16519    vqsubq_s64(a, vqdmull_laneq_s32::<N>(b, c))
16520}
16521#[doc = "Signed saturating doubling multiply-subtract long"]
16522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"]
16523#[inline]
16524#[target_feature(enable = "neon")]
16525#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
16526#[rustc_legacy_const_generics(3)]
16527#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16528pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
16529    static_assert_uimm_bits!(LANE, 2);
16530    vqdmlslh_s16(a, b, vget_lane_s16::<LANE>(c))
16531}
16532#[doc = "Signed saturating doubling multiply-subtract long"]
16533#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"]
16534#[inline]
16535#[target_feature(enable = "neon")]
16536#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
16537#[rustc_legacy_const_generics(3)]
16538#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16539pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32 {
16540    static_assert_uimm_bits!(LANE, 3);
16541    vqdmlslh_s16(a, b, vgetq_lane_s16::<LANE>(c))
16542}
16543#[doc = "Signed saturating doubling multiply-subtract long"]
16544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"]
16545#[inline]
16546#[target_feature(enable = "neon")]
16547#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
16548#[rustc_legacy_const_generics(3)]
16549#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16550pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
16551    static_assert_uimm_bits!(LANE, 1);
16552    vqdmlsls_s32(a, b, vget_lane_s32::<LANE>(c))
16553}
16554#[doc = "Signed saturating doubling multiply-subtract long"]
16555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"]
16556#[inline]
16557#[target_feature(enable = "neon")]
16558#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, LANE = 0))]
16559#[rustc_legacy_const_generics(3)]
16560#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16561pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64 {
16562    static_assert_uimm_bits!(LANE, 2);
16563    vqdmlsls_s32(a, b, vgetq_lane_s32::<LANE>(c))
16564}
16565#[doc = "Signed saturating doubling multiply-subtract long"]
16566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"]
16567#[inline]
16568#[target_feature(enable = "neon")]
16569#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl))]
16570#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16571pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 {
16572    let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c));
16573    vqsubs_s32(a, vgetq_lane_s32::<0>(x))
16574}
16575#[doc = "Signed saturating doubling multiply-subtract long"]
16576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"]
16577#[inline]
16578#[target_feature(enable = "neon")]
16579#[cfg_attr(test, assert_instr(sqdmlsl))]
16580#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16581pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 {
16582    let x: i64 = vqsubd_s64(a, vqdmulls_s32(b, c));
16583    x
16584}
16585#[doc = "Vector saturating doubling multiply high by scalar"]
16586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"]
16587#[inline]
16588#[target_feature(enable = "neon")]
16589#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
16590#[rustc_legacy_const_generics(2)]
16591#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16592pub fn vqdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
16593    static_assert_uimm_bits!(LANE, 2);
16594    vqdmulh_s16(a, vdup_n_s16(vget_lane_s16::<LANE>(b)))
16595}
16596#[doc = "Vector saturating doubling multiply high by scalar"]
16597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"]
16598#[inline]
16599#[target_feature(enable = "neon")]
16600#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
16601#[rustc_legacy_const_generics(2)]
16602#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16603pub fn vqdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
16604    static_assert_uimm_bits!(LANE, 2);
16605    vqdmulhq_s16(a, vdupq_n_s16(vget_lane_s16::<LANE>(b)))
16606}
16607#[doc = "Vector saturating doubling multiply high by scalar"]
16608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"]
16609#[inline]
16610#[target_feature(enable = "neon")]
16611#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
16612#[rustc_legacy_const_generics(2)]
16613#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16614pub fn vqdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
16615    static_assert_uimm_bits!(LANE, 1);
16616    vqdmulh_s32(a, vdup_n_s32(vget_lane_s32::<LANE>(b)))
16617}
16618#[doc = "Vector saturating doubling multiply high by scalar"]
16619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"]
16620#[inline]
16621#[target_feature(enable = "neon")]
16622#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
16623#[rustc_legacy_const_generics(2)]
16624#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16625pub fn vqdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
16626    static_assert_uimm_bits!(LANE, 1);
16627    vqdmulhq_s32(a, vdupq_n_s32(vget_lane_s32::<LANE>(b)))
16628}
16629#[doc = "Signed saturating doubling multiply returning high half"]
16630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"]
16631#[inline]
16632#[target_feature(enable = "neon")]
16633#[cfg_attr(test, assert_instr(sqdmulh, N = 2))]
16634#[rustc_legacy_const_generics(2)]
16635#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16636pub fn vqdmulhh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i16 {
16637    static_assert_uimm_bits!(N, 2);
16638    let b: i16 = vget_lane_s16::<N>(b);
16639    vqdmulhh_s16(a, b)
16640}
16641#[doc = "Signed saturating doubling multiply returning high half"]
16642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"]
16643#[inline]
16644#[target_feature(enable = "neon")]
16645#[cfg_attr(test, assert_instr(sqdmulh, N = 2))]
16646#[rustc_legacy_const_generics(2)]
16647#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16648pub fn vqdmulhh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i16 {
16649    static_assert_uimm_bits!(N, 3);
16650    let b: i16 = vgetq_lane_s16::<N>(b);
16651    vqdmulhh_s16(a, b)
16652}
16653#[doc = "Signed saturating doubling multiply returning high half"]
16654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"]
16655#[inline]
16656#[target_feature(enable = "neon")]
16657#[cfg_attr(test, assert_instr(sqdmulh))]
16658#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16659pub fn vqdmulhh_s16(a: i16, b: i16) -> i16 {
16660    let a: int16x4_t = vdup_n_s16(a);
16661    let b: int16x4_t = vdup_n_s16(b);
16662    vget_lane_s16::<0>(vqdmulh_s16(a, b))
16663}
16664#[doc = "Signed saturating doubling multiply returning high half"]
16665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"]
16666#[inline]
16667#[target_feature(enable = "neon")]
16668#[cfg_attr(test, assert_instr(sqdmulh))]
16669#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16670pub fn vqdmulhs_s32(a: i32, b: i32) -> i32 {
16671    let a: int32x2_t = vdup_n_s32(a);
16672    let b: int32x2_t = vdup_n_s32(b);
16673    vget_lane_s32::<0>(vqdmulh_s32(a, b))
16674}
16675#[doc = "Signed saturating doubling multiply returning high half"]
16676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"]
16677#[inline]
16678#[target_feature(enable = "neon")]
16679#[cfg_attr(test, assert_instr(sqdmulh, N = 1))]
16680#[rustc_legacy_const_generics(2)]
16681#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16682pub fn vqdmulhs_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i32 {
16683    static_assert_uimm_bits!(N, 1);
16684    let b: i32 = vget_lane_s32::<N>(b);
16685    vqdmulhs_s32(a, b)
16686}
16687#[doc = "Signed saturating doubling multiply returning high half"]
16688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"]
16689#[inline]
16690#[target_feature(enable = "neon")]
16691#[cfg_attr(test, assert_instr(sqdmulh, N = 1))]
16692#[rustc_legacy_const_generics(2)]
16693#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16694pub fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 {
16695    static_assert_uimm_bits!(N, 2);
16696    let b: i32 = vgetq_lane_s32::<N>(b);
16697    vqdmulhs_s32(a, b)
16698}
16699#[doc = "Signed saturating doubling multiply long"]
16700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"]
16701#[inline]
16702#[target_feature(enable = "neon")]
16703#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))]
16704#[rustc_legacy_const_generics(2)]
16705#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16706pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t {
16707    static_assert_uimm_bits!(N, 2);
16708    let a = vget_high_s16(a);
16709    let b = vdup_lane_s16::<N>(b);
16710    vqdmull_s16(a, b)
16711}
16712#[doc = "Signed saturating doubling multiply long"]
16713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"]
16714#[inline]
16715#[target_feature(enable = "neon")]
16716#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))]
16717#[rustc_legacy_const_generics(2)]
16718#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16719pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t {
16720    static_assert_uimm_bits!(N, 2);
16721    let a = vget_high_s32(a);
16722    let b = vdup_laneq_s32::<N>(b);
16723    vqdmull_s32(a, b)
16724}
16725#[doc = "Signed saturating doubling multiply long"]
16726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"]
16727#[inline]
16728#[target_feature(enable = "neon")]
16729#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 1))]
16730#[rustc_legacy_const_generics(2)]
16731#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16732pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t {
16733    static_assert_uimm_bits!(N, 1);
16734    let a = vget_high_s32(a);
16735    let b = vdup_lane_s32::<N>(b);
16736    vqdmull_s32(a, b)
16737}
16738#[doc = "Signed saturating doubling multiply long"]
16739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"]
16740#[inline]
16741#[target_feature(enable = "neon")]
16742#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 4))]
16743#[rustc_legacy_const_generics(2)]
16744#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16745pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t {
16746    static_assert_uimm_bits!(N, 3);
16747    let a = vget_high_s16(a);
16748    let b = vdup_laneq_s16::<N>(b);
16749    vqdmull_s16(a, b)
16750}
16751#[doc = "Signed saturating doubling multiply long"]
16752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"]
16753#[inline]
16754#[target_feature(enable = "neon")]
16755#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
16756#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16757pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
16758    let a = vget_high_s16(a);
16759    let b = vdup_n_s16(b);
16760    vqdmull_s16(a, b)
16761}
16762#[doc = "Signed saturating doubling multiply long"]
16763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"]
16764#[inline]
16765#[target_feature(enable = "neon")]
16766#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
16767#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16768pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
16769    let a = vget_high_s32(a);
16770    let b = vdup_n_s32(b);
16771    vqdmull_s32(a, b)
16772}
16773#[doc = "Signed saturating doubling multiply long"]
16774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"]
16775#[inline]
16776#[target_feature(enable = "neon")]
16777#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
16778#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16779pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
16780    let a = vget_high_s16(a);
16781    let b = vget_high_s16(b);
16782    vqdmull_s16(a, b)
16783}
16784#[doc = "Signed saturating doubling multiply long"]
16785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"]
16786#[inline]
16787#[target_feature(enable = "neon")]
16788#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
16789#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16790pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
16791    let a = vget_high_s32(a);
16792    let b = vget_high_s32(b);
16793    vqdmull_s32(a, b)
16794}
16795#[doc = "Vector saturating doubling long multiply by scalar"]
16796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"]
16797#[inline]
16798#[target_feature(enable = "neon")]
16799#[cfg_attr(test, assert_instr(sqdmull, N = 4))]
16800#[rustc_legacy_const_generics(2)]
16801#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16802pub fn vqdmull_laneq_s16<const N: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t {
16803    static_assert_uimm_bits!(N, 3);
16804    let b = vdup_laneq_s16::<N>(b);
16805    vqdmull_s16(a, b)
16806}
16807#[doc = "Vector saturating doubling long multiply by scalar"]
16808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"]
16809#[inline]
16810#[target_feature(enable = "neon")]
16811#[cfg_attr(test, assert_instr(sqdmull, N = 2))]
16812#[rustc_legacy_const_generics(2)]
16813#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16814pub fn vqdmull_laneq_s32<const N: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t {
16815    static_assert_uimm_bits!(N, 2);
16816    let b = vdup_laneq_s32::<N>(b);
16817    vqdmull_s32(a, b)
16818}
16819#[doc = "Signed saturating doubling multiply long"]
16820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"]
16821#[inline]
16822#[target_feature(enable = "neon")]
16823#[cfg_attr(test, assert_instr(sqdmull, N = 2))]
16824#[rustc_legacy_const_generics(2)]
16825#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16826pub fn vqdmullh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i32 {
16827    static_assert_uimm_bits!(N, 2);
16828    let b: i16 = vget_lane_s16::<N>(b);
16829    vqdmullh_s16(a, b)
16830}
16831#[doc = "Signed saturating doubling multiply long"]
16832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"]
16833#[inline]
16834#[target_feature(enable = "neon")]
16835#[cfg_attr(test, assert_instr(sqdmull, N = 2))]
16836#[rustc_legacy_const_generics(2)]
16837#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16838pub fn vqdmulls_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i64 {
16839    static_assert_uimm_bits!(N, 2);
16840    let b: i32 = vgetq_lane_s32::<N>(b);
16841    vqdmulls_s32(a, b)
16842}
16843#[doc = "Signed saturating doubling multiply long"]
16844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"]
16845#[inline]
16846#[target_feature(enable = "neon")]
16847#[cfg_attr(test, assert_instr(sqdmull, N = 4))]
16848#[rustc_legacy_const_generics(2)]
16849#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16850pub fn vqdmullh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i32 {
16851    static_assert_uimm_bits!(N, 3);
16852    let b: i16 = vgetq_lane_s16::<N>(b);
16853    vqdmullh_s16(a, b)
16854}
16855#[doc = "Signed saturating doubling multiply long"]
16856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"]
16857#[inline]
16858#[target_feature(enable = "neon")]
16859#[cfg_attr(test, assert_instr(sqdmull))]
16860#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16861pub fn vqdmullh_s16(a: i16, b: i16) -> i32 {
16862    let a: int16x4_t = vdup_n_s16(a);
16863    let b: int16x4_t = vdup_n_s16(b);
16864    vgetq_lane_s32::<0>(vqdmull_s16(a, b))
16865}
16866#[doc = "Signed saturating doubling multiply long"]
16867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"]
16868#[inline]
16869#[target_feature(enable = "neon")]
16870#[cfg_attr(test, assert_instr(sqdmull, N = 1))]
16871#[rustc_legacy_const_generics(2)]
16872#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16873pub fn vqdmulls_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i64 {
16874    static_assert_uimm_bits!(N, 1);
16875    let b: i32 = vget_lane_s32::<N>(b);
16876    vqdmulls_s32(a, b)
16877}
16878#[doc = "Signed saturating doubling multiply long"]
16879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"]
16880#[inline]
16881#[target_feature(enable = "neon")]
16882#[cfg_attr(test, assert_instr(sqdmull))]
16883#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16884pub fn vqdmulls_s32(a: i32, b: i32) -> i64 {
16885    unsafe extern "unadjusted" {
16886        #[cfg_attr(
16887            any(target_arch = "aarch64", target_arch = "arm64ec"),
16888            link_name = "llvm.aarch64.neon.sqdmulls.scalar"
16889        )]
16890        fn _vqdmulls_s32(a: i32, b: i32) -> i64;
16891    }
16892    unsafe { _vqdmulls_s32(a, b) }
16893}
16894#[doc = "Signed saturating extract narrow"]
16895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"]
16896#[inline]
16897#[target_feature(enable = "neon")]
16898#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
16899#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16900pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
16901    vcombine_s8(a, vqmovn_s16(b))
16902}
16903#[doc = "Signed saturating extract narrow"]
16904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"]
16905#[inline]
16906#[target_feature(enable = "neon")]
16907#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
16908#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16909pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
16910    vcombine_s16(a, vqmovn_s32(b))
16911}
16912#[doc = "Signed saturating extract narrow"]
16913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"]
16914#[inline]
16915#[target_feature(enable = "neon")]
16916#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
16917#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16918pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
16919    vcombine_s32(a, vqmovn_s64(b))
16920}
16921#[doc = "Signed saturating extract narrow"]
16922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"]
16923#[inline]
16924#[target_feature(enable = "neon")]
16925#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
16926#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16927pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
16928    vcombine_u8(a, vqmovn_u16(b))
16929}
16930#[doc = "Signed saturating extract narrow"]
16931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"]
16932#[inline]
16933#[target_feature(enable = "neon")]
16934#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
16935#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16936pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
16937    vcombine_u16(a, vqmovn_u32(b))
16938}
16939#[doc = "Signed saturating extract narrow"]
16940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"]
16941#[inline]
16942#[target_feature(enable = "neon")]
16943#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
16944#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16945pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
16946    vcombine_u32(a, vqmovn_u64(b))
16947}
16948#[doc = "Saturating extract narrow"]
16949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"]
16950#[inline]
16951#[target_feature(enable = "neon")]
16952#[cfg_attr(test, assert_instr(sqxtn))]
16953#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16954pub fn vqmovnd_s64(a: i64) -> i32 {
16955    unsafe extern "unadjusted" {
16956        #[cfg_attr(
16957            any(target_arch = "aarch64", target_arch = "arm64ec"),
16958            link_name = "llvm.aarch64.neon.scalar.sqxtn.i32.i64"
16959        )]
16960        fn _vqmovnd_s64(a: i64) -> i32;
16961    }
16962    unsafe { _vqmovnd_s64(a) }
16963}
16964#[doc = "Saturating extract narrow"]
16965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64)"]
16966#[inline]
16967#[target_feature(enable = "neon")]
16968#[cfg_attr(test, assert_instr(uqxtn))]
16969#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16970pub fn vqmovnd_u64(a: u64) -> u32 {
16971    unsafe extern "unadjusted" {
16972        #[cfg_attr(
16973            any(target_arch = "aarch64", target_arch = "arm64ec"),
16974            link_name = "llvm.aarch64.neon.scalar.uqxtn.i32.i64"
16975        )]
16976        fn _vqmovnd_u64(a: u64) -> u32;
16977    }
16978    unsafe { _vqmovnd_u64(a) }
16979}
16980#[doc = "Saturating extract narrow"]
16981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16)"]
16982#[inline]
16983#[target_feature(enable = "neon")]
16984#[cfg_attr(test, assert_instr(sqxtn))]
16985#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16986pub fn vqmovnh_s16(a: i16) -> i8 {
16987    vget_lane_s8::<0>(vqmovn_s16(vdupq_n_s16(a)))
16988}
16989#[doc = "Saturating extract narrow"]
16990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"]
16991#[inline]
16992#[target_feature(enable = "neon")]
16993#[cfg_attr(test, assert_instr(sqxtn))]
16994#[stable(feature = "neon_intrinsics", since = "1.59.0")]
16995pub fn vqmovns_s32(a: i32) -> i16 {
16996    vget_lane_s16::<0>(vqmovn_s32(vdupq_n_s32(a)))
16997}
16998#[doc = "Saturating extract narrow"]
16999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"]
17000#[inline]
17001#[target_feature(enable = "neon")]
17002#[cfg_attr(test, assert_instr(uqxtn))]
17003#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17004pub fn vqmovnh_u16(a: u16) -> u8 {
17005    vget_lane_u8::<0>(vqmovn_u16(vdupq_n_u16(a)))
17006}
17007#[doc = "Saturating extract narrow"]
17008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"]
17009#[inline]
17010#[target_feature(enable = "neon")]
17011#[cfg_attr(test, assert_instr(uqxtn))]
17012#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17013pub fn vqmovns_u32(a: u32) -> u16 {
17014    vget_lane_u16::<0>(vqmovn_u32(vdupq_n_u32(a)))
17015}
17016#[doc = "Signed saturating extract unsigned narrow"]
17017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"]
17018#[inline]
17019#[target_feature(enable = "neon")]
17020#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
17021#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17022pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
17023    vcombine_u8(a, vqmovun_s16(b))
17024}
17025#[doc = "Signed saturating extract unsigned narrow"]
17026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"]
17027#[inline]
17028#[target_feature(enable = "neon")]
17029#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
17030#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17031pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
17032    vcombine_u16(a, vqmovun_s32(b))
17033}
17034#[doc = "Signed saturating extract unsigned narrow"]
17035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"]
17036#[inline]
17037#[target_feature(enable = "neon")]
17038#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
17039#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17040pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
17041    vcombine_u32(a, vqmovun_s64(b))
17042}
17043#[doc = "Signed saturating extract unsigned narrow"]
17044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"]
17045#[inline]
17046#[target_feature(enable = "neon")]
17047#[cfg_attr(test, assert_instr(sqxtun))]
17048#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17049pub fn vqmovunh_s16(a: i16) -> u8 {
17050    vget_lane_u8::<0>(vqmovun_s16(vdupq_n_s16(a)))
17051}
17052#[doc = "Signed saturating extract unsigned narrow"]
17053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"]
17054#[inline]
17055#[target_feature(enable = "neon")]
17056#[cfg_attr(test, assert_instr(sqxtun))]
17057#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17058pub fn vqmovuns_s32(a: i32) -> u16 {
17059    vget_lane_u16::<0>(vqmovun_s32(vdupq_n_s32(a)))
17060}
17061#[doc = "Signed saturating extract unsigned narrow"]
17062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"]
17063#[inline]
17064#[target_feature(enable = "neon")]
17065#[cfg_attr(test, assert_instr(sqxtun))]
17066#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17067pub fn vqmovund_s64(a: i64) -> u32 {
17068    vget_lane_u32::<0>(vqmovun_s64(vdupq_n_s64(a)))
17069}
17070#[doc = "Signed saturating negate"]
17071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"]
17072#[inline]
17073#[target_feature(enable = "neon")]
17074#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17075#[cfg_attr(test, assert_instr(sqneg))]
17076pub fn vqneg_s64(a: int64x1_t) -> int64x1_t {
17077    unsafe extern "unadjusted" {
17078        #[cfg_attr(
17079            any(target_arch = "aarch64", target_arch = "arm64ec"),
17080            link_name = "llvm.aarch64.neon.sqneg.v1i64"
17081        )]
17082        fn _vqneg_s64(a: int64x1_t) -> int64x1_t;
17083    }
17084    unsafe { _vqneg_s64(a) }
17085}
17086#[doc = "Signed saturating negate"]
17087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)"]
17088#[inline]
17089#[target_feature(enable = "neon")]
17090#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17091#[cfg_attr(test, assert_instr(sqneg))]
17092pub fn vqnegq_s64(a: int64x2_t) -> int64x2_t {
17093    unsafe extern "unadjusted" {
17094        #[cfg_attr(
17095            any(target_arch = "aarch64", target_arch = "arm64ec"),
17096            link_name = "llvm.aarch64.neon.sqneg.v2i64"
17097        )]
17098        fn _vqnegq_s64(a: int64x2_t) -> int64x2_t;
17099    }
17100    unsafe { _vqnegq_s64(a) }
17101}
17102#[doc = "Signed saturating negate"]
17103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)"]
17104#[inline]
17105#[target_feature(enable = "neon")]
17106#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17107#[cfg_attr(test, assert_instr(sqneg))]
17108pub fn vqnegb_s8(a: i8) -> i8 {
17109    vget_lane_s8::<0>(vqneg_s8(vdup_n_s8(a)))
17110}
17111#[doc = "Signed saturating negate"]
17112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"]
17113#[inline]
17114#[target_feature(enable = "neon")]
17115#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17116#[cfg_attr(test, assert_instr(sqneg))]
17117pub fn vqnegh_s16(a: i16) -> i16 {
17118    vget_lane_s16::<0>(vqneg_s16(vdup_n_s16(a)))
17119}
17120#[doc = "Signed saturating negate"]
17121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"]
17122#[inline]
17123#[target_feature(enable = "neon")]
17124#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17125#[cfg_attr(test, assert_instr(sqneg))]
17126pub fn vqnegs_s32(a: i32) -> i32 {
17127    vget_lane_s32::<0>(vqneg_s32(vdup_n_s32(a)))
17128}
17129#[doc = "Signed saturating negate"]
17130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"]
17131#[inline]
17132#[target_feature(enable = "neon")]
17133#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17134#[cfg_attr(test, assert_instr(sqneg))]
17135pub fn vqnegd_s64(a: i64) -> i64 {
17136    vget_lane_s64::<0>(vqneg_s64(vdup_n_s64(a)))
17137}
17138#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"]
17140#[inline]
17141#[target_feature(enable = "rdm")]
17142#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17143#[rustc_legacy_const_generics(3)]
17144#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17145pub fn vqrdmlah_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
17146    static_assert_uimm_bits!(LANE, 2);
17147    let c = vdup_lane_s16::<LANE>(c);
17148    vqrdmlah_s16(a, b, c)
17149}
17150#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"]
17152#[inline]
17153#[target_feature(enable = "rdm")]
17154#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17155#[rustc_legacy_const_generics(3)]
17156#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17157pub fn vqrdmlah_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
17158    static_assert_uimm_bits!(LANE, 1);
17159    let c = vdup_lane_s32::<LANE>(c);
17160    vqrdmlah_s32(a, b, c)
17161}
17162#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"]
17164#[inline]
17165#[target_feature(enable = "rdm")]
17166#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17167#[rustc_legacy_const_generics(3)]
17168#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17169pub fn vqrdmlah_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
17170    static_assert_uimm_bits!(LANE, 3);
17171    let c = vdup_laneq_s16::<LANE>(c);
17172    vqrdmlah_s16(a, b, c)
17173}
17174#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"]
17176#[inline]
17177#[target_feature(enable = "rdm")]
17178#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17179#[rustc_legacy_const_generics(3)]
17180#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17181pub fn vqrdmlah_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
17182    static_assert_uimm_bits!(LANE, 2);
17183    let c = vdup_laneq_s32::<LANE>(c);
17184    vqrdmlah_s32(a, b, c)
17185}
17186#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"]
17188#[inline]
17189#[target_feature(enable = "rdm")]
17190#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17191#[rustc_legacy_const_generics(3)]
17192#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17193pub fn vqrdmlahq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
17194    static_assert_uimm_bits!(LANE, 2);
17195    let c = vdupq_lane_s16::<LANE>(c);
17196    vqrdmlahq_s16(a, b, c)
17197}
17198#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"]
17200#[inline]
17201#[target_feature(enable = "rdm")]
17202#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17203#[rustc_legacy_const_generics(3)]
17204#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17205pub fn vqrdmlahq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
17206    static_assert_uimm_bits!(LANE, 1);
17207    let c = vdupq_lane_s32::<LANE>(c);
17208    vqrdmlahq_s32(a, b, c)
17209}
17210#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"]
17212#[inline]
17213#[target_feature(enable = "rdm")]
17214#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17215#[rustc_legacy_const_generics(3)]
17216#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17217pub fn vqrdmlahq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
17218    static_assert_uimm_bits!(LANE, 3);
17219    let c = vdupq_laneq_s16::<LANE>(c);
17220    vqrdmlahq_s16(a, b, c)
17221}
17222#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"]
17224#[inline]
17225#[target_feature(enable = "rdm")]
17226#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17227#[rustc_legacy_const_generics(3)]
17228#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17229pub fn vqrdmlahq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
17230    static_assert_uimm_bits!(LANE, 2);
17231    let c = vdupq_laneq_s32::<LANE>(c);
17232    vqrdmlahq_s32(a, b, c)
17233}
17234#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"]
17236#[inline]
17237#[target_feature(enable = "rdm")]
17238#[cfg_attr(test, assert_instr(sqrdmlah))]
17239#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17240pub fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
17241    unsafe extern "unadjusted" {
17242        #[cfg_attr(
17243            any(target_arch = "aarch64", target_arch = "arm64ec"),
17244            link_name = "llvm.aarch64.neon.sqrdmlah.v4i16"
17245        )]
17246        fn _vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
17247    }
17248    unsafe { _vqrdmlah_s16(a, b, c) }
17249}
17250#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16)"]
17252#[inline]
17253#[target_feature(enable = "rdm")]
17254#[cfg_attr(test, assert_instr(sqrdmlah))]
17255#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17256pub fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
17257    unsafe extern "unadjusted" {
17258        #[cfg_attr(
17259            any(target_arch = "aarch64", target_arch = "arm64ec"),
17260            link_name = "llvm.aarch64.neon.sqrdmlah.v8i16"
17261        )]
17262        fn _vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
17263    }
17264    unsafe { _vqrdmlahq_s16(a, b, c) }
17265}
17266#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32)"]
17268#[inline]
17269#[target_feature(enable = "rdm")]
17270#[cfg_attr(test, assert_instr(sqrdmlah))]
17271#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17272pub fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
17273    unsafe extern "unadjusted" {
17274        #[cfg_attr(
17275            any(target_arch = "aarch64", target_arch = "arm64ec"),
17276            link_name = "llvm.aarch64.neon.sqrdmlah.v2i32"
17277        )]
17278        fn _vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
17279    }
17280    unsafe { _vqrdmlah_s32(a, b, c) }
17281}
17282#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32)"]
17284#[inline]
17285#[target_feature(enable = "rdm")]
17286#[cfg_attr(test, assert_instr(sqrdmlah))]
17287#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17288pub fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
17289    unsafe extern "unadjusted" {
17290        #[cfg_attr(
17291            any(target_arch = "aarch64", target_arch = "arm64ec"),
17292            link_name = "llvm.aarch64.neon.sqrdmlah.v4i32"
17293        )]
17294        fn _vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
17295    }
17296    unsafe { _vqrdmlahq_s32(a, b, c) }
17297}
17298#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16)"]
17300#[inline]
17301#[target_feature(enable = "rdm")]
17302#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17303#[rustc_legacy_const_generics(3)]
17304#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17305pub fn vqrdmlahh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16 {
17306    static_assert_uimm_bits!(LANE, 2);
17307    vqrdmlahh_s16(a, b, vget_lane_s16::<LANE>(c))
17308}
17309#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"]
17311#[inline]
17312#[target_feature(enable = "rdm")]
17313#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17314#[rustc_legacy_const_generics(3)]
17315#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17316pub fn vqrdmlahh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16 {
17317    static_assert_uimm_bits!(LANE, 3);
17318    vqrdmlahh_s16(a, b, vgetq_lane_s16::<LANE>(c))
17319}
17320#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"]
17322#[inline]
17323#[target_feature(enable = "rdm")]
17324#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17325#[rustc_legacy_const_generics(3)]
17326#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17327pub fn vqrdmlahs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32 {
17328    static_assert_uimm_bits!(LANE, 1);
17329    vqrdmlahs_s32(a, b, vget_lane_s32::<LANE>(c))
17330}
17331#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"]
17333#[inline]
17334#[target_feature(enable = "rdm")]
17335#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
17336#[rustc_legacy_const_generics(3)]
17337#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17338pub fn vqrdmlahs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32 {
17339    static_assert_uimm_bits!(LANE, 2);
17340    vqrdmlahs_s32(a, b, vgetq_lane_s32::<LANE>(c))
17341}
17342#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"]
17344#[inline]
17345#[target_feature(enable = "rdm")]
17346#[cfg_attr(test, assert_instr(sqrdmlah))]
17347#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17348pub fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 {
17349    let a: int16x4_t = vdup_n_s16(a);
17350    let b: int16x4_t = vdup_n_s16(b);
17351    let c: int16x4_t = vdup_n_s16(c);
17352    vget_lane_s16::<0>(vqrdmlah_s16(a, b, c))
17353}
17354#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
17355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"]
17356#[inline]
17357#[target_feature(enable = "rdm")]
17358#[cfg_attr(test, assert_instr(sqrdmlah))]
17359#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17360pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 {
17361    let a: int32x2_t = vdup_n_s32(a);
17362    let b: int32x2_t = vdup_n_s32(b);
17363    let c: int32x2_t = vdup_n_s32(c);
17364    vget_lane_s32::<0>(vqrdmlah_s32(a, b, c))
17365}
17366#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"]
17368#[inline]
17369#[target_feature(enable = "rdm")]
17370#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17371#[rustc_legacy_const_generics(3)]
17372#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17373pub fn vqrdmlsh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
17374    static_assert_uimm_bits!(LANE, 2);
17375    let c = vdup_lane_s16::<LANE>(c);
17376    vqrdmlsh_s16(a, b, c)
17377}
17378#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"]
17380#[inline]
17381#[target_feature(enable = "rdm")]
17382#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17383#[rustc_legacy_const_generics(3)]
17384#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17385pub fn vqrdmlsh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
17386    static_assert_uimm_bits!(LANE, 1);
17387    let c = vdup_lane_s32::<LANE>(c);
17388    vqrdmlsh_s32(a, b, c)
17389}
17390#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"]
17392#[inline]
17393#[target_feature(enable = "rdm")]
17394#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17395#[rustc_legacy_const_generics(3)]
17396#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17397pub fn vqrdmlsh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
17398    static_assert_uimm_bits!(LANE, 3);
17399    let c = vdup_laneq_s16::<LANE>(c);
17400    vqrdmlsh_s16(a, b, c)
17401}
17402#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"]
17404#[inline]
17405#[target_feature(enable = "rdm")]
17406#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17407#[rustc_legacy_const_generics(3)]
17408#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17409pub fn vqrdmlsh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
17410    static_assert_uimm_bits!(LANE, 2);
17411    let c = vdup_laneq_s32::<LANE>(c);
17412    vqrdmlsh_s32(a, b, c)
17413}
17414#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"]
17416#[inline]
17417#[target_feature(enable = "rdm")]
17418#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17419#[rustc_legacy_const_generics(3)]
17420#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17421pub fn vqrdmlshq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
17422    static_assert_uimm_bits!(LANE, 2);
17423    let c = vdupq_lane_s16::<LANE>(c);
17424    vqrdmlshq_s16(a, b, c)
17425}
17426#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"]
17428#[inline]
17429#[target_feature(enable = "rdm")]
17430#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17431#[rustc_legacy_const_generics(3)]
17432#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17433pub fn vqrdmlshq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
17434    static_assert_uimm_bits!(LANE, 1);
17435    let c = vdupq_lane_s32::<LANE>(c);
17436    vqrdmlshq_s32(a, b, c)
17437}
17438#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"]
17440#[inline]
17441#[target_feature(enable = "rdm")]
17442#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17443#[rustc_legacy_const_generics(3)]
17444#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17445pub fn vqrdmlshq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
17446    static_assert_uimm_bits!(LANE, 3);
17447    let c = vdupq_laneq_s16::<LANE>(c);
17448    vqrdmlshq_s16(a, b, c)
17449}
17450#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"]
17452#[inline]
17453#[target_feature(enable = "rdm")]
17454#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17455#[rustc_legacy_const_generics(3)]
17456#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17457pub fn vqrdmlshq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
17458    static_assert_uimm_bits!(LANE, 2);
17459    let c = vdupq_laneq_s32::<LANE>(c);
17460    vqrdmlshq_s32(a, b, c)
17461}
17462#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"]
17464#[inline]
17465#[target_feature(enable = "rdm")]
17466#[cfg_attr(test, assert_instr(sqrdmlsh))]
17467#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17468pub fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
17469    unsafe extern "unadjusted" {
17470        #[cfg_attr(
17471            any(target_arch = "aarch64", target_arch = "arm64ec"),
17472            link_name = "llvm.aarch64.neon.sqrdmlsh.v4i16"
17473        )]
17474        fn _vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
17475    }
17476    unsafe { _vqrdmlsh_s16(a, b, c) }
17477}
17478#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16)"]
17480#[inline]
17481#[target_feature(enable = "rdm")]
17482#[cfg_attr(test, assert_instr(sqrdmlsh))]
17483#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17484pub fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
17485    unsafe extern "unadjusted" {
17486        #[cfg_attr(
17487            any(target_arch = "aarch64", target_arch = "arm64ec"),
17488            link_name = "llvm.aarch64.neon.sqrdmlsh.v8i16"
17489        )]
17490        fn _vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
17491    }
17492    unsafe { _vqrdmlshq_s16(a, b, c) }
17493}
17494#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32)"]
17496#[inline]
17497#[target_feature(enable = "rdm")]
17498#[cfg_attr(test, assert_instr(sqrdmlsh))]
17499#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17500pub fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
17501    unsafe extern "unadjusted" {
17502        #[cfg_attr(
17503            any(target_arch = "aarch64", target_arch = "arm64ec"),
17504            link_name = "llvm.aarch64.neon.sqrdmlsh.v2i32"
17505        )]
17506        fn _vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
17507    }
17508    unsafe { _vqrdmlsh_s32(a, b, c) }
17509}
17510#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32)"]
17512#[inline]
17513#[target_feature(enable = "rdm")]
17514#[cfg_attr(test, assert_instr(sqrdmlsh))]
17515#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17516pub fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
17517    unsafe extern "unadjusted" {
17518        #[cfg_attr(
17519            any(target_arch = "aarch64", target_arch = "arm64ec"),
17520            link_name = "llvm.aarch64.neon.sqrdmlsh.v4i32"
17521        )]
17522        fn _vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
17523    }
17524    unsafe { _vqrdmlshq_s32(a, b, c) }
17525}
17526#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16)"]
17528#[inline]
17529#[target_feature(enable = "rdm")]
17530#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17531#[rustc_legacy_const_generics(3)]
17532#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17533pub fn vqrdmlshh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16 {
17534    static_assert_uimm_bits!(LANE, 2);
17535    vqrdmlshh_s16(a, b, vget_lane_s16::<LANE>(c))
17536}
17537#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"]
17539#[inline]
17540#[target_feature(enable = "rdm")]
17541#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17542#[rustc_legacy_const_generics(3)]
17543#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17544pub fn vqrdmlshh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16 {
17545    static_assert_uimm_bits!(LANE, 3);
17546    vqrdmlshh_s16(a, b, vgetq_lane_s16::<LANE>(c))
17547}
17548#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"]
17550#[inline]
17551#[target_feature(enable = "rdm")]
17552#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17553#[rustc_legacy_const_generics(3)]
17554#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17555pub fn vqrdmlshs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32 {
17556    static_assert_uimm_bits!(LANE, 1);
17557    vqrdmlshs_s32(a, b, vget_lane_s32::<LANE>(c))
17558}
17559#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"]
17561#[inline]
17562#[target_feature(enable = "rdm")]
17563#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
17564#[rustc_legacy_const_generics(3)]
17565#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17566pub fn vqrdmlshs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32 {
17567    static_assert_uimm_bits!(LANE, 2);
17568    vqrdmlshs_s32(a, b, vgetq_lane_s32::<LANE>(c))
17569}
17570#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"]
17572#[inline]
17573#[target_feature(enable = "rdm")]
17574#[cfg_attr(test, assert_instr(sqrdmlsh))]
17575#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17576pub fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 {
17577    let a: int16x4_t = vdup_n_s16(a);
17578    let b: int16x4_t = vdup_n_s16(b);
17579    let c: int16x4_t = vdup_n_s16(c);
17580    vget_lane_s16::<0>(vqrdmlsh_s16(a, b, c))
17581}
17582#[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
17583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"]
17584#[inline]
17585#[target_feature(enable = "rdm")]
17586#[cfg_attr(test, assert_instr(sqrdmlsh))]
17587#[stable(feature = "rdm_intrinsics", since = "1.62.0")]
17588pub fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 {
17589    let a: int32x2_t = vdup_n_s32(a);
17590    let b: int32x2_t = vdup_n_s32(b);
17591    let c: int32x2_t = vdup_n_s32(c);
17592    vget_lane_s32::<0>(vqrdmlsh_s32(a, b, c))
17593}
17594#[doc = "Signed saturating rounding doubling multiply returning high half"]
17595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"]
17596#[inline]
17597#[target_feature(enable = "neon")]
17598#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
17599#[rustc_legacy_const_generics(2)]
17600#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17601pub fn vqrdmulhh_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> i16 {
17602    static_assert_uimm_bits!(LANE, 2);
17603    vqrdmulhh_s16(a, vget_lane_s16::<LANE>(b))
17604}
17605#[doc = "Signed saturating rounding doubling multiply returning high half"]
17606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"]
17607#[inline]
17608#[target_feature(enable = "neon")]
17609#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
17610#[rustc_legacy_const_generics(2)]
17611#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17612pub fn vqrdmulhh_laneq_s16<const LANE: i32>(a: i16, b: int16x8_t) -> i16 {
17613    static_assert_uimm_bits!(LANE, 3);
17614    vqrdmulhh_s16(a, vgetq_lane_s16::<LANE>(b))
17615}
17616#[doc = "Signed saturating rounding doubling multiply returning high half"]
17617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"]
17618#[inline]
17619#[target_feature(enable = "neon")]
17620#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
17621#[rustc_legacy_const_generics(2)]
17622#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17623pub fn vqrdmulhs_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> i32 {
17624    static_assert_uimm_bits!(LANE, 1);
17625    vqrdmulhs_s32(a, vget_lane_s32::<LANE>(b))
17626}
17627#[doc = "Signed saturating rounding doubling multiply returning high half"]
17628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"]
17629#[inline]
17630#[target_feature(enable = "neon")]
17631#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
17632#[rustc_legacy_const_generics(2)]
17633#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17634pub fn vqrdmulhs_laneq_s32<const LANE: i32>(a: i32, b: int32x4_t) -> i32 {
17635    static_assert_uimm_bits!(LANE, 2);
17636    vqrdmulhs_s32(a, vgetq_lane_s32::<LANE>(b))
17637}
17638#[doc = "Signed saturating rounding doubling multiply returning high half"]
17639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"]
17640#[inline]
17641#[target_feature(enable = "neon")]
17642#[cfg_attr(test, assert_instr(sqrdmulh))]
17643#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17644pub fn vqrdmulhh_s16(a: i16, b: i16) -> i16 {
17645    vget_lane_s16::<0>(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)))
17646}
17647#[doc = "Signed saturating rounding doubling multiply returning high half"]
17648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"]
17649#[inline]
17650#[target_feature(enable = "neon")]
17651#[cfg_attr(test, assert_instr(sqrdmulh))]
17652#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17653pub fn vqrdmulhs_s32(a: i32, b: i32) -> i32 {
17654    vget_lane_s32::<0>(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)))
17655}
17656#[doc = "Signed saturating rounding shift left"]
17657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"]
17658#[inline]
17659#[target_feature(enable = "neon")]
17660#[cfg_attr(test, assert_instr(sqrshl))]
17661#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17662pub fn vqrshlb_s8(a: i8, b: i8) -> i8 {
17663    let a: int8x8_t = vdup_n_s8(a);
17664    let b: int8x8_t = vdup_n_s8(b);
17665    vget_lane_s8::<0>(vqrshl_s8(a, b))
17666}
17667#[doc = "Signed saturating rounding shift left"]
17668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"]
17669#[inline]
17670#[target_feature(enable = "neon")]
17671#[cfg_attr(test, assert_instr(sqrshl))]
17672#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17673pub fn vqrshlh_s16(a: i16, b: i16) -> i16 {
17674    let a: int16x4_t = vdup_n_s16(a);
17675    let b: int16x4_t = vdup_n_s16(b);
17676    vget_lane_s16::<0>(vqrshl_s16(a, b))
17677}
17678#[doc = "Unsigned signed saturating rounding shift left"]
17679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"]
17680#[inline]
17681#[target_feature(enable = "neon")]
17682#[cfg_attr(test, assert_instr(uqrshl))]
17683#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17684pub fn vqrshlb_u8(a: u8, b: i8) -> u8 {
17685    let a: uint8x8_t = vdup_n_u8(a);
17686    let b: int8x8_t = vdup_n_s8(b);
17687    vget_lane_u8::<0>(vqrshl_u8(a, b))
17688}
17689#[doc = "Unsigned signed saturating rounding shift left"]
17690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"]
17691#[inline]
17692#[target_feature(enable = "neon")]
17693#[cfg_attr(test, assert_instr(uqrshl))]
17694#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17695pub fn vqrshlh_u16(a: u16, b: i16) -> u16 {
17696    let a: uint16x4_t = vdup_n_u16(a);
17697    let b: int16x4_t = vdup_n_s16(b);
17698    vget_lane_u16::<0>(vqrshl_u16(a, b))
17699}
17700#[doc = "Signed saturating rounding shift left"]
17701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"]
17702#[inline]
17703#[target_feature(enable = "neon")]
17704#[cfg_attr(test, assert_instr(sqrshl))]
17705#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17706pub fn vqrshld_s64(a: i64, b: i64) -> i64 {
17707    unsafe extern "unadjusted" {
17708        #[cfg_attr(
17709            any(target_arch = "aarch64", target_arch = "arm64ec"),
17710            link_name = "llvm.aarch64.neon.sqrshl.i64"
17711        )]
17712        fn _vqrshld_s64(a: i64, b: i64) -> i64;
17713    }
17714    unsafe { _vqrshld_s64(a, b) }
17715}
17716#[doc = "Signed saturating rounding shift left"]
17717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)"]
17718#[inline]
17719#[target_feature(enable = "neon")]
17720#[cfg_attr(test, assert_instr(sqrshl))]
17721#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17722pub fn vqrshls_s32(a: i32, b: i32) -> i32 {
17723    unsafe extern "unadjusted" {
17724        #[cfg_attr(
17725            any(target_arch = "aarch64", target_arch = "arm64ec"),
17726            link_name = "llvm.aarch64.neon.sqrshl.i32"
17727        )]
17728        fn _vqrshls_s32(a: i32, b: i32) -> i32;
17729    }
17730    unsafe { _vqrshls_s32(a, b) }
17731}
17732#[doc = "Unsigned signed saturating rounding shift left"]
17733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)"]
17734#[inline]
17735#[target_feature(enable = "neon")]
17736#[cfg_attr(test, assert_instr(uqrshl))]
17737#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17738pub fn vqrshls_u32(a: u32, b: i32) -> u32 {
17739    unsafe extern "unadjusted" {
17740        #[cfg_attr(
17741            any(target_arch = "aarch64", target_arch = "arm64ec"),
17742            link_name = "llvm.aarch64.neon.uqrshl.i32"
17743        )]
17744        fn _vqrshls_u32(a: u32, b: i32) -> u32;
17745    }
17746    unsafe { _vqrshls_u32(a, b) }
17747}
17748#[doc = "Unsigned signed saturating rounding shift left"]
17749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64)"]
17750#[inline]
17751#[target_feature(enable = "neon")]
17752#[cfg_attr(test, assert_instr(uqrshl))]
17753#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17754pub fn vqrshld_u64(a: u64, b: i64) -> u64 {
17755    unsafe extern "unadjusted" {
17756        #[cfg_attr(
17757            any(target_arch = "aarch64", target_arch = "arm64ec"),
17758            link_name = "llvm.aarch64.neon.uqrshl.i64"
17759        )]
17760        fn _vqrshld_u64(a: u64, b: i64) -> u64;
17761    }
17762    unsafe { _vqrshld_u64(a, b) }
17763}
17764#[doc = "Signed saturating rounded shift right narrow"]
17765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"]
17766#[inline]
17767#[target_feature(enable = "neon")]
17768#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))]
17769#[rustc_legacy_const_generics(2)]
17770#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17771pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
17772    static_assert!(N >= 1 && N <= 8);
17773    vcombine_s8(a, vqrshrn_n_s16::<N>(b))
17774}
17775#[doc = "Signed saturating rounded shift right narrow"]
17776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"]
17777#[inline]
17778#[target_feature(enable = "neon")]
17779#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))]
17780#[rustc_legacy_const_generics(2)]
17781#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17782pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
17783    static_assert!(N >= 1 && N <= 16);
17784    vcombine_s16(a, vqrshrn_n_s32::<N>(b))
17785}
17786#[doc = "Signed saturating rounded shift right narrow"]
17787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"]
17788#[inline]
17789#[target_feature(enable = "neon")]
17790#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))]
17791#[rustc_legacy_const_generics(2)]
17792#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17793pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
17794    static_assert!(N >= 1 && N <= 32);
17795    vcombine_s32(a, vqrshrn_n_s64::<N>(b))
17796}
17797#[doc = "Unsigned saturating rounded shift right narrow"]
17798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"]
17799#[inline]
17800#[target_feature(enable = "neon")]
17801#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))]
17802#[rustc_legacy_const_generics(2)]
17803#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17804pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
17805    static_assert!(N >= 1 && N <= 8);
17806    vcombine_u8(a, vqrshrn_n_u16::<N>(b))
17807}
17808#[doc = "Unsigned saturating rounded shift right narrow"]
17809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"]
17810#[inline]
17811#[target_feature(enable = "neon")]
17812#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))]
17813#[rustc_legacy_const_generics(2)]
17814#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17815pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
17816    static_assert!(N >= 1 && N <= 16);
17817    vcombine_u16(a, vqrshrn_n_u32::<N>(b))
17818}
17819#[doc = "Unsigned saturating rounded shift right narrow"]
17820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"]
17821#[inline]
17822#[target_feature(enable = "neon")]
17823#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))]
17824#[rustc_legacy_const_generics(2)]
17825#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17826pub fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
17827    static_assert!(N >= 1 && N <= 32);
17828    vcombine_u32(a, vqrshrn_n_u64::<N>(b))
17829}
17830#[doc = "Unsigned saturating rounded shift right narrow"]
17831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"]
17832#[inline]
17833#[target_feature(enable = "neon")]
17834#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
17835#[rustc_legacy_const_generics(1)]
17836#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17837pub fn vqrshrnd_n_u64<const N: i32>(a: u64) -> u32 {
17838    static_assert!(N >= 1 && N <= 32);
17839    let a: uint64x2_t = vdupq_n_u64(a);
17840    vget_lane_u32::<0>(vqrshrn_n_u64::<N>(a))
17841}
17842#[doc = "Unsigned saturating rounded shift right narrow"]
17843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"]
17844#[inline]
17845#[target_feature(enable = "neon")]
17846#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
17847#[rustc_legacy_const_generics(1)]
17848#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17849pub fn vqrshrnh_n_u16<const N: i32>(a: u16) -> u8 {
17850    static_assert!(N >= 1 && N <= 8);
17851    let a: uint16x8_t = vdupq_n_u16(a);
17852    vget_lane_u8::<0>(vqrshrn_n_u16::<N>(a))
17853}
17854#[doc = "Unsigned saturating rounded shift right narrow"]
17855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"]
17856#[inline]
17857#[target_feature(enable = "neon")]
17858#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
17859#[rustc_legacy_const_generics(1)]
17860#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17861pub fn vqrshrns_n_u32<const N: i32>(a: u32) -> u16 {
17862    static_assert!(N >= 1 && N <= 16);
17863    let a: uint32x4_t = vdupq_n_u32(a);
17864    vget_lane_u16::<0>(vqrshrn_n_u32::<N>(a))
17865}
17866#[doc = "Signed saturating rounded shift right narrow"]
17867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"]
17868#[inline]
17869#[target_feature(enable = "neon")]
17870#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
17871#[rustc_legacy_const_generics(1)]
17872#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17873pub fn vqrshrnh_n_s16<const N: i32>(a: i16) -> i8 {
17874    static_assert!(N >= 1 && N <= 8);
17875    let a: int16x8_t = vdupq_n_s16(a);
17876    vget_lane_s8::<0>(vqrshrn_n_s16::<N>(a))
17877}
17878#[doc = "Signed saturating rounded shift right narrow"]
17879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"]
17880#[inline]
17881#[target_feature(enable = "neon")]
17882#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
17883#[rustc_legacy_const_generics(1)]
17884#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17885pub fn vqrshrns_n_s32<const N: i32>(a: i32) -> i16 {
17886    static_assert!(N >= 1 && N <= 16);
17887    let a: int32x4_t = vdupq_n_s32(a);
17888    vget_lane_s16::<0>(vqrshrn_n_s32::<N>(a))
17889}
17890#[doc = "Signed saturating rounded shift right narrow"]
17891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"]
17892#[inline]
17893#[target_feature(enable = "neon")]
17894#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
17895#[rustc_legacy_const_generics(1)]
17896#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17897pub fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 {
17898    static_assert!(N >= 1 && N <= 32);
17899    let a: int64x2_t = vdupq_n_s64(a);
17900    vget_lane_s32::<0>(vqrshrn_n_s64::<N>(a))
17901}
17902#[doc = "Signed saturating rounded shift right unsigned narrow"]
17903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"]
17904#[inline]
17905#[target_feature(enable = "neon")]
17906#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))]
17907#[rustc_legacy_const_generics(2)]
17908#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17909pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
17910    static_assert!(N >= 1 && N <= 8);
17911    vcombine_u8(a, vqrshrun_n_s16::<N>(b))
17912}
17913#[doc = "Signed saturating rounded shift right unsigned narrow"]
17914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"]
17915#[inline]
17916#[target_feature(enable = "neon")]
17917#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))]
17918#[rustc_legacy_const_generics(2)]
17919#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17920pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
17921    static_assert!(N >= 1 && N <= 16);
17922    vcombine_u16(a, vqrshrun_n_s32::<N>(b))
17923}
17924#[doc = "Signed saturating rounded shift right unsigned narrow"]
17925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"]
17926#[inline]
17927#[target_feature(enable = "neon")]
17928#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))]
17929#[rustc_legacy_const_generics(2)]
17930#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17931pub fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
17932    static_assert!(N >= 1 && N <= 32);
17933    vcombine_u32(a, vqrshrun_n_s64::<N>(b))
17934}
17935#[doc = "Signed saturating rounded shift right unsigned narrow"]
17936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"]
17937#[inline]
17938#[target_feature(enable = "neon")]
17939#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
17940#[rustc_legacy_const_generics(1)]
17941#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17942pub fn vqrshrund_n_s64<const N: i32>(a: i64) -> u32 {
17943    static_assert!(N >= 1 && N <= 32);
17944    let a: int64x2_t = vdupq_n_s64(a);
17945    vget_lane_u32::<0>(vqrshrun_n_s64::<N>(a))
17946}
17947#[doc = "Signed saturating rounded shift right unsigned narrow"]
17948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"]
17949#[inline]
17950#[target_feature(enable = "neon")]
17951#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
17952#[rustc_legacy_const_generics(1)]
17953#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17954pub fn vqrshrunh_n_s16<const N: i32>(a: i16) -> u8 {
17955    static_assert!(N >= 1 && N <= 8);
17956    let a: int16x8_t = vdupq_n_s16(a);
17957    vget_lane_u8::<0>(vqrshrun_n_s16::<N>(a))
17958}
17959#[doc = "Signed saturating rounded shift right unsigned narrow"]
17960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"]
17961#[inline]
17962#[target_feature(enable = "neon")]
17963#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
17964#[rustc_legacy_const_generics(1)]
17965#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17966pub fn vqrshruns_n_s32<const N: i32>(a: i32) -> u16 {
17967    static_assert!(N >= 1 && N <= 16);
17968    let a: int32x4_t = vdupq_n_s32(a);
17969    vget_lane_u16::<0>(vqrshrun_n_s32::<N>(a))
17970}
17971#[doc = "Signed saturating shift left"]
17972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"]
17973#[inline]
17974#[target_feature(enable = "neon")]
17975#[cfg_attr(test, assert_instr(sqshl, N = 2))]
17976#[rustc_legacy_const_generics(1)]
17977#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17978pub fn vqshlb_n_s8<const N: i32>(a: i8) -> i8 {
17979    static_assert_uimm_bits!(N, 3);
17980    vget_lane_s8::<0>(vqshl_n_s8::<N>(vdup_n_s8(a)))
17981}
17982#[doc = "Signed saturating shift left"]
17983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"]
17984#[inline]
17985#[target_feature(enable = "neon")]
17986#[cfg_attr(test, assert_instr(sqshl, N = 2))]
17987#[rustc_legacy_const_generics(1)]
17988#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17989pub fn vqshld_n_s64<const N: i32>(a: i64) -> i64 {
17990    static_assert_uimm_bits!(N, 6);
17991    vget_lane_s64::<0>(vqshl_n_s64::<N>(vdup_n_s64(a)))
17992}
17993#[doc = "Signed saturating shift left"]
17994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"]
17995#[inline]
17996#[target_feature(enable = "neon")]
17997#[cfg_attr(test, assert_instr(sqshl, N = 2))]
17998#[rustc_legacy_const_generics(1)]
17999#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18000pub fn vqshlh_n_s16<const N: i32>(a: i16) -> i16 {
18001    static_assert_uimm_bits!(N, 4);
18002    vget_lane_s16::<0>(vqshl_n_s16::<N>(vdup_n_s16(a)))
18003}
18004#[doc = "Signed saturating shift left"]
18005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"]
18006#[inline]
18007#[target_feature(enable = "neon")]
18008#[cfg_attr(test, assert_instr(sqshl, N = 2))]
18009#[rustc_legacy_const_generics(1)]
18010#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18011pub fn vqshls_n_s32<const N: i32>(a: i32) -> i32 {
18012    static_assert_uimm_bits!(N, 5);
18013    vget_lane_s32::<0>(vqshl_n_s32::<N>(vdup_n_s32(a)))
18014}
18015#[doc = "Unsigned saturating shift left"]
18016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"]
18017#[inline]
18018#[target_feature(enable = "neon")]
18019#[cfg_attr(test, assert_instr(uqshl, N = 2))]
18020#[rustc_legacy_const_generics(1)]
18021#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18022pub fn vqshlb_n_u8<const N: i32>(a: u8) -> u8 {
18023    static_assert_uimm_bits!(N, 3);
18024    vget_lane_u8::<0>(vqshl_n_u8::<N>(vdup_n_u8(a)))
18025}
18026#[doc = "Unsigned saturating shift left"]
18027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"]
18028#[inline]
18029#[target_feature(enable = "neon")]
18030#[cfg_attr(test, assert_instr(uqshl, N = 2))]
18031#[rustc_legacy_const_generics(1)]
18032#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18033pub fn vqshld_n_u64<const N: i32>(a: u64) -> u64 {
18034    static_assert_uimm_bits!(N, 6);
18035    vget_lane_u64::<0>(vqshl_n_u64::<N>(vdup_n_u64(a)))
18036}
18037#[doc = "Unsigned saturating shift left"]
18038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"]
18039#[inline]
18040#[target_feature(enable = "neon")]
18041#[cfg_attr(test, assert_instr(uqshl, N = 2))]
18042#[rustc_legacy_const_generics(1)]
18043#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18044pub fn vqshlh_n_u16<const N: i32>(a: u16) -> u16 {
18045    static_assert_uimm_bits!(N, 4);
18046    vget_lane_u16::<0>(vqshl_n_u16::<N>(vdup_n_u16(a)))
18047}
18048#[doc = "Unsigned saturating shift left"]
18049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"]
18050#[inline]
18051#[target_feature(enable = "neon")]
18052#[cfg_attr(test, assert_instr(uqshl, N = 2))]
18053#[rustc_legacy_const_generics(1)]
18054#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18055pub fn vqshls_n_u32<const N: i32>(a: u32) -> u32 {
18056    static_assert_uimm_bits!(N, 5);
18057    vget_lane_u32::<0>(vqshl_n_u32::<N>(vdup_n_u32(a)))
18058}
18059#[doc = "Signed saturating shift left"]
18060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"]
18061#[inline]
18062#[target_feature(enable = "neon")]
18063#[cfg_attr(test, assert_instr(sqshl))]
18064#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18065pub fn vqshlb_s8(a: i8, b: i8) -> i8 {
18066    let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b));
18067    vget_lane_s8::<0>(c)
18068}
18069#[doc = "Signed saturating shift left"]
18070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"]
18071#[inline]
18072#[target_feature(enable = "neon")]
18073#[cfg_attr(test, assert_instr(sqshl))]
18074#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18075pub fn vqshlh_s16(a: i16, b: i16) -> i16 {
18076    let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b));
18077    vget_lane_s16::<0>(c)
18078}
18079#[doc = "Signed saturating shift left"]
18080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"]
18081#[inline]
18082#[target_feature(enable = "neon")]
18083#[cfg_attr(test, assert_instr(sqshl))]
18084#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18085pub fn vqshls_s32(a: i32, b: i32) -> i32 {
18086    let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b));
18087    vget_lane_s32::<0>(c)
18088}
18089#[doc = "Unsigned saturating shift left"]
18090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"]
18091#[inline]
18092#[target_feature(enable = "neon")]
18093#[cfg_attr(test, assert_instr(uqshl))]
18094#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18095pub fn vqshlb_u8(a: u8, b: i8) -> u8 {
18096    let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b));
18097    vget_lane_u8::<0>(c)
18098}
18099#[doc = "Unsigned saturating shift left"]
18100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"]
18101#[inline]
18102#[target_feature(enable = "neon")]
18103#[cfg_attr(test, assert_instr(uqshl))]
18104#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18105pub fn vqshlh_u16(a: u16, b: i16) -> u16 {
18106    let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b));
18107    vget_lane_u16::<0>(c)
18108}
18109#[doc = "Unsigned saturating shift left"]
18110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"]
18111#[inline]
18112#[target_feature(enable = "neon")]
18113#[cfg_attr(test, assert_instr(uqshl))]
18114#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18115pub fn vqshls_u32(a: u32, b: i32) -> u32 {
18116    let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b));
18117    vget_lane_u32::<0>(c)
18118}
18119#[doc = "Signed saturating shift left"]
18120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"]
18121#[inline]
18122#[target_feature(enable = "neon")]
18123#[cfg_attr(test, assert_instr(sqshl))]
18124#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18125pub fn vqshld_s64(a: i64, b: i64) -> i64 {
18126    unsafe extern "unadjusted" {
18127        #[cfg_attr(
18128            any(target_arch = "aarch64", target_arch = "arm64ec"),
18129            link_name = "llvm.aarch64.neon.sqshl.i64"
18130        )]
18131        fn _vqshld_s64(a: i64, b: i64) -> i64;
18132    }
18133    unsafe { _vqshld_s64(a, b) }
18134}
18135#[doc = "Unsigned saturating shift left"]
18136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64)"]
18137#[inline]
18138#[target_feature(enable = "neon")]
18139#[cfg_attr(test, assert_instr(uqshl))]
18140#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18141pub fn vqshld_u64(a: u64, b: i64) -> u64 {
18142    unsafe extern "unadjusted" {
18143        #[cfg_attr(
18144            any(target_arch = "aarch64", target_arch = "arm64ec"),
18145            link_name = "llvm.aarch64.neon.uqshl.i64"
18146        )]
18147        fn _vqshld_u64(a: u64, b: i64) -> u64;
18148    }
18149    unsafe { _vqshld_u64(a, b) }
18150}
18151#[doc = "Signed saturating shift left unsigned"]
18152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)"]
18153#[inline]
18154#[target_feature(enable = "neon")]
18155#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
18156#[rustc_legacy_const_generics(1)]
18157#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18158pub fn vqshlub_n_s8<const N: i32>(a: i8) -> u8 {
18159    static_assert_uimm_bits!(N, 3);
18160    vget_lane_u8::<0>(vqshlu_n_s8::<N>(vdup_n_s8(a)))
18161}
18162#[doc = "Signed saturating shift left unsigned"]
18163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"]
18164#[inline]
18165#[target_feature(enable = "neon")]
18166#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
18167#[rustc_legacy_const_generics(1)]
18168#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18169pub fn vqshlud_n_s64<const N: i32>(a: i64) -> u64 {
18170    static_assert_uimm_bits!(N, 6);
18171    vget_lane_u64::<0>(vqshlu_n_s64::<N>(vdup_n_s64(a)))
18172}
18173#[doc = "Signed saturating shift left unsigned"]
18174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"]
18175#[inline]
18176#[target_feature(enable = "neon")]
18177#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
18178#[rustc_legacy_const_generics(1)]
18179#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18180pub fn vqshluh_n_s16<const N: i32>(a: i16) -> u16 {
18181    static_assert_uimm_bits!(N, 4);
18182    vget_lane_u16::<0>(vqshlu_n_s16::<N>(vdup_n_s16(a)))
18183}
18184#[doc = "Signed saturating shift left unsigned"]
18185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"]
18186#[inline]
18187#[target_feature(enable = "neon")]
18188#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
18189#[rustc_legacy_const_generics(1)]
18190#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18191pub fn vqshlus_n_s32<const N: i32>(a: i32) -> u32 {
18192    static_assert_uimm_bits!(N, 5);
18193    vget_lane_u32::<0>(vqshlu_n_s32::<N>(vdup_n_s32(a)))
18194}
18195#[doc = "Signed saturating shift right narrow"]
18196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"]
18197#[inline]
18198#[target_feature(enable = "neon")]
18199#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))]
18200#[rustc_legacy_const_generics(2)]
18201#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18202pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
18203    static_assert!(N >= 1 && N <= 8);
18204    vcombine_s8(a, vqshrn_n_s16::<N>(b))
18205}
18206#[doc = "Signed saturating shift right narrow"]
18207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"]
18208#[inline]
18209#[target_feature(enable = "neon")]
18210#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))]
18211#[rustc_legacy_const_generics(2)]
18212#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18213pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
18214    static_assert!(N >= 1 && N <= 16);
18215    vcombine_s16(a, vqshrn_n_s32::<N>(b))
18216}
18217#[doc = "Signed saturating shift right narrow"]
18218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"]
18219#[inline]
18220#[target_feature(enable = "neon")]
18221#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))]
18222#[rustc_legacy_const_generics(2)]
18223#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18224pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
18225    static_assert!(N >= 1 && N <= 32);
18226    vcombine_s32(a, vqshrn_n_s64::<N>(b))
18227}
18228#[doc = "Unsigned saturating shift right narrow"]
18229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"]
18230#[inline]
18231#[target_feature(enable = "neon")]
18232#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))]
18233#[rustc_legacy_const_generics(2)]
18234#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18235pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
18236    static_assert!(N >= 1 && N <= 8);
18237    vcombine_u8(a, vqshrn_n_u16::<N>(b))
18238}
18239#[doc = "Unsigned saturating shift right narrow"]
18240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"]
18241#[inline]
18242#[target_feature(enable = "neon")]
18243#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))]
18244#[rustc_legacy_const_generics(2)]
18245#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18246pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
18247    static_assert!(N >= 1 && N <= 16);
18248    vcombine_u16(a, vqshrn_n_u32::<N>(b))
18249}
18250#[doc = "Unsigned saturating shift right narrow"]
18251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"]
18252#[inline]
18253#[target_feature(enable = "neon")]
18254#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))]
18255#[rustc_legacy_const_generics(2)]
18256#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18257pub fn vqshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
18258    static_assert!(N >= 1 && N <= 32);
18259    vcombine_u32(a, vqshrn_n_u64::<N>(b))
18260}
18261#[doc = "Signed saturating shift right narrow"]
18262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"]
18263#[inline]
18264#[target_feature(enable = "neon")]
18265#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
18266#[rustc_legacy_const_generics(1)]
18267#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18268pub fn vqshrnd_n_s64<const N: i32>(a: i64) -> i32 {
18269    static_assert!(N >= 1 && N <= 32);
18270    unsafe extern "unadjusted" {
18271        #[cfg_attr(
18272            any(target_arch = "aarch64", target_arch = "arm64ec"),
18273            link_name = "llvm.aarch64.neon.sqshrn.i32"
18274        )]
18275        fn _vqshrnd_n_s64(a: i64, n: i32) -> i32;
18276    }
18277    unsafe { _vqshrnd_n_s64(a, N) }
18278}
18279#[doc = "Unsigned saturating shift right narrow"]
18280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)"]
18281#[inline]
18282#[target_feature(enable = "neon")]
18283#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
18284#[rustc_legacy_const_generics(1)]
18285#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18286pub fn vqshrnd_n_u64<const N: i32>(a: u64) -> u32 {
18287    static_assert!(N >= 1 && N <= 32);
18288    unsafe extern "unadjusted" {
18289        #[cfg_attr(
18290            any(target_arch = "aarch64", target_arch = "arm64ec"),
18291            link_name = "llvm.aarch64.neon.uqshrn.i32"
18292        )]
18293        fn _vqshrnd_n_u64(a: u64, n: i32) -> u32;
18294    }
18295    unsafe { _vqshrnd_n_u64(a, N) }
18296}
18297#[doc = "Signed saturating shift right narrow"]
18298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)"]
18299#[inline]
18300#[target_feature(enable = "neon")]
18301#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
18302#[rustc_legacy_const_generics(1)]
18303#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18304pub fn vqshrnh_n_s16<const N: i32>(a: i16) -> i8 {
18305    static_assert!(N >= 1 && N <= 8);
18306    vget_lane_s8::<0>(vqshrn_n_s16::<N>(vdupq_n_s16(a)))
18307}
18308#[doc = "Signed saturating shift right narrow"]
18309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"]
18310#[inline]
18311#[target_feature(enable = "neon")]
18312#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
18313#[rustc_legacy_const_generics(1)]
18314#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18315pub fn vqshrns_n_s32<const N: i32>(a: i32) -> i16 {
18316    static_assert!(N >= 1 && N <= 16);
18317    vget_lane_s16::<0>(vqshrn_n_s32::<N>(vdupq_n_s32(a)))
18318}
18319#[doc = "Unsigned saturating shift right narrow"]
18320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"]
18321#[inline]
18322#[target_feature(enable = "neon")]
18323#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
18324#[rustc_legacy_const_generics(1)]
18325#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18326pub fn vqshrnh_n_u16<const N: i32>(a: u16) -> u8 {
18327    static_assert!(N >= 1 && N <= 8);
18328    vget_lane_u8::<0>(vqshrn_n_u16::<N>(vdupq_n_u16(a)))
18329}
18330#[doc = "Unsigned saturating shift right narrow"]
18331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"]
18332#[inline]
18333#[target_feature(enable = "neon")]
18334#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
18335#[rustc_legacy_const_generics(1)]
18336#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18337pub fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 {
18338    static_assert!(N >= 1 && N <= 16);
18339    vget_lane_u16::<0>(vqshrn_n_u32::<N>(vdupq_n_u32(a)))
18340}
18341#[doc = "Signed saturating shift right unsigned narrow"]
18342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"]
18343#[inline]
18344#[target_feature(enable = "neon")]
18345#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))]
18346#[rustc_legacy_const_generics(2)]
18347#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18348pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
18349    static_assert!(N >= 1 && N <= 8);
18350    vcombine_u8(a, vqshrun_n_s16::<N>(b))
18351}
18352#[doc = "Signed saturating shift right unsigned narrow"]
18353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"]
18354#[inline]
18355#[target_feature(enable = "neon")]
18356#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))]
18357#[rustc_legacy_const_generics(2)]
18358#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18359pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
18360    static_assert!(N >= 1 && N <= 16);
18361    vcombine_u16(a, vqshrun_n_s32::<N>(b))
18362}
18363#[doc = "Signed saturating shift right unsigned narrow"]
18364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"]
18365#[inline]
18366#[target_feature(enable = "neon")]
18367#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))]
18368#[rustc_legacy_const_generics(2)]
18369#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18370pub fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
18371    static_assert!(N >= 1 && N <= 32);
18372    vcombine_u32(a, vqshrun_n_s64::<N>(b))
18373}
18374#[doc = "Signed saturating shift right unsigned narrow"]
18375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"]
18376#[inline]
18377#[target_feature(enable = "neon")]
18378#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
18379#[rustc_legacy_const_generics(1)]
18380#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18381pub fn vqshrund_n_s64<const N: i32>(a: i64) -> u32 {
18382    static_assert!(N >= 1 && N <= 32);
18383    vget_lane_u32::<0>(vqshrun_n_s64::<N>(vdupq_n_s64(a)))
18384}
18385#[doc = "Signed saturating shift right unsigned narrow"]
18386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"]
18387#[inline]
18388#[target_feature(enable = "neon")]
18389#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
18390#[rustc_legacy_const_generics(1)]
18391#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18392pub fn vqshrunh_n_s16<const N: i32>(a: i16) -> u8 {
18393    static_assert!(N >= 1 && N <= 8);
18394    vget_lane_u8::<0>(vqshrun_n_s16::<N>(vdupq_n_s16(a)))
18395}
18396#[doc = "Signed saturating shift right unsigned narrow"]
18397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"]
18398#[inline]
18399#[target_feature(enable = "neon")]
18400#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
18401#[rustc_legacy_const_generics(1)]
18402#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18403pub fn vqshruns_n_s32<const N: i32>(a: i32) -> u16 {
18404    static_assert!(N >= 1 && N <= 16);
18405    vget_lane_u16::<0>(vqshrun_n_s32::<N>(vdupq_n_s32(a)))
18406}
18407#[doc = "Saturating subtract"]
18408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"]
18409#[inline]
18410#[target_feature(enable = "neon")]
18411#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18412#[cfg_attr(test, assert_instr(sqsub))]
18413pub fn vqsubb_s8(a: i8, b: i8) -> i8 {
18414    let a: int8x8_t = vdup_n_s8(a);
18415    let b: int8x8_t = vdup_n_s8(b);
18416    vget_lane_s8::<0>(vqsub_s8(a, b))
18417}
18418#[doc = "Saturating subtract"]
18419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"]
18420#[inline]
18421#[target_feature(enable = "neon")]
18422#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18423#[cfg_attr(test, assert_instr(sqsub))]
18424pub fn vqsubh_s16(a: i16, b: i16) -> i16 {
18425    let a: int16x4_t = vdup_n_s16(a);
18426    let b: int16x4_t = vdup_n_s16(b);
18427    vget_lane_s16::<0>(vqsub_s16(a, b))
18428}
18429#[doc = "Saturating subtract"]
18430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"]
18431#[inline]
18432#[target_feature(enable = "neon")]
18433#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18434#[cfg_attr(test, assert_instr(uqsub))]
18435pub fn vqsubb_u8(a: u8, b: u8) -> u8 {
18436    let a: uint8x8_t = vdup_n_u8(a);
18437    let b: uint8x8_t = vdup_n_u8(b);
18438    vget_lane_u8::<0>(vqsub_u8(a, b))
18439}
18440#[doc = "Saturating subtract"]
18441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"]
18442#[inline]
18443#[target_feature(enable = "neon")]
18444#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18445#[cfg_attr(test, assert_instr(uqsub))]
18446pub fn vqsubh_u16(a: u16, b: u16) -> u16 {
18447    let a: uint16x4_t = vdup_n_u16(a);
18448    let b: uint16x4_t = vdup_n_u16(b);
18449    vget_lane_u16::<0>(vqsub_u16(a, b))
18450}
18451#[doc = "Saturating subtract"]
18452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"]
18453#[inline]
18454#[target_feature(enable = "neon")]
18455#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18456#[cfg_attr(test, assert_instr(sqsub))]
18457pub fn vqsubs_s32(a: i32, b: i32) -> i32 {
18458    unsafe extern "unadjusted" {
18459        #[cfg_attr(
18460            any(target_arch = "aarch64", target_arch = "arm64ec"),
18461            link_name = "llvm.aarch64.neon.sqsub.i32"
18462        )]
18463        fn _vqsubs_s32(a: i32, b: i32) -> i32;
18464    }
18465    unsafe { _vqsubs_s32(a, b) }
18466}
18467#[doc = "Saturating subtract"]
18468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64)"]
18469#[inline]
18470#[target_feature(enable = "neon")]
18471#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18472#[cfg_attr(test, assert_instr(sqsub))]
18473pub fn vqsubd_s64(a: i64, b: i64) -> i64 {
18474    unsafe extern "unadjusted" {
18475        #[cfg_attr(
18476            any(target_arch = "aarch64", target_arch = "arm64ec"),
18477            link_name = "llvm.aarch64.neon.sqsub.i64"
18478        )]
18479        fn _vqsubd_s64(a: i64, b: i64) -> i64;
18480    }
18481    unsafe { _vqsubd_s64(a, b) }
18482}
18483#[doc = "Saturating subtract"]
18484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)"]
18485#[inline]
18486#[target_feature(enable = "neon")]
18487#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18488#[cfg_attr(test, assert_instr(uqsub))]
18489pub fn vqsubs_u32(a: u32, b: u32) -> u32 {
18490    unsafe extern "unadjusted" {
18491        #[cfg_attr(
18492            any(target_arch = "aarch64", target_arch = "arm64ec"),
18493            link_name = "llvm.aarch64.neon.uqsub.i32"
18494        )]
18495        fn _vqsubs_u32(a: u32, b: u32) -> u32;
18496    }
18497    unsafe { _vqsubs_u32(a, b) }
18498}
18499#[doc = "Saturating subtract"]
18500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64)"]
18501#[inline]
18502#[target_feature(enable = "neon")]
18503#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18504#[cfg_attr(test, assert_instr(uqsub))]
18505pub fn vqsubd_u64(a: u64, b: u64) -> u64 {
18506    unsafe extern "unadjusted" {
18507        #[cfg_attr(
18508            any(target_arch = "aarch64", target_arch = "arm64ec"),
18509            link_name = "llvm.aarch64.neon.uqsub.i64"
18510        )]
18511        fn _vqsubd_u64(a: u64, b: u64) -> u64;
18512    }
18513    unsafe { _vqsubd_u64(a, b) }
18514}
18515#[doc = "Table look-up"]
18516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1)"]
18517#[inline]
18518#[target_feature(enable = "neon")]
18519#[cfg_attr(test, assert_instr(tbl))]
18520#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18521fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t {
18522    unsafe extern "unadjusted" {
18523        #[cfg_attr(
18524            any(target_arch = "aarch64", target_arch = "arm64ec"),
18525            link_name = "llvm.aarch64.neon.tbl1.v8i8"
18526        )]
18527        fn _vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t;
18528    }
18529    unsafe { _vqtbl1(a, b) }
18530}
18531#[doc = "Table look-up"]
18532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q)"]
18533#[inline]
18534#[target_feature(enable = "neon")]
18535#[cfg_attr(test, assert_instr(tbl))]
18536#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18537fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
18538    unsafe extern "unadjusted" {
18539        #[cfg_attr(
18540            any(target_arch = "aarch64", target_arch = "arm64ec"),
18541            link_name = "llvm.aarch64.neon.tbl1.v16i8"
18542        )]
18543        fn _vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t;
18544    }
18545    unsafe { _vqtbl1q(a, b) }
18546}
18547#[doc = "Table look-up"]
18548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"]
18549#[inline]
18550#[cfg(target_endian = "little")]
18551#[target_feature(enable = "neon")]
18552#[cfg_attr(test, assert_instr(tbl))]
18553#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18554pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t {
18555    vqtbl1(a, b)
18556}
18557#[doc = "Table look-up"]
18558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"]
18559#[inline]
18560#[cfg(target_endian = "big")]
18561#[target_feature(enable = "neon")]
18562#[cfg_attr(test, assert_instr(tbl))]
18563#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18564pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t {
18565    unsafe {
18566        let a: int8x16_t =
18567            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18568        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
18569        let ret_val: int8x8_t = vqtbl1(a, b);
18570        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
18571    }
18572}
18573#[doc = "Table look-up"]
18574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"]
18575#[inline]
18576#[cfg(target_endian = "little")]
18577#[target_feature(enable = "neon")]
18578#[cfg_attr(test, assert_instr(tbl))]
18579#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18580pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
18581    vqtbl1q(a, b)
18582}
18583#[doc = "Table look-up"]
18584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"]
18585#[inline]
18586#[cfg(target_endian = "big")]
18587#[target_feature(enable = "neon")]
18588#[cfg_attr(test, assert_instr(tbl))]
18589#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18590pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
18591    unsafe {
18592        let a: int8x16_t =
18593            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18594        let b: uint8x16_t =
18595            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18596        let ret_val: int8x16_t = vqtbl1q(a, b);
18597        simd_shuffle!(
18598            ret_val,
18599            ret_val,
18600            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18601        )
18602    }
18603}
18604#[doc = "Table look-up"]
18605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"]
18606#[inline]
18607#[cfg(target_endian = "little")]
18608#[target_feature(enable = "neon")]
18609#[cfg_attr(test, assert_instr(tbl))]
18610#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18611pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t {
18612    unsafe { transmute(vqtbl1(transmute(a), b)) }
18613}
18614#[doc = "Table look-up"]
18615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"]
18616#[inline]
18617#[cfg(target_endian = "big")]
18618#[target_feature(enable = "neon")]
18619#[cfg_attr(test, assert_instr(tbl))]
18620#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18621pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t {
18622    unsafe {
18623        let a: uint8x16_t =
18624            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18625        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
18626        let ret_val: uint8x8_t = transmute(vqtbl1(transmute(a), b));
18627        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
18628    }
18629}
18630#[doc = "Table look-up"]
18631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"]
18632#[inline]
18633#[cfg(target_endian = "little")]
18634#[target_feature(enable = "neon")]
18635#[cfg_attr(test, assert_instr(tbl))]
18636#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18637pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
18638    unsafe { transmute(vqtbl1q(transmute(a), b)) }
18639}
18640#[doc = "Table look-up"]
18641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"]
18642#[inline]
18643#[cfg(target_endian = "big")]
18644#[target_feature(enable = "neon")]
18645#[cfg_attr(test, assert_instr(tbl))]
18646#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18647pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
18648    unsafe {
18649        let a: uint8x16_t =
18650            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18651        let b: uint8x16_t =
18652            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18653        let ret_val: uint8x16_t = transmute(vqtbl1q(transmute(a), b));
18654        simd_shuffle!(
18655            ret_val,
18656            ret_val,
18657            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18658        )
18659    }
18660}
18661#[doc = "Table look-up"]
18662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"]
18663#[inline]
18664#[cfg(target_endian = "little")]
18665#[target_feature(enable = "neon")]
18666#[cfg_attr(test, assert_instr(tbl))]
18667#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18668pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t {
18669    unsafe { transmute(vqtbl1(transmute(a), b)) }
18670}
18671#[doc = "Table look-up"]
18672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"]
18673#[inline]
18674#[cfg(target_endian = "big")]
18675#[target_feature(enable = "neon")]
18676#[cfg_attr(test, assert_instr(tbl))]
18677#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18678pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t {
18679    unsafe {
18680        let a: poly8x16_t =
18681            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18682        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
18683        let ret_val: poly8x8_t = transmute(vqtbl1(transmute(a), b));
18684        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
18685    }
18686}
18687#[doc = "Table look-up"]
18688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"]
18689#[inline]
18690#[cfg(target_endian = "little")]
18691#[target_feature(enable = "neon")]
18692#[cfg_attr(test, assert_instr(tbl))]
18693#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18694pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
18695    unsafe { transmute(vqtbl1q(transmute(a), b)) }
18696}
18697#[doc = "Table look-up"]
18698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"]
18699#[inline]
18700#[cfg(target_endian = "big")]
18701#[target_feature(enable = "neon")]
18702#[cfg_attr(test, assert_instr(tbl))]
18703#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18704pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
18705    unsafe {
18706        let a: poly8x16_t =
18707            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18708        let b: uint8x16_t =
18709            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18710        let ret_val: poly8x16_t = transmute(vqtbl1q(transmute(a), b));
18711        simd_shuffle!(
18712            ret_val,
18713            ret_val,
18714            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18715        )
18716    }
18717}
18718#[doc = "Table look-up"]
18719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2)"]
18720#[inline]
18721#[target_feature(enable = "neon")]
18722#[cfg_attr(test, assert_instr(tbl))]
18723#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18724fn vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
18725    unsafe extern "unadjusted" {
18726        #[cfg_attr(
18727            any(target_arch = "aarch64", target_arch = "arm64ec"),
18728            link_name = "llvm.aarch64.neon.tbl2.v8i8"
18729        )]
18730        fn _vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t;
18731    }
18732    unsafe { _vqtbl2(a, b, c) }
18733}
18734#[doc = "Table look-up"]
18735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q)"]
18736#[inline]
18737#[target_feature(enable = "neon")]
18738#[cfg_attr(test, assert_instr(tbl))]
18739#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18740fn vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
18741    unsafe extern "unadjusted" {
18742        #[cfg_attr(
18743            any(target_arch = "aarch64", target_arch = "arm64ec"),
18744            link_name = "llvm.aarch64.neon.tbl2.v16i8"
18745        )]
18746        fn _vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t;
18747    }
18748    unsafe { _vqtbl2q(a, b, c) }
18749}
18750#[doc = "Table look-up"]
18751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"]
18752#[inline]
18753#[cfg(target_endian = "little")]
18754#[target_feature(enable = "neon")]
18755#[cfg_attr(test, assert_instr(tbl))]
18756#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18757pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t {
18758    vqtbl2(a.0, a.1, b)
18759}
18760#[doc = "Table look-up"]
18761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"]
18762#[inline]
18763#[cfg(target_endian = "big")]
18764#[target_feature(enable = "neon")]
18765#[cfg_attr(test, assert_instr(tbl))]
18766#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18767pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t {
18768    let mut a: int8x16x2_t = a;
18769    unsafe {
18770        a.0 = simd_shuffle!(
18771            a.0,
18772            a.0,
18773            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18774        );
18775        a.1 = simd_shuffle!(
18776            a.1,
18777            a.1,
18778            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18779        );
18780        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
18781        let ret_val: int8x8_t = vqtbl2(a.0, a.1, b);
18782        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
18783    }
18784}
18785#[doc = "Table look-up"]
18786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"]
18787#[inline]
18788#[cfg(target_endian = "little")]
18789#[target_feature(enable = "neon")]
18790#[cfg_attr(test, assert_instr(tbl))]
18791#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18792pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t {
18793    vqtbl2q(a.0, a.1, b)
18794}
18795#[doc = "Table look-up"]
18796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"]
18797#[inline]
18798#[cfg(target_endian = "big")]
18799#[target_feature(enable = "neon")]
18800#[cfg_attr(test, assert_instr(tbl))]
18801#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18802pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t {
18803    let mut a: int8x16x2_t = a;
18804    unsafe {
18805        a.0 = simd_shuffle!(
18806            a.0,
18807            a.0,
18808            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18809        );
18810        a.1 = simd_shuffle!(
18811            a.1,
18812            a.1,
18813            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18814        );
18815        let b: uint8x16_t =
18816            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18817        let ret_val: int8x16_t = vqtbl2q(a.0, a.1, b);
18818        simd_shuffle!(
18819            ret_val,
18820            ret_val,
18821            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18822        )
18823    }
18824}
18825#[doc = "Table look-up"]
18826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"]
18827#[inline]
18828#[cfg(target_endian = "little")]
18829#[target_feature(enable = "neon")]
18830#[cfg_attr(test, assert_instr(tbl))]
18831#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18832pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t {
18833    unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) }
18834}
18835#[doc = "Table look-up"]
18836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"]
18837#[inline]
18838#[cfg(target_endian = "big")]
18839#[target_feature(enable = "neon")]
18840#[cfg_attr(test, assert_instr(tbl))]
18841#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18842pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t {
18843    let mut a: uint8x16x2_t = a;
18844    unsafe {
18845        a.0 = simd_shuffle!(
18846            a.0,
18847            a.0,
18848            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18849        );
18850        a.1 = simd_shuffle!(
18851            a.1,
18852            a.1,
18853            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18854        );
18855        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
18856        let ret_val: uint8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b));
18857        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
18858    }
18859}
18860#[doc = "Table look-up"]
18861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"]
18862#[inline]
18863#[cfg(target_endian = "little")]
18864#[target_feature(enable = "neon")]
18865#[cfg_attr(test, assert_instr(tbl))]
18866#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18867pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t {
18868    unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) }
18869}
18870#[doc = "Table look-up"]
18871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"]
18872#[inline]
18873#[cfg(target_endian = "big")]
18874#[target_feature(enable = "neon")]
18875#[cfg_attr(test, assert_instr(tbl))]
18876#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18877pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t {
18878    let mut a: uint8x16x2_t = a;
18879    unsafe {
18880        a.0 = simd_shuffle!(
18881            a.0,
18882            a.0,
18883            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18884        );
18885        a.1 = simd_shuffle!(
18886            a.1,
18887            a.1,
18888            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18889        );
18890        let b: uint8x16_t =
18891            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18892        let ret_val: uint8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b));
18893        simd_shuffle!(
18894            ret_val,
18895            ret_val,
18896            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18897        )
18898    }
18899}
18900#[doc = "Table look-up"]
18901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"]
18902#[inline]
18903#[cfg(target_endian = "little")]
18904#[target_feature(enable = "neon")]
18905#[cfg_attr(test, assert_instr(tbl))]
18906#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18907pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t {
18908    unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) }
18909}
18910#[doc = "Table look-up"]
18911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"]
18912#[inline]
18913#[cfg(target_endian = "big")]
18914#[target_feature(enable = "neon")]
18915#[cfg_attr(test, assert_instr(tbl))]
18916#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18917pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t {
18918    let mut a: poly8x16x2_t = a;
18919    unsafe {
18920        a.0 = simd_shuffle!(
18921            a.0,
18922            a.0,
18923            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18924        );
18925        a.1 = simd_shuffle!(
18926            a.1,
18927            a.1,
18928            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18929        );
18930        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
18931        let ret_val: poly8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b));
18932        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
18933    }
18934}
18935#[doc = "Table look-up"]
18936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"]
18937#[inline]
18938#[cfg(target_endian = "little")]
18939#[target_feature(enable = "neon")]
18940#[cfg_attr(test, assert_instr(tbl))]
18941#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18942pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t {
18943    unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) }
18944}
18945#[doc = "Table look-up"]
18946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"]
18947#[inline]
18948#[cfg(target_endian = "big")]
18949#[target_feature(enable = "neon")]
18950#[cfg_attr(test, assert_instr(tbl))]
18951#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18952pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t {
18953    let mut a: poly8x16x2_t = a;
18954    unsafe {
18955        a.0 = simd_shuffle!(
18956            a.0,
18957            a.0,
18958            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18959        );
18960        a.1 = simd_shuffle!(
18961            a.1,
18962            a.1,
18963            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18964        );
18965        let b: uint8x16_t =
18966            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
18967        let ret_val: poly8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b));
18968        simd_shuffle!(
18969            ret_val,
18970            ret_val,
18971            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18972        )
18973    }
18974}
18975#[doc = "Table look-up"]
18976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"]
18977#[inline]
18978#[target_feature(enable = "neon")]
18979#[cfg_attr(test, assert_instr(tbl))]
18980#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18981fn vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t {
18982    unsafe extern "unadjusted" {
18983        #[cfg_attr(
18984            any(target_arch = "aarch64", target_arch = "arm64ec"),
18985            link_name = "llvm.aarch64.neon.tbl3.v8i8"
18986        )]
18987        fn _vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t;
18988    }
18989    unsafe { _vqtbl3(a, b, c, d) }
18990}
18991#[doc = "Table look-up"]
18992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q)"]
18993#[inline]
18994#[target_feature(enable = "neon")]
18995#[cfg_attr(test, assert_instr(tbl))]
18996#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18997fn vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t {
18998    unsafe extern "unadjusted" {
18999        #[cfg_attr(
19000            any(target_arch = "aarch64", target_arch = "arm64ec"),
19001            link_name = "llvm.aarch64.neon.tbl3.v16i8"
19002        )]
19003        fn _vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t;
19004    }
19005    unsafe { _vqtbl3q(a, b, c, d) }
19006}
19007#[doc = "Table look-up"]
19008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"]
19009#[inline]
19010#[cfg(target_endian = "little")]
19011#[target_feature(enable = "neon")]
19012#[cfg_attr(test, assert_instr(tbl))]
19013#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19014pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t {
19015    vqtbl3(a.0, a.1, a.2, b)
19016}
19017#[doc = "Table look-up"]
19018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"]
19019#[inline]
19020#[cfg(target_endian = "big")]
19021#[target_feature(enable = "neon")]
19022#[cfg_attr(test, assert_instr(tbl))]
19023#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19024pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t {
19025    let mut a: int8x16x3_t = a;
19026    unsafe {
19027        a.0 = simd_shuffle!(
19028            a.0,
19029            a.0,
19030            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19031        );
19032        a.1 = simd_shuffle!(
19033            a.1,
19034            a.1,
19035            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19036        );
19037        a.2 = simd_shuffle!(
19038            a.2,
19039            a.2,
19040            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19041        );
19042        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
19043        let ret_val: int8x8_t = vqtbl3(a.0, a.1, a.2, b);
19044        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19045    }
19046}
19047#[doc = "Table look-up"]
19048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"]
19049#[inline]
19050#[cfg(target_endian = "little")]
19051#[target_feature(enable = "neon")]
19052#[cfg_attr(test, assert_instr(tbl))]
19053#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19054pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t {
19055    vqtbl3q(a.0, a.1, a.2, b)
19056}
19057#[doc = "Table look-up"]
19058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"]
19059#[inline]
19060#[cfg(target_endian = "big")]
19061#[target_feature(enable = "neon")]
19062#[cfg_attr(test, assert_instr(tbl))]
19063#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19064pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t {
19065    let mut a: int8x16x3_t = a;
19066    unsafe {
19067        a.0 = simd_shuffle!(
19068            a.0,
19069            a.0,
19070            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19071        );
19072        a.1 = simd_shuffle!(
19073            a.1,
19074            a.1,
19075            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19076        );
19077        a.2 = simd_shuffle!(
19078            a.2,
19079            a.2,
19080            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19081        );
19082        let b: uint8x16_t =
19083            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19084        let ret_val: int8x16_t = vqtbl3q(a.0, a.1, a.2, b);
19085        simd_shuffle!(
19086            ret_val,
19087            ret_val,
19088            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19089        )
19090    }
19091}
19092#[doc = "Table look-up"]
19093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"]
19094#[inline]
19095#[cfg(target_endian = "little")]
19096#[target_feature(enable = "neon")]
19097#[cfg_attr(test, assert_instr(tbl))]
19098#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19099pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t {
19100    unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) }
19101}
19102#[doc = "Table look-up"]
19103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"]
19104#[inline]
19105#[cfg(target_endian = "big")]
19106#[target_feature(enable = "neon")]
19107#[cfg_attr(test, assert_instr(tbl))]
19108#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19109pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t {
19110    let mut a: uint8x16x3_t = a;
19111    unsafe {
19112        a.0 = simd_shuffle!(
19113            a.0,
19114            a.0,
19115            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19116        );
19117        a.1 = simd_shuffle!(
19118            a.1,
19119            a.1,
19120            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19121        );
19122        a.2 = simd_shuffle!(
19123            a.2,
19124            a.2,
19125            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19126        );
19127        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
19128        let ret_val: uint8x8_t =
19129            transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b));
19130        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19131    }
19132}
19133#[doc = "Table look-up"]
19134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"]
19135#[inline]
19136#[cfg(target_endian = "little")]
19137#[target_feature(enable = "neon")]
19138#[cfg_attr(test, assert_instr(tbl))]
19139#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19140pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t {
19141    unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) }
19142}
19143#[doc = "Table look-up"]
19144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"]
19145#[inline]
19146#[cfg(target_endian = "big")]
19147#[target_feature(enable = "neon")]
19148#[cfg_attr(test, assert_instr(tbl))]
19149#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19150pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t {
19151    let mut a: uint8x16x3_t = a;
19152    unsafe {
19153        a.0 = simd_shuffle!(
19154            a.0,
19155            a.0,
19156            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19157        );
19158        a.1 = simd_shuffle!(
19159            a.1,
19160            a.1,
19161            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19162        );
19163        a.2 = simd_shuffle!(
19164            a.2,
19165            a.2,
19166            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19167        );
19168        let b: uint8x16_t =
19169            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19170        let ret_val: uint8x16_t =
19171            transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b));
19172        simd_shuffle!(
19173            ret_val,
19174            ret_val,
19175            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19176        )
19177    }
19178}
19179#[doc = "Table look-up"]
19180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"]
19181#[inline]
19182#[cfg(target_endian = "little")]
19183#[target_feature(enable = "neon")]
19184#[cfg_attr(test, assert_instr(tbl))]
19185#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19186pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t {
19187    unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) }
19188}
19189#[doc = "Table look-up"]
19190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"]
19191#[inline]
19192#[cfg(target_endian = "big")]
19193#[target_feature(enable = "neon")]
19194#[cfg_attr(test, assert_instr(tbl))]
19195#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19196pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t {
19197    let mut a: poly8x16x3_t = a;
19198    unsafe {
19199        a.0 = simd_shuffle!(
19200            a.0,
19201            a.0,
19202            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19203        );
19204        a.1 = simd_shuffle!(
19205            a.1,
19206            a.1,
19207            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19208        );
19209        a.2 = simd_shuffle!(
19210            a.2,
19211            a.2,
19212            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19213        );
19214        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
19215        let ret_val: poly8x8_t =
19216            transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b));
19217        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19218    }
19219}
19220#[doc = "Table look-up"]
19221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"]
19222#[inline]
19223#[cfg(target_endian = "little")]
19224#[target_feature(enable = "neon")]
19225#[cfg_attr(test, assert_instr(tbl))]
19226#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19227pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t {
19228    unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) }
19229}
19230#[doc = "Table look-up"]
19231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"]
19232#[inline]
19233#[cfg(target_endian = "big")]
19234#[target_feature(enable = "neon")]
19235#[cfg_attr(test, assert_instr(tbl))]
19236#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19237pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t {
19238    let mut a: poly8x16x3_t = a;
19239    unsafe {
19240        a.0 = simd_shuffle!(
19241            a.0,
19242            a.0,
19243            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19244        );
19245        a.1 = simd_shuffle!(
19246            a.1,
19247            a.1,
19248            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19249        );
19250        a.2 = simd_shuffle!(
19251            a.2,
19252            a.2,
19253            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19254        );
19255        let b: uint8x16_t =
19256            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19257        let ret_val: poly8x16_t =
19258            transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b));
19259        simd_shuffle!(
19260            ret_val,
19261            ret_val,
19262            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19263        )
19264    }
19265}
19266#[doc = "Table look-up"]
19267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"]
19268#[inline]
19269#[target_feature(enable = "neon")]
19270#[cfg_attr(test, assert_instr(tbl))]
19271#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19272fn vqtbl4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -> int8x8_t {
19273    unsafe extern "unadjusted" {
19274        #[cfg_attr(
19275            any(target_arch = "aarch64", target_arch = "arm64ec"),
19276            link_name = "llvm.aarch64.neon.tbl4.v8i8"
19277        )]
19278        fn _vqtbl4(
19279            a: int8x16_t,
19280            b: int8x16_t,
19281            c: int8x16_t,
19282            d: int8x16_t,
19283            e: uint8x8_t,
19284        ) -> int8x8_t;
19285    }
19286    unsafe { _vqtbl4(a, b, c, d, e) }
19287}
19288#[doc = "Table look-up"]
19289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q)"]
19290#[inline]
19291#[target_feature(enable = "neon")]
19292#[cfg_attr(test, assert_instr(tbl))]
19293#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19294fn vqtbl4q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t) -> int8x16_t {
19295    unsafe extern "unadjusted" {
19296        #[cfg_attr(
19297            any(target_arch = "aarch64", target_arch = "arm64ec"),
19298            link_name = "llvm.aarch64.neon.tbl4.v16i8"
19299        )]
19300        fn _vqtbl4q(
19301            a: int8x16_t,
19302            b: int8x16_t,
19303            c: int8x16_t,
19304            d: int8x16_t,
19305            e: uint8x16_t,
19306        ) -> int8x16_t;
19307    }
19308    unsafe { _vqtbl4q(a, b, c, d, e) }
19309}
19310#[doc = "Table look-up"]
19311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"]
19312#[inline]
19313#[cfg(target_endian = "little")]
19314#[target_feature(enable = "neon")]
19315#[cfg_attr(test, assert_instr(tbl))]
19316#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19317pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t {
19318    vqtbl4(a.0, a.1, a.2, a.3, b)
19319}
19320#[doc = "Table look-up"]
19321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"]
19322#[inline]
19323#[cfg(target_endian = "big")]
19324#[target_feature(enable = "neon")]
19325#[cfg_attr(test, assert_instr(tbl))]
19326#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19327pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t {
19328    let mut a: int8x16x4_t = a;
19329    unsafe {
19330        a.0 = simd_shuffle!(
19331            a.0,
19332            a.0,
19333            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19334        );
19335        a.1 = simd_shuffle!(
19336            a.1,
19337            a.1,
19338            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19339        );
19340        a.2 = simd_shuffle!(
19341            a.2,
19342            a.2,
19343            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19344        );
19345        a.3 = simd_shuffle!(
19346            a.3,
19347            a.3,
19348            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19349        );
19350        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
19351        let ret_val: int8x8_t = vqtbl4(a.0, a.1, a.2, a.3, b);
19352        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19353    }
19354}
19355#[doc = "Table look-up"]
19356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"]
19357#[inline]
19358#[cfg(target_endian = "little")]
19359#[target_feature(enable = "neon")]
19360#[cfg_attr(test, assert_instr(tbl))]
19361#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19362pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t {
19363    vqtbl4q(a.0, a.1, a.2, a.3, b)
19364}
19365#[doc = "Table look-up"]
19366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"]
19367#[inline]
19368#[cfg(target_endian = "big")]
19369#[target_feature(enable = "neon")]
19370#[cfg_attr(test, assert_instr(tbl))]
19371#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19372pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t {
19373    let mut a: int8x16x4_t = a;
19374    unsafe {
19375        a.0 = simd_shuffle!(
19376            a.0,
19377            a.0,
19378            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19379        );
19380        a.1 = simd_shuffle!(
19381            a.1,
19382            a.1,
19383            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19384        );
19385        a.2 = simd_shuffle!(
19386            a.2,
19387            a.2,
19388            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19389        );
19390        a.3 = simd_shuffle!(
19391            a.3,
19392            a.3,
19393            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19394        );
19395        let b: uint8x16_t =
19396            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19397        let ret_val: int8x16_t = vqtbl4q(a.0, a.1, a.2, a.3, b);
19398        simd_shuffle!(
19399            ret_val,
19400            ret_val,
19401            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19402        )
19403    }
19404}
19405#[doc = "Table look-up"]
19406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"]
19407#[inline]
19408#[cfg(target_endian = "little")]
19409#[target_feature(enable = "neon")]
19410#[cfg_attr(test, assert_instr(tbl))]
19411#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19412pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t {
19413    unsafe {
19414        transmute(vqtbl4(
19415            transmute(a.0),
19416            transmute(a.1),
19417            transmute(a.2),
19418            transmute(a.3),
19419            b,
19420        ))
19421    }
19422}
19423#[doc = "Table look-up"]
19424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"]
19425#[inline]
19426#[cfg(target_endian = "big")]
19427#[target_feature(enable = "neon")]
19428#[cfg_attr(test, assert_instr(tbl))]
19429#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19430pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t {
19431    let mut a: uint8x16x4_t = a;
19432    unsafe {
19433        a.0 = simd_shuffle!(
19434            a.0,
19435            a.0,
19436            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19437        );
19438        a.1 = simd_shuffle!(
19439            a.1,
19440            a.1,
19441            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19442        );
19443        a.2 = simd_shuffle!(
19444            a.2,
19445            a.2,
19446            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19447        );
19448        a.3 = simd_shuffle!(
19449            a.3,
19450            a.3,
19451            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19452        );
19453        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
19454        let ret_val: uint8x8_t = transmute(vqtbl4(
19455            transmute(a.0),
19456            transmute(a.1),
19457            transmute(a.2),
19458            transmute(a.3),
19459            b,
19460        ));
19461        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19462    }
19463}
19464#[doc = "Table look-up"]
19465#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
19466#[inline]
19467#[cfg(target_endian = "little")]
19468#[target_feature(enable = "neon")]
19469#[cfg_attr(test, assert_instr(tbl))]
19470#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19471pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
19472    unsafe {
19473        transmute(vqtbl4q(
19474            transmute(a.0),
19475            transmute(a.1),
19476            transmute(a.2),
19477            transmute(a.3),
19478            b,
19479        ))
19480    }
19481}
19482#[doc = "Table look-up"]
19483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
19484#[inline]
19485#[cfg(target_endian = "big")]
19486#[target_feature(enable = "neon")]
19487#[cfg_attr(test, assert_instr(tbl))]
19488#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19489pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
19490    let mut a: uint8x16x4_t = a;
19491    unsafe {
19492        a.0 = simd_shuffle!(
19493            a.0,
19494            a.0,
19495            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19496        );
19497        a.1 = simd_shuffle!(
19498            a.1,
19499            a.1,
19500            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19501        );
19502        a.2 = simd_shuffle!(
19503            a.2,
19504            a.2,
19505            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19506        );
19507        a.3 = simd_shuffle!(
19508            a.3,
19509            a.3,
19510            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19511        );
19512        let b: uint8x16_t =
19513            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19514        let ret_val: uint8x16_t = transmute(vqtbl4q(
19515            transmute(a.0),
19516            transmute(a.1),
19517            transmute(a.2),
19518            transmute(a.3),
19519            b,
19520        ));
19521        simd_shuffle!(
19522            ret_val,
19523            ret_val,
19524            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19525        )
19526    }
19527}
19528#[doc = "Table look-up"]
19529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"]
19530#[inline]
19531#[cfg(target_endian = "little")]
19532#[target_feature(enable = "neon")]
19533#[cfg_attr(test, assert_instr(tbl))]
19534#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19535pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t {
19536    unsafe {
19537        transmute(vqtbl4(
19538            transmute(a.0),
19539            transmute(a.1),
19540            transmute(a.2),
19541            transmute(a.3),
19542            b,
19543        ))
19544    }
19545}
19546#[doc = "Table look-up"]
19547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"]
19548#[inline]
19549#[cfg(target_endian = "big")]
19550#[target_feature(enable = "neon")]
19551#[cfg_attr(test, assert_instr(tbl))]
19552#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19553pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t {
19554    let mut a: poly8x16x4_t = a;
19555    unsafe {
19556        a.0 = simd_shuffle!(
19557            a.0,
19558            a.0,
19559            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19560        );
19561        a.1 = simd_shuffle!(
19562            a.1,
19563            a.1,
19564            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19565        );
19566        a.2 = simd_shuffle!(
19567            a.2,
19568            a.2,
19569            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19570        );
19571        a.3 = simd_shuffle!(
19572            a.3,
19573            a.3,
19574            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19575        );
19576        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
19577        let ret_val: poly8x8_t = transmute(vqtbl4(
19578            transmute(a.0),
19579            transmute(a.1),
19580            transmute(a.2),
19581            transmute(a.3),
19582            b,
19583        ));
19584        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19585    }
19586}
19587#[doc = "Table look-up"]
19588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"]
19589#[inline]
19590#[cfg(target_endian = "little")]
19591#[target_feature(enable = "neon")]
19592#[cfg_attr(test, assert_instr(tbl))]
19593#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19594pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t {
19595    unsafe {
19596        transmute(vqtbl4q(
19597            transmute(a.0),
19598            transmute(a.1),
19599            transmute(a.2),
19600            transmute(a.3),
19601            b,
19602        ))
19603    }
19604}
19605#[doc = "Table look-up"]
19606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"]
19607#[inline]
19608#[cfg(target_endian = "big")]
19609#[target_feature(enable = "neon")]
19610#[cfg_attr(test, assert_instr(tbl))]
19611#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19612pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t {
19613    let mut a: poly8x16x4_t = a;
19614    unsafe {
19615        a.0 = simd_shuffle!(
19616            a.0,
19617            a.0,
19618            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19619        );
19620        a.1 = simd_shuffle!(
19621            a.1,
19622            a.1,
19623            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19624        );
19625        a.2 = simd_shuffle!(
19626            a.2,
19627            a.2,
19628            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19629        );
19630        a.3 = simd_shuffle!(
19631            a.3,
19632            a.3,
19633            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19634        );
19635        let b: uint8x16_t =
19636            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19637        let ret_val: poly8x16_t = transmute(vqtbl4q(
19638            transmute(a.0),
19639            transmute(a.1),
19640            transmute(a.2),
19641            transmute(a.3),
19642            b,
19643        ));
19644        simd_shuffle!(
19645            ret_val,
19646            ret_val,
19647            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19648        )
19649    }
19650}
19651#[doc = "Extended table look-up"]
19652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"]
19653#[inline]
19654#[target_feature(enable = "neon")]
19655#[cfg_attr(test, assert_instr(tbx))]
19656#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19657fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
19658    unsafe extern "unadjusted" {
19659        #[cfg_attr(
19660            any(target_arch = "aarch64", target_arch = "arm64ec"),
19661            link_name = "llvm.aarch64.neon.tbx1.v8i8"
19662        )]
19663        fn _vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t;
19664    }
19665    unsafe { _vqtbx1(a, b, c) }
19666}
19667#[doc = "Extended table look-up"]
19668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q)"]
19669#[inline]
19670#[target_feature(enable = "neon")]
19671#[cfg_attr(test, assert_instr(tbx))]
19672#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19673fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
19674    unsafe extern "unadjusted" {
19675        #[cfg_attr(
19676            any(target_arch = "aarch64", target_arch = "arm64ec"),
19677            link_name = "llvm.aarch64.neon.tbx1.v16i8"
19678        )]
19679        fn _vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t;
19680    }
19681    unsafe { _vqtbx1q(a, b, c) }
19682}
19683#[doc = "Extended table look-up"]
19684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"]
19685#[inline]
19686#[cfg(target_endian = "little")]
19687#[target_feature(enable = "neon")]
19688#[cfg_attr(test, assert_instr(tbx))]
19689#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19690pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
19691    vqtbx1(a, b, c)
19692}
19693#[doc = "Extended table look-up"]
19694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"]
19695#[inline]
19696#[cfg(target_endian = "big")]
19697#[target_feature(enable = "neon")]
19698#[cfg_attr(test, assert_instr(tbx))]
19699#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19700pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
19701    unsafe {
19702        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
19703        let b: int8x16_t =
19704            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19705        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
19706        let ret_val: int8x8_t = vqtbx1(a, b, c);
19707        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19708    }
19709}
19710#[doc = "Extended table look-up"]
19711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"]
19712#[inline]
19713#[cfg(target_endian = "little")]
19714#[target_feature(enable = "neon")]
19715#[cfg_attr(test, assert_instr(tbx))]
19716#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19717pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
19718    vqtbx1q(a, b, c)
19719}
19720#[doc = "Extended table look-up"]
19721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"]
19722#[inline]
19723#[cfg(target_endian = "big")]
19724#[target_feature(enable = "neon")]
19725#[cfg_attr(test, assert_instr(tbx))]
19726#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19727pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
19728    unsafe {
19729        let a: int8x16_t =
19730            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19731        let b: int8x16_t =
19732            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19733        let c: uint8x16_t =
19734            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19735        let ret_val: int8x16_t = vqtbx1q(a, b, c);
19736        simd_shuffle!(
19737            ret_val,
19738            ret_val,
19739            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19740        )
19741    }
19742}
19743#[doc = "Extended table look-up"]
19744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"]
19745#[inline]
19746#[cfg(target_endian = "little")]
19747#[target_feature(enable = "neon")]
19748#[cfg_attr(test, assert_instr(tbx))]
19749#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19750pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t {
19751    unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) }
19752}
19753#[doc = "Extended table look-up"]
19754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"]
19755#[inline]
19756#[cfg(target_endian = "big")]
19757#[target_feature(enable = "neon")]
19758#[cfg_attr(test, assert_instr(tbx))]
19759#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19760pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t {
19761    unsafe {
19762        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
19763        let b: uint8x16_t =
19764            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19765        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
19766        let ret_val: uint8x8_t = transmute(vqtbx1(transmute(a), transmute(b), c));
19767        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19768    }
19769}
19770#[doc = "Extended table look-up"]
19771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"]
19772#[inline]
19773#[cfg(target_endian = "little")]
19774#[target_feature(enable = "neon")]
19775#[cfg_attr(test, assert_instr(tbx))]
19776#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19777pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
19778    unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) }
19779}
19780#[doc = "Extended table look-up"]
19781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"]
19782#[inline]
19783#[cfg(target_endian = "big")]
19784#[target_feature(enable = "neon")]
19785#[cfg_attr(test, assert_instr(tbx))]
19786#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19787pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
19788    unsafe {
19789        let a: uint8x16_t =
19790            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19791        let b: uint8x16_t =
19792            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19793        let c: uint8x16_t =
19794            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19795        let ret_val: uint8x16_t = transmute(vqtbx1q(transmute(a), transmute(b), c));
19796        simd_shuffle!(
19797            ret_val,
19798            ret_val,
19799            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19800        )
19801    }
19802}
19803#[doc = "Extended table look-up"]
19804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"]
19805#[inline]
19806#[cfg(target_endian = "little")]
19807#[target_feature(enable = "neon")]
19808#[cfg_attr(test, assert_instr(tbx))]
19809#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19810pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t {
19811    unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) }
19812}
19813#[doc = "Extended table look-up"]
19814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"]
19815#[inline]
19816#[cfg(target_endian = "big")]
19817#[target_feature(enable = "neon")]
19818#[cfg_attr(test, assert_instr(tbx))]
19819#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19820pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t {
19821    unsafe {
19822        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
19823        let b: poly8x16_t =
19824            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19825        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
19826        let ret_val: poly8x8_t = transmute(vqtbx1(transmute(a), transmute(b), c));
19827        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19828    }
19829}
19830#[doc = "Extended table look-up"]
19831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"]
19832#[inline]
19833#[cfg(target_endian = "little")]
19834#[target_feature(enable = "neon")]
19835#[cfg_attr(test, assert_instr(tbx))]
19836#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19837pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t {
19838    unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) }
19839}
19840#[doc = "Extended table look-up"]
19841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"]
19842#[inline]
19843#[cfg(target_endian = "big")]
19844#[target_feature(enable = "neon")]
19845#[cfg_attr(test, assert_instr(tbx))]
19846#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19847pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t {
19848    unsafe {
19849        let a: poly8x16_t =
19850            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19851        let b: poly8x16_t =
19852            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19853        let c: uint8x16_t =
19854            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19855        let ret_val: poly8x16_t = transmute(vqtbx1q(transmute(a), transmute(b), c));
19856        simd_shuffle!(
19857            ret_val,
19858            ret_val,
19859            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19860        )
19861    }
19862}
19863#[doc = "Extended table look-up"]
19864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"]
19865#[inline]
19866#[target_feature(enable = "neon")]
19867#[cfg_attr(test, assert_instr(tbx))]
19868#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19869fn vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t {
19870    unsafe extern "unadjusted" {
19871        #[cfg_attr(
19872            any(target_arch = "aarch64", target_arch = "arm64ec"),
19873            link_name = "llvm.aarch64.neon.tbx2.v8i8"
19874        )]
19875        fn _vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t;
19876    }
19877    unsafe { _vqtbx2(a, b, c, d) }
19878}
19879#[doc = "Extended table look-up"]
19880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q)"]
19881#[inline]
19882#[target_feature(enable = "neon")]
19883#[cfg_attr(test, assert_instr(tbx))]
19884#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19885fn vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t {
19886    unsafe extern "unadjusted" {
19887        #[cfg_attr(
19888            any(target_arch = "aarch64", target_arch = "arm64ec"),
19889            link_name = "llvm.aarch64.neon.tbx2.v16i8"
19890        )]
19891        fn _vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t;
19892    }
19893    unsafe { _vqtbx2q(a, b, c, d) }
19894}
19895#[doc = "Extended table look-up"]
19896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"]
19897#[inline]
19898#[cfg(target_endian = "little")]
19899#[target_feature(enable = "neon")]
19900#[cfg_attr(test, assert_instr(tbx))]
19901#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19902pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t {
19903    vqtbx2(a, b.0, b.1, c)
19904}
19905#[doc = "Extended table look-up"]
19906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"]
19907#[inline]
19908#[cfg(target_endian = "big")]
19909#[target_feature(enable = "neon")]
19910#[cfg_attr(test, assert_instr(tbx))]
19911#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19912pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t {
19913    let mut b: int8x16x2_t = b;
19914    unsafe {
19915        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
19916        b.0 = simd_shuffle!(
19917            b.0,
19918            b.0,
19919            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19920        );
19921        b.1 = simd_shuffle!(
19922            b.1,
19923            b.1,
19924            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19925        );
19926        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
19927        let ret_val: int8x8_t = vqtbx2(a, b.0, b.1, c);
19928        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
19929    }
19930}
19931#[doc = "Extended table look-up"]
19932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"]
19933#[inline]
19934#[cfg(target_endian = "little")]
19935#[target_feature(enable = "neon")]
19936#[cfg_attr(test, assert_instr(tbx))]
19937#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19938pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t {
19939    vqtbx2q(a, b.0, b.1, c)
19940}
19941#[doc = "Extended table look-up"]
19942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"]
19943#[inline]
19944#[cfg(target_endian = "big")]
19945#[target_feature(enable = "neon")]
19946#[cfg_attr(test, assert_instr(tbx))]
19947#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19948pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t {
19949    let mut b: int8x16x2_t = b;
19950    unsafe {
19951        let a: int8x16_t =
19952            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19953        b.0 = simd_shuffle!(
19954            b.0,
19955            b.0,
19956            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19957        );
19958        b.1 = simd_shuffle!(
19959            b.1,
19960            b.1,
19961            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19962        );
19963        let c: uint8x16_t =
19964            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
19965        let ret_val: int8x16_t = vqtbx2q(a, b.0, b.1, c);
19966        simd_shuffle!(
19967            ret_val,
19968            ret_val,
19969            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19970        )
19971    }
19972}
19973#[doc = "Extended table look-up"]
19974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"]
19975#[inline]
19976#[cfg(target_endian = "little")]
19977#[target_feature(enable = "neon")]
19978#[cfg_attr(test, assert_instr(tbx))]
19979#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19980pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t {
19981    unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) }
19982}
19983#[doc = "Extended table look-up"]
19984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"]
19985#[inline]
19986#[cfg(target_endian = "big")]
19987#[target_feature(enable = "neon")]
19988#[cfg_attr(test, assert_instr(tbx))]
19989#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19990pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t {
19991    let mut b: uint8x16x2_t = b;
19992    unsafe {
19993        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
19994        b.0 = simd_shuffle!(
19995            b.0,
19996            b.0,
19997            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19998        );
19999        b.1 = simd_shuffle!(
20000            b.1,
20001            b.1,
20002            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20003        );
20004        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
20005        let ret_val: uint8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c));
20006        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
20007    }
20008}
20009#[doc = "Extended table look-up"]
20010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"]
20011#[inline]
20012#[cfg(target_endian = "little")]
20013#[target_feature(enable = "neon")]
20014#[cfg_attr(test, assert_instr(tbx))]
20015#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20016pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t {
20017    unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) }
20018}
20019#[doc = "Extended table look-up"]
20020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"]
20021#[inline]
20022#[cfg(target_endian = "big")]
20023#[target_feature(enable = "neon")]
20024#[cfg_attr(test, assert_instr(tbx))]
20025#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20026pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t {
20027    let mut b: uint8x16x2_t = b;
20028    unsafe {
20029        let a: uint8x16_t =
20030            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20031        b.0 = simd_shuffle!(
20032            b.0,
20033            b.0,
20034            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20035        );
20036        b.1 = simd_shuffle!(
20037            b.1,
20038            b.1,
20039            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20040        );
20041        let c: uint8x16_t =
20042            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20043        let ret_val: uint8x16_t =
20044            transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c));
20045        simd_shuffle!(
20046            ret_val,
20047            ret_val,
20048            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20049        )
20050    }
20051}
20052#[doc = "Extended table look-up"]
20053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"]
20054#[inline]
20055#[cfg(target_endian = "little")]
20056#[target_feature(enable = "neon")]
20057#[cfg_attr(test, assert_instr(tbx))]
20058#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20059pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t {
20060    unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) }
20061}
20062#[doc = "Extended table look-up"]
20063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"]
20064#[inline]
20065#[cfg(target_endian = "big")]
20066#[target_feature(enable = "neon")]
20067#[cfg_attr(test, assert_instr(tbx))]
20068#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20069pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t {
20070    let mut b: poly8x16x2_t = b;
20071    unsafe {
20072        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
20073        b.0 = simd_shuffle!(
20074            b.0,
20075            b.0,
20076            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20077        );
20078        b.1 = simd_shuffle!(
20079            b.1,
20080            b.1,
20081            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20082        );
20083        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
20084        let ret_val: poly8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c));
20085        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
20086    }
20087}
20088#[doc = "Extended table look-up"]
20089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"]
20090#[inline]
20091#[cfg(target_endian = "little")]
20092#[target_feature(enable = "neon")]
20093#[cfg_attr(test, assert_instr(tbx))]
20094#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20095pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t {
20096    unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) }
20097}
20098#[doc = "Extended table look-up"]
20099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"]
20100#[inline]
20101#[cfg(target_endian = "big")]
20102#[target_feature(enable = "neon")]
20103#[cfg_attr(test, assert_instr(tbx))]
20104#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20105pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t {
20106    let mut b: poly8x16x2_t = b;
20107    unsafe {
20108        let a: poly8x16_t =
20109            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20110        b.0 = simd_shuffle!(
20111            b.0,
20112            b.0,
20113            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20114        );
20115        b.1 = simd_shuffle!(
20116            b.1,
20117            b.1,
20118            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20119        );
20120        let c: uint8x16_t =
20121            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20122        let ret_val: poly8x16_t =
20123            transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c));
20124        simd_shuffle!(
20125            ret_val,
20126            ret_val,
20127            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20128        )
20129    }
20130}
20131#[doc = "Extended table look-up"]
20132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"]
20133#[inline]
20134#[target_feature(enable = "neon")]
20135#[cfg_attr(test, assert_instr(tbx))]
20136#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20137fn vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -> int8x8_t {
20138    unsafe extern "unadjusted" {
20139        #[cfg_attr(
20140            any(target_arch = "aarch64", target_arch = "arm64ec"),
20141            link_name = "llvm.aarch64.neon.tbx3.v8i8"
20142        )]
20143        fn _vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t)
20144            -> int8x8_t;
20145    }
20146    unsafe { _vqtbx3(a, b, c, d, e) }
20147}
20148#[doc = "Extended table look-up"]
20149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q)"]
20150#[inline]
20151#[target_feature(enable = "neon")]
20152#[cfg_attr(test, assert_instr(tbx))]
20153#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20154fn vqtbx3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t) -> int8x16_t {
20155    unsafe extern "unadjusted" {
20156        #[cfg_attr(
20157            any(target_arch = "aarch64", target_arch = "arm64ec"),
20158            link_name = "llvm.aarch64.neon.tbx3.v16i8"
20159        )]
20160        fn _vqtbx3q(
20161            a: int8x16_t,
20162            b: int8x16_t,
20163            c: int8x16_t,
20164            d: int8x16_t,
20165            e: uint8x16_t,
20166        ) -> int8x16_t;
20167    }
20168    unsafe { _vqtbx3q(a, b, c, d, e) }
20169}
20170#[doc = "Extended table look-up"]
20171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"]
20172#[inline]
20173#[cfg(target_endian = "little")]
20174#[target_feature(enable = "neon")]
20175#[cfg_attr(test, assert_instr(tbx))]
20176#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20177pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t {
20178    vqtbx3(a, b.0, b.1, b.2, c)
20179}
20180#[doc = "Extended table look-up"]
20181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"]
20182#[inline]
20183#[cfg(target_endian = "big")]
20184#[target_feature(enable = "neon")]
20185#[cfg_attr(test, assert_instr(tbx))]
20186#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20187pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t {
20188    let mut b: int8x16x3_t = b;
20189    unsafe {
20190        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
20191        b.0 = simd_shuffle!(
20192            b.0,
20193            b.0,
20194            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20195        );
20196        b.1 = simd_shuffle!(
20197            b.1,
20198            b.1,
20199            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20200        );
20201        b.2 = simd_shuffle!(
20202            b.2,
20203            b.2,
20204            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20205        );
20206        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
20207        let ret_val: int8x8_t = vqtbx3(a, b.0, b.1, b.2, c);
20208        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
20209    }
20210}
20211#[doc = "Extended table look-up"]
20212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"]
20213#[inline]
20214#[cfg(target_endian = "little")]
20215#[target_feature(enable = "neon")]
20216#[cfg_attr(test, assert_instr(tbx))]
20217#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20218pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t {
20219    vqtbx3q(a, b.0, b.1, b.2, c)
20220}
20221#[doc = "Extended table look-up"]
20222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"]
20223#[inline]
20224#[cfg(target_endian = "big")]
20225#[target_feature(enable = "neon")]
20226#[cfg_attr(test, assert_instr(tbx))]
20227#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20228pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t {
20229    let mut b: int8x16x3_t = b;
20230    unsafe {
20231        let a: int8x16_t =
20232            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20233        b.0 = simd_shuffle!(
20234            b.0,
20235            b.0,
20236            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20237        );
20238        b.1 = simd_shuffle!(
20239            b.1,
20240            b.1,
20241            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20242        );
20243        b.2 = simd_shuffle!(
20244            b.2,
20245            b.2,
20246            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20247        );
20248        let c: uint8x16_t =
20249            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20250        let ret_val: int8x16_t = vqtbx3q(a, b.0, b.1, b.2, c);
20251        simd_shuffle!(
20252            ret_val,
20253            ret_val,
20254            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20255        )
20256    }
20257}
20258#[doc = "Extended table look-up"]
20259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"]
20260#[inline]
20261#[cfg(target_endian = "little")]
20262#[target_feature(enable = "neon")]
20263#[cfg_attr(test, assert_instr(tbx))]
20264#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20265pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t {
20266    unsafe {
20267        transmute(vqtbx3(
20268            transmute(a),
20269            transmute(b.0),
20270            transmute(b.1),
20271            transmute(b.2),
20272            c,
20273        ))
20274    }
20275}
20276#[doc = "Extended table look-up"]
20277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"]
20278#[inline]
20279#[cfg(target_endian = "big")]
20280#[target_feature(enable = "neon")]
20281#[cfg_attr(test, assert_instr(tbx))]
20282#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20283pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t {
20284    let mut b: uint8x16x3_t = b;
20285    unsafe {
20286        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
20287        b.0 = simd_shuffle!(
20288            b.0,
20289            b.0,
20290            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20291        );
20292        b.1 = simd_shuffle!(
20293            b.1,
20294            b.1,
20295            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20296        );
20297        b.2 = simd_shuffle!(
20298            b.2,
20299            b.2,
20300            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20301        );
20302        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
20303        let ret_val: uint8x8_t = transmute(vqtbx3(
20304            transmute(a),
20305            transmute(b.0),
20306            transmute(b.1),
20307            transmute(b.2),
20308            c,
20309        ));
20310        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
20311    }
20312}
20313#[doc = "Extended table look-up"]
20314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"]
20315#[inline]
20316#[cfg(target_endian = "little")]
20317#[target_feature(enable = "neon")]
20318#[cfg_attr(test, assert_instr(tbx))]
20319#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20320pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t {
20321    unsafe {
20322        transmute(vqtbx3q(
20323            transmute(a),
20324            transmute(b.0),
20325            transmute(b.1),
20326            transmute(b.2),
20327            c,
20328        ))
20329    }
20330}
20331#[doc = "Extended table look-up"]
20332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"]
20333#[inline]
20334#[cfg(target_endian = "big")]
20335#[target_feature(enable = "neon")]
20336#[cfg_attr(test, assert_instr(tbx))]
20337#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20338pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t {
20339    let mut b: uint8x16x3_t = b;
20340    unsafe {
20341        let a: uint8x16_t =
20342            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20343        b.0 = simd_shuffle!(
20344            b.0,
20345            b.0,
20346            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20347        );
20348        b.1 = simd_shuffle!(
20349            b.1,
20350            b.1,
20351            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20352        );
20353        b.2 = simd_shuffle!(
20354            b.2,
20355            b.2,
20356            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20357        );
20358        let c: uint8x16_t =
20359            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20360        let ret_val: uint8x16_t = transmute(vqtbx3q(
20361            transmute(a),
20362            transmute(b.0),
20363            transmute(b.1),
20364            transmute(b.2),
20365            c,
20366        ));
20367        simd_shuffle!(
20368            ret_val,
20369            ret_val,
20370            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20371        )
20372    }
20373}
20374#[doc = "Extended table look-up"]
20375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"]
20376#[inline]
20377#[cfg(target_endian = "little")]
20378#[target_feature(enable = "neon")]
20379#[cfg_attr(test, assert_instr(tbx))]
20380#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20381pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t {
20382    unsafe {
20383        transmute(vqtbx3(
20384            transmute(a),
20385            transmute(b.0),
20386            transmute(b.1),
20387            transmute(b.2),
20388            c,
20389        ))
20390    }
20391}
20392#[doc = "Extended table look-up"]
20393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"]
20394#[inline]
20395#[cfg(target_endian = "big")]
20396#[target_feature(enable = "neon")]
20397#[cfg_attr(test, assert_instr(tbx))]
20398#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20399pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t {
20400    let mut b: poly8x16x3_t = b;
20401    unsafe {
20402        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
20403        b.0 = simd_shuffle!(
20404            b.0,
20405            b.0,
20406            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20407        );
20408        b.1 = simd_shuffle!(
20409            b.1,
20410            b.1,
20411            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20412        );
20413        b.2 = simd_shuffle!(
20414            b.2,
20415            b.2,
20416            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20417        );
20418        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
20419        let ret_val: poly8x8_t = transmute(vqtbx3(
20420            transmute(a),
20421            transmute(b.0),
20422            transmute(b.1),
20423            transmute(b.2),
20424            c,
20425        ));
20426        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
20427    }
20428}
20429#[doc = "Extended table look-up"]
20430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"]
20431#[inline]
20432#[cfg(target_endian = "little")]
20433#[target_feature(enable = "neon")]
20434#[cfg_attr(test, assert_instr(tbx))]
20435#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20436pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t {
20437    unsafe {
20438        transmute(vqtbx3q(
20439            transmute(a),
20440            transmute(b.0),
20441            transmute(b.1),
20442            transmute(b.2),
20443            c,
20444        ))
20445    }
20446}
20447#[doc = "Extended table look-up"]
20448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"]
20449#[inline]
20450#[cfg(target_endian = "big")]
20451#[target_feature(enable = "neon")]
20452#[cfg_attr(test, assert_instr(tbx))]
20453#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20454pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t {
20455    let mut b: poly8x16x3_t = b;
20456    unsafe {
20457        let a: poly8x16_t =
20458            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20459        b.0 = simd_shuffle!(
20460            b.0,
20461            b.0,
20462            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20463        );
20464        b.1 = simd_shuffle!(
20465            b.1,
20466            b.1,
20467            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20468        );
20469        b.2 = simd_shuffle!(
20470            b.2,
20471            b.2,
20472            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20473        );
20474        let c: uint8x16_t =
20475            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20476        let ret_val: poly8x16_t = transmute(vqtbx3q(
20477            transmute(a),
20478            transmute(b.0),
20479            transmute(b.1),
20480            transmute(b.2),
20481            c,
20482        ));
20483        simd_shuffle!(
20484            ret_val,
20485            ret_val,
20486            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20487        )
20488    }
20489}
20490#[doc = "Extended table look-up"]
20491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"]
20492#[inline]
20493#[target_feature(enable = "neon")]
20494#[cfg_attr(test, assert_instr(tbx))]
20495#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20496fn vqtbx4(
20497    a: int8x8_t,
20498    b: int8x16_t,
20499    c: int8x16_t,
20500    d: int8x16_t,
20501    e: int8x16_t,
20502    f: uint8x8_t,
20503) -> int8x8_t {
20504    unsafe extern "unadjusted" {
20505        #[cfg_attr(
20506            any(target_arch = "aarch64", target_arch = "arm64ec"),
20507            link_name = "llvm.aarch64.neon.tbx4.v8i8"
20508        )]
20509        fn _vqtbx4(
20510            a: int8x8_t,
20511            b: int8x16_t,
20512            c: int8x16_t,
20513            d: int8x16_t,
20514            e: int8x16_t,
20515            f: uint8x8_t,
20516        ) -> int8x8_t;
20517    }
20518    unsafe { _vqtbx4(a, b, c, d, e, f) }
20519}
20520#[doc = "Extended table look-up"]
20521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q)"]
20522#[inline]
20523#[target_feature(enable = "neon")]
20524#[cfg_attr(test, assert_instr(tbx))]
20525#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20526fn vqtbx4q(
20527    a: int8x16_t,
20528    b: int8x16_t,
20529    c: int8x16_t,
20530    d: int8x16_t,
20531    e: int8x16_t,
20532    f: uint8x16_t,
20533) -> int8x16_t {
20534    unsafe extern "unadjusted" {
20535        #[cfg_attr(
20536            any(target_arch = "aarch64", target_arch = "arm64ec"),
20537            link_name = "llvm.aarch64.neon.tbx4.v16i8"
20538        )]
20539        fn _vqtbx4q(
20540            a: int8x16_t,
20541            b: int8x16_t,
20542            c: int8x16_t,
20543            d: int8x16_t,
20544            e: int8x16_t,
20545            f: uint8x16_t,
20546        ) -> int8x16_t;
20547    }
20548    unsafe { _vqtbx4q(a, b, c, d, e, f) }
20549}
20550#[doc = "Extended table look-up"]
20551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"]
20552#[inline]
20553#[cfg(target_endian = "little")]
20554#[target_feature(enable = "neon")]
20555#[cfg_attr(test, assert_instr(tbx))]
20556#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20557pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t {
20558    vqtbx4(a, b.0, b.1, b.2, b.3, c)
20559}
20560#[doc = "Extended table look-up"]
20561#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"]
20562#[inline]
20563#[cfg(target_endian = "big")]
20564#[target_feature(enable = "neon")]
20565#[cfg_attr(test, assert_instr(tbx))]
20566#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20567pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t {
20568    let mut b: int8x16x4_t = b;
20569    unsafe {
20570        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
20571        b.0 = simd_shuffle!(
20572            b.0,
20573            b.0,
20574            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20575        );
20576        b.1 = simd_shuffle!(
20577            b.1,
20578            b.1,
20579            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20580        );
20581        b.2 = simd_shuffle!(
20582            b.2,
20583            b.2,
20584            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20585        );
20586        b.3 = simd_shuffle!(
20587            b.3,
20588            b.3,
20589            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20590        );
20591        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
20592        let ret_val: int8x8_t = vqtbx4(a, b.0, b.1, b.2, b.3, c);
20593        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
20594    }
20595}
20596#[doc = "Extended table look-up"]
20597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"]
20598#[inline]
20599#[cfg(target_endian = "little")]
20600#[target_feature(enable = "neon")]
20601#[cfg_attr(test, assert_instr(tbx))]
20602#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20603pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t {
20604    vqtbx4q(a, b.0, b.1, b.2, b.3, c)
20605}
20606#[doc = "Extended table look-up"]
20607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"]
20608#[inline]
20609#[cfg(target_endian = "big")]
20610#[target_feature(enable = "neon")]
20611#[cfg_attr(test, assert_instr(tbx))]
20612#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20613pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t {
20614    let mut b: int8x16x4_t = b;
20615    unsafe {
20616        let a: int8x16_t =
20617            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20618        b.0 = simd_shuffle!(
20619            b.0,
20620            b.0,
20621            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20622        );
20623        b.1 = simd_shuffle!(
20624            b.1,
20625            b.1,
20626            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20627        );
20628        b.2 = simd_shuffle!(
20629            b.2,
20630            b.2,
20631            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20632        );
20633        b.3 = simd_shuffle!(
20634            b.3,
20635            b.3,
20636            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20637        );
20638        let c: uint8x16_t =
20639            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20640        let ret_val: int8x16_t = vqtbx4q(a, b.0, b.1, b.2, b.3, c);
20641        simd_shuffle!(
20642            ret_val,
20643            ret_val,
20644            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20645        )
20646    }
20647}
20648#[doc = "Extended table look-up"]
20649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
20650#[inline]
20651#[cfg(target_endian = "little")]
20652#[target_feature(enable = "neon")]
20653#[cfg_attr(test, assert_instr(tbx))]
20654#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20655pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
20656    unsafe {
20657        transmute(vqtbx4(
20658            transmute(a),
20659            transmute(b.0),
20660            transmute(b.1),
20661            transmute(b.2),
20662            transmute(b.3),
20663            c,
20664        ))
20665    }
20666}
20667#[doc = "Extended table look-up"]
20668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
20669#[inline]
20670#[cfg(target_endian = "big")]
20671#[target_feature(enable = "neon")]
20672#[cfg_attr(test, assert_instr(tbx))]
20673#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20674pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
20675    let mut b: uint8x16x4_t = b;
20676    unsafe {
20677        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
20678        b.0 = simd_shuffle!(
20679            b.0,
20680            b.0,
20681            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20682        );
20683        b.1 = simd_shuffle!(
20684            b.1,
20685            b.1,
20686            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20687        );
20688        b.2 = simd_shuffle!(
20689            b.2,
20690            b.2,
20691            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20692        );
20693        b.3 = simd_shuffle!(
20694            b.3,
20695            b.3,
20696            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20697        );
20698        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
20699        let ret_val: uint8x8_t = transmute(vqtbx4(
20700            transmute(a),
20701            transmute(b.0),
20702            transmute(b.1),
20703            transmute(b.2),
20704            transmute(b.3),
20705            c,
20706        ));
20707        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
20708    }
20709}
20710#[doc = "Extended table look-up"]
20711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
20712#[inline]
20713#[cfg(target_endian = "little")]
20714#[target_feature(enable = "neon")]
20715#[cfg_attr(test, assert_instr(tbx))]
20716#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20717pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
20718    unsafe {
20719        transmute(vqtbx4q(
20720            transmute(a),
20721            transmute(b.0),
20722            transmute(b.1),
20723            transmute(b.2),
20724            transmute(b.3),
20725            c,
20726        ))
20727    }
20728}
20729#[doc = "Extended table look-up"]
20730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
20731#[inline]
20732#[cfg(target_endian = "big")]
20733#[target_feature(enable = "neon")]
20734#[cfg_attr(test, assert_instr(tbx))]
20735#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20736pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
20737    let mut b: uint8x16x4_t = b;
20738    unsafe {
20739        let a: uint8x16_t =
20740            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20741        b.0 = simd_shuffle!(
20742            b.0,
20743            b.0,
20744            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20745        );
20746        b.1 = simd_shuffle!(
20747            b.1,
20748            b.1,
20749            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20750        );
20751        b.2 = simd_shuffle!(
20752            b.2,
20753            b.2,
20754            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20755        );
20756        b.3 = simd_shuffle!(
20757            b.3,
20758            b.3,
20759            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20760        );
20761        let c: uint8x16_t =
20762            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20763        let ret_val: uint8x16_t = transmute(vqtbx4q(
20764            transmute(a),
20765            transmute(b.0),
20766            transmute(b.1),
20767            transmute(b.2),
20768            transmute(b.3),
20769            c,
20770        ));
20771        simd_shuffle!(
20772            ret_val,
20773            ret_val,
20774            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20775        )
20776    }
20777}
20778#[doc = "Extended table look-up"]
20779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
20780#[inline]
20781#[cfg(target_endian = "little")]
20782#[target_feature(enable = "neon")]
20783#[cfg_attr(test, assert_instr(tbx))]
20784#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20785pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
20786    unsafe {
20787        transmute(vqtbx4(
20788            transmute(a),
20789            transmute(b.0),
20790            transmute(b.1),
20791            transmute(b.2),
20792            transmute(b.3),
20793            c,
20794        ))
20795    }
20796}
20797#[doc = "Extended table look-up"]
20798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
20799#[inline]
20800#[cfg(target_endian = "big")]
20801#[target_feature(enable = "neon")]
20802#[cfg_attr(test, assert_instr(tbx))]
20803#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20804pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
20805    let mut b: poly8x16x4_t = b;
20806    unsafe {
20807        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
20808        b.0 = simd_shuffle!(
20809            b.0,
20810            b.0,
20811            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20812        );
20813        b.1 = simd_shuffle!(
20814            b.1,
20815            b.1,
20816            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20817        );
20818        b.2 = simd_shuffle!(
20819            b.2,
20820            b.2,
20821            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20822        );
20823        b.3 = simd_shuffle!(
20824            b.3,
20825            b.3,
20826            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20827        );
20828        let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]);
20829        let ret_val: poly8x8_t = transmute(vqtbx4(
20830            transmute(a),
20831            transmute(b.0),
20832            transmute(b.1),
20833            transmute(b.2),
20834            transmute(b.3),
20835            c,
20836        ));
20837        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
20838    }
20839}
20840#[doc = "Extended table look-up"]
20841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"]
20842#[inline]
20843#[cfg(target_endian = "little")]
20844#[target_feature(enable = "neon")]
20845#[cfg_attr(test, assert_instr(tbx))]
20846#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20847pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
20848    unsafe {
20849        transmute(vqtbx4q(
20850            transmute(a),
20851            transmute(b.0),
20852            transmute(b.1),
20853            transmute(b.2),
20854            transmute(b.3),
20855            c,
20856        ))
20857    }
20858}
20859#[doc = "Extended table look-up"]
20860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"]
20861#[inline]
20862#[cfg(target_endian = "big")]
20863#[target_feature(enable = "neon")]
20864#[cfg_attr(test, assert_instr(tbx))]
20865#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20866pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
20867    let mut b: poly8x16x4_t = b;
20868    unsafe {
20869        let a: poly8x16_t =
20870            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20871        b.0 = simd_shuffle!(
20872            b.0,
20873            b.0,
20874            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20875        );
20876        b.1 = simd_shuffle!(
20877            b.1,
20878            b.1,
20879            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20880        );
20881        b.2 = simd_shuffle!(
20882            b.2,
20883            b.2,
20884            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20885        );
20886        b.3 = simd_shuffle!(
20887            b.3,
20888            b.3,
20889            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20890        );
20891        let c: uint8x16_t =
20892            simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
20893        let ret_val: poly8x16_t = transmute(vqtbx4q(
20894            transmute(a),
20895            transmute(b.0),
20896            transmute(b.1),
20897            transmute(b.2),
20898            transmute(b.3),
20899            c,
20900        ));
20901        simd_shuffle!(
20902            ret_val,
20903            ret_val,
20904            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20905        )
20906    }
20907}
20908#[doc = "Rotate and exclusive OR"]
20909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"]
20910#[inline]
20911#[target_feature(enable = "neon,sha3")]
20912#[cfg_attr(test, assert_instr(rax1))]
20913#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
20914pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
20915    unsafe extern "unadjusted" {
20916        #[cfg_attr(
20917            any(target_arch = "aarch64", target_arch = "arm64ec"),
20918            link_name = "llvm.aarch64.crypto.rax1"
20919        )]
20920        fn _vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
20921    }
20922    unsafe { _vrax1q_u64(a, b) }
20923}
20924#[doc = "Reverse bit order"]
20925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"]
20926#[inline]
20927#[target_feature(enable = "neon")]
20928#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20929#[cfg_attr(test, assert_instr(rbit))]
20930pub fn vrbit_s8(a: int8x8_t) -> int8x8_t {
20931    unsafe { simd_bitreverse(a) }
20932}
20933#[doc = "Reverse bit order"]
20934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"]
20935#[inline]
20936#[target_feature(enable = "neon")]
20937#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20938#[cfg_attr(test, assert_instr(rbit))]
20939pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t {
20940    unsafe { simd_bitreverse(a) }
20941}
20942#[doc = "Reverse bit order"]
20943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
20944#[inline]
20945#[target_feature(enable = "neon")]
20946#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20947#[cfg_attr(test, assert_instr(rbit))]
20948pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
20949    unsafe { transmute(vrbit_s8(transmute(a))) }
20950}
20951#[doc = "Reverse bit order"]
20952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"]
20953#[inline]
20954#[target_feature(enable = "neon")]
20955#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20956#[cfg_attr(test, assert_instr(rbit))]
20957pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
20958    unsafe { transmute(vrbitq_s8(transmute(a))) }
20959}
20960#[doc = "Reverse bit order"]
20961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"]
20962#[inline]
20963#[target_feature(enable = "neon")]
20964#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20965#[cfg_attr(test, assert_instr(rbit))]
20966pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
20967    unsafe { transmute(vrbit_s8(transmute(a))) }
20968}
20969#[doc = "Reverse bit order"]
20970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"]
20971#[inline]
20972#[target_feature(enable = "neon")]
20973#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20974#[cfg_attr(test, assert_instr(rbit))]
20975pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
20976    unsafe { transmute(vrbitq_s8(transmute(a))) }
20977}
20978#[doc = "Reciprocal estimate."]
20979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"]
20980#[inline]
20981#[target_feature(enable = "neon")]
20982#[cfg_attr(test, assert_instr(frecpe))]
20983#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20984pub fn vrecpe_f64(a: float64x1_t) -> float64x1_t {
20985    unsafe extern "unadjusted" {
20986        #[cfg_attr(
20987            any(target_arch = "aarch64", target_arch = "arm64ec"),
20988            link_name = "llvm.aarch64.neon.frecpe.v1f64"
20989        )]
20990        fn _vrecpe_f64(a: float64x1_t) -> float64x1_t;
20991    }
20992    unsafe { _vrecpe_f64(a) }
20993}
20994#[doc = "Reciprocal estimate."]
20995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)"]
20996#[inline]
20997#[target_feature(enable = "neon")]
20998#[cfg_attr(test, assert_instr(frecpe))]
20999#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21000pub fn vrecpeq_f64(a: float64x2_t) -> float64x2_t {
21001    unsafe extern "unadjusted" {
21002        #[cfg_attr(
21003            any(target_arch = "aarch64", target_arch = "arm64ec"),
21004            link_name = "llvm.aarch64.neon.frecpe.v2f64"
21005        )]
21006        fn _vrecpeq_f64(a: float64x2_t) -> float64x2_t;
21007    }
21008    unsafe { _vrecpeq_f64(a) }
21009}
21010#[doc = "Reciprocal estimate."]
21011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64)"]
21012#[inline]
21013#[target_feature(enable = "neon")]
21014#[cfg_attr(test, assert_instr(frecpe))]
21015#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21016pub fn vrecped_f64(a: f64) -> f64 {
21017    unsafe extern "unadjusted" {
21018        #[cfg_attr(
21019            any(target_arch = "aarch64", target_arch = "arm64ec"),
21020            link_name = "llvm.aarch64.neon.frecpe.f64"
21021        )]
21022        fn _vrecped_f64(a: f64) -> f64;
21023    }
21024    unsafe { _vrecped_f64(a) }
21025}
21026#[doc = "Reciprocal estimate."]
21027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)"]
21028#[inline]
21029#[target_feature(enable = "neon")]
21030#[cfg_attr(test, assert_instr(frecpe))]
21031#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21032pub fn vrecpes_f32(a: f32) -> f32 {
21033    unsafe extern "unadjusted" {
21034        #[cfg_attr(
21035            any(target_arch = "aarch64", target_arch = "arm64ec"),
21036            link_name = "llvm.aarch64.neon.frecpe.f32"
21037        )]
21038        fn _vrecpes_f32(a: f32) -> f32;
21039    }
21040    unsafe { _vrecpes_f32(a) }
21041}
21042#[doc = "Reciprocal estimate."]
21043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeh_f16)"]
21044#[inline]
21045#[cfg_attr(test, assert_instr(frecpe))]
21046#[target_feature(enable = "neon,fp16")]
21047#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21048#[cfg(not(target_arch = "arm64ec"))]
21049pub fn vrecpeh_f16(a: f16) -> f16 {
21050    unsafe extern "unadjusted" {
21051        #[cfg_attr(
21052            any(target_arch = "aarch64", target_arch = "arm64ec"),
21053            link_name = "llvm.aarch64.neon.frecpe.f16"
21054        )]
21055        fn _vrecpeh_f16(a: f16) -> f16;
21056    }
21057    unsafe { _vrecpeh_f16(a) }
21058}
21059#[doc = "Floating-point reciprocal step"]
21060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)"]
21061#[inline]
21062#[target_feature(enable = "neon")]
21063#[cfg_attr(test, assert_instr(frecps))]
21064#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21065pub fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
21066    unsafe extern "unadjusted" {
21067        #[cfg_attr(
21068            any(target_arch = "aarch64", target_arch = "arm64ec"),
21069            link_name = "llvm.aarch64.neon.frecps.v1f64"
21070        )]
21071        fn _vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
21072    }
21073    unsafe { _vrecps_f64(a, b) }
21074}
21075#[doc = "Floating-point reciprocal step"]
21076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)"]
21077#[inline]
21078#[target_feature(enable = "neon")]
21079#[cfg_attr(test, assert_instr(frecps))]
21080#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21081pub fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
21082    unsafe extern "unadjusted" {
21083        #[cfg_attr(
21084            any(target_arch = "aarch64", target_arch = "arm64ec"),
21085            link_name = "llvm.aarch64.neon.frecps.v2f64"
21086        )]
21087        fn _vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
21088    }
21089    unsafe { _vrecpsq_f64(a, b) }
21090}
21091#[doc = "Floating-point reciprocal step"]
21092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64)"]
21093#[inline]
21094#[target_feature(enable = "neon")]
21095#[cfg_attr(test, assert_instr(frecps))]
21096#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21097pub fn vrecpsd_f64(a: f64, b: f64) -> f64 {
21098    unsafe extern "unadjusted" {
21099        #[cfg_attr(
21100            any(target_arch = "aarch64", target_arch = "arm64ec"),
21101            link_name = "llvm.aarch64.neon.frecps.f64"
21102        )]
21103        fn _vrecpsd_f64(a: f64, b: f64) -> f64;
21104    }
21105    unsafe { _vrecpsd_f64(a, b) }
21106}
21107#[doc = "Floating-point reciprocal step"]
21108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)"]
21109#[inline]
21110#[target_feature(enable = "neon")]
21111#[cfg_attr(test, assert_instr(frecps))]
21112#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21113pub fn vrecpss_f32(a: f32, b: f32) -> f32 {
21114    unsafe extern "unadjusted" {
21115        #[cfg_attr(
21116            any(target_arch = "aarch64", target_arch = "arm64ec"),
21117            link_name = "llvm.aarch64.neon.frecps.f32"
21118        )]
21119        fn _vrecpss_f32(a: f32, b: f32) -> f32;
21120    }
21121    unsafe { _vrecpss_f32(a, b) }
21122}
21123#[doc = "Floating-point reciprocal step"]
21124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsh_f16)"]
21125#[inline]
21126#[cfg_attr(test, assert_instr(frecps))]
21127#[target_feature(enable = "neon,fp16")]
21128#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21129#[cfg(not(target_arch = "arm64ec"))]
21130pub fn vrecpsh_f16(a: f16, b: f16) -> f16 {
21131    unsafe extern "unadjusted" {
21132        #[cfg_attr(
21133            any(target_arch = "aarch64", target_arch = "arm64ec"),
21134            link_name = "llvm.aarch64.neon.frecps.f16"
21135        )]
21136        fn _vrecpsh_f16(a: f16, b: f16) -> f16;
21137    }
21138    unsafe { _vrecpsh_f16(a, b) }
21139}
21140#[doc = "Floating-point reciprocal exponent"]
21141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)"]
21142#[inline]
21143#[target_feature(enable = "neon")]
21144#[cfg_attr(test, assert_instr(frecpx))]
21145#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21146pub fn vrecpxd_f64(a: f64) -> f64 {
21147    unsafe extern "unadjusted" {
21148        #[cfg_attr(
21149            any(target_arch = "aarch64", target_arch = "arm64ec"),
21150            link_name = "llvm.aarch64.neon.frecpx.f64"
21151        )]
21152        fn _vrecpxd_f64(a: f64) -> f64;
21153    }
21154    unsafe { _vrecpxd_f64(a) }
21155}
21156#[doc = "Floating-point reciprocal exponent"]
21157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)"]
21158#[inline]
21159#[target_feature(enable = "neon")]
21160#[cfg_attr(test, assert_instr(frecpx))]
21161#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21162pub fn vrecpxs_f32(a: f32) -> f32 {
21163    unsafe extern "unadjusted" {
21164        #[cfg_attr(
21165            any(target_arch = "aarch64", target_arch = "arm64ec"),
21166            link_name = "llvm.aarch64.neon.frecpx.f32"
21167        )]
21168        fn _vrecpxs_f32(a: f32) -> f32;
21169    }
21170    unsafe { _vrecpxs_f32(a) }
21171}
21172#[doc = "Floating-point reciprocal exponent"]
21173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxh_f16)"]
21174#[inline]
21175#[cfg_attr(test, assert_instr(frecpx))]
21176#[target_feature(enable = "neon,fp16")]
21177#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21178#[cfg(not(target_arch = "arm64ec"))]
21179pub fn vrecpxh_f16(a: f16) -> f16 {
21180    unsafe extern "unadjusted" {
21181        #[cfg_attr(
21182            any(target_arch = "aarch64", target_arch = "arm64ec"),
21183            link_name = "llvm.aarch64.neon.frecpx.f16"
21184        )]
21185        fn _vrecpxh_f16(a: f16) -> f16;
21186    }
21187    unsafe { _vrecpxh_f16(a) }
21188}
21189#[doc = "Vector reinterpret cast operation"]
21190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
21191#[inline]
21192#[target_feature(enable = "neon")]
21193#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
21194#[cfg(not(target_arch = "arm64ec"))]
21195#[cfg_attr(test, assert_instr(nop))]
21196pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
21197    unsafe { transmute(a) }
21198}
21199#[doc = "Vector reinterpret cast operation"]
21200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
21201#[inline]
21202#[target_feature(enable = "neon")]
21203#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
21204#[cfg(not(target_arch = "arm64ec"))]
21205#[cfg_attr(test, assert_instr(nop))]
21206pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
21207    unsafe { transmute(a) }
21208}
21209#[doc = "Vector reinterpret cast operation"]
21210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
21211#[inline]
21212#[target_feature(enable = "neon")]
21213#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
21214#[cfg(not(target_arch = "arm64ec"))]
21215#[cfg_attr(test, assert_instr(nop))]
21216pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
21217    unsafe { transmute(a) }
21218}
21219#[doc = "Vector reinterpret cast operation"]
21220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
21221#[inline]
21222#[target_feature(enable = "neon")]
21223#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
21224#[cfg(not(target_arch = "arm64ec"))]
21225#[cfg_attr(test, assert_instr(nop))]
21226pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
21227    unsafe { transmute(a) }
21228}
21229#[doc = "Vector reinterpret cast operation"]
21230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"]
21231#[inline]
21232#[target_feature(enable = "neon")]
21233#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21234#[cfg_attr(test, assert_instr(nop))]
21235pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t {
21236    unsafe { transmute(a) }
21237}
21238#[doc = "Vector reinterpret cast operation"]
21239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"]
21240#[inline]
21241#[target_feature(enable = "neon")]
21242#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21243#[cfg_attr(test, assert_instr(nop))]
21244pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t {
21245    unsafe { transmute(a) }
21246}
21247#[doc = "Vector reinterpret cast operation"]
21248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"]
21249#[inline]
21250#[target_feature(enable = "neon")]
21251#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21252#[cfg_attr(test, assert_instr(nop))]
21253pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t {
21254    unsafe { transmute(a) }
21255}
21256#[doc = "Vector reinterpret cast operation"]
21257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
21258#[inline]
21259#[target_feature(enable = "neon")]
21260#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21261#[cfg_attr(test, assert_instr(nop))]
21262pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
21263    unsafe { transmute(a) }
21264}
21265#[doc = "Vector reinterpret cast operation"]
21266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
21267#[inline]
21268#[target_feature(enable = "neon")]
21269#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21270#[cfg_attr(test, assert_instr(nop))]
21271pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
21272    unsafe { transmute(a) }
21273}
21274#[doc = "Vector reinterpret cast operation"]
21275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
21276#[inline]
21277#[target_feature(enable = "neon")]
21278#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21279#[cfg_attr(test, assert_instr(nop))]
21280pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
21281    unsafe { transmute(a) }
21282}
21283#[doc = "Vector reinterpret cast operation"]
21284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"]
21285#[inline]
21286#[target_feature(enable = "neon")]
21287#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21288#[cfg_attr(test, assert_instr(nop))]
21289pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t {
21290    unsafe { transmute(a) }
21291}
21292#[doc = "Vector reinterpret cast operation"]
21293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"]
21294#[inline]
21295#[target_feature(enable = "neon")]
21296#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21297#[cfg_attr(test, assert_instr(nop))]
21298pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t {
21299    unsafe { transmute(a) }
21300}
21301#[doc = "Vector reinterpret cast operation"]
21302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
21303#[inline]
21304#[target_feature(enable = "neon")]
21305#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21306#[cfg_attr(test, assert_instr(nop))]
21307pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
21308    unsafe { transmute(a) }
21309}
21310#[doc = "Vector reinterpret cast operation"]
21311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
21312#[inline]
21313#[target_feature(enable = "neon")]
21314#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21315#[cfg_attr(test, assert_instr(nop))]
21316pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
21317    unsafe { transmute(a) }
21318}
21319#[doc = "Vector reinterpret cast operation"]
21320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"]
21321#[inline]
21322#[target_feature(enable = "neon")]
21323#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21324#[cfg_attr(test, assert_instr(nop))]
21325pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t {
21326    unsafe { transmute(a) }
21327}
21328#[doc = "Vector reinterpret cast operation"]
21329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"]
21330#[inline]
21331#[target_feature(enable = "neon")]
21332#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21333#[cfg_attr(test, assert_instr(nop))]
21334pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t {
21335    unsafe { transmute(a) }
21336}
21337#[doc = "Vector reinterpret cast operation"]
21338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
21339#[inline]
21340#[target_feature(enable = "neon")]
21341#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21342#[cfg_attr(test, assert_instr(nop))]
21343pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
21344    unsafe { transmute(a) }
21345}
21346#[doc = "Vector reinterpret cast operation"]
21347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
21348#[inline]
21349#[target_feature(enable = "neon")]
21350#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21351#[cfg_attr(test, assert_instr(nop))]
21352pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
21353    unsafe { transmute(a) }
21354}
21355#[doc = "Vector reinterpret cast operation"]
21356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"]
21357#[inline]
21358#[target_feature(enable = "neon")]
21359#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21360#[cfg_attr(test, assert_instr(nop))]
21361pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t {
21362    unsafe { transmute(a) }
21363}
21364#[doc = "Vector reinterpret cast operation"]
21365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"]
21366#[inline]
21367#[target_feature(enable = "neon")]
21368#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21369#[cfg_attr(test, assert_instr(nop))]
21370pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t {
21371    unsafe { transmute(a) }
21372}
21373#[doc = "Vector reinterpret cast operation"]
21374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"]
21375#[inline]
21376#[target_feature(enable = "neon")]
21377#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21378#[cfg_attr(test, assert_instr(nop))]
21379pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t {
21380    unsafe { transmute(a) }
21381}
21382#[doc = "Vector reinterpret cast operation"]
21383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
21384#[inline]
21385#[target_feature(enable = "neon")]
21386#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21387#[cfg_attr(test, assert_instr(nop))]
21388pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
21389    unsafe { transmute(a) }
21390}
21391#[doc = "Vector reinterpret cast operation"]
21392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
21393#[inline]
21394#[target_feature(enable = "neon")]
21395#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21396#[cfg_attr(test, assert_instr(nop))]
21397pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
21398    unsafe { transmute(a) }
21399}
21400#[doc = "Vector reinterpret cast operation"]
21401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
21402#[inline]
21403#[target_feature(enable = "neon")]
21404#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21405#[cfg_attr(test, assert_instr(nop))]
21406pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
21407    unsafe { transmute(a) }
21408}
21409#[doc = "Vector reinterpret cast operation"]
21410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
21411#[inline]
21412#[target_feature(enable = "neon")]
21413#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21414#[cfg_attr(test, assert_instr(nop))]
21415pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t {
21416    unsafe { transmute(a) }
21417}
21418#[doc = "Vector reinterpret cast operation"]
21419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"]
21420#[inline]
21421#[target_feature(enable = "neon")]
21422#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21423#[cfg_attr(test, assert_instr(nop))]
21424pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
21425    unsafe { transmute(a) }
21426}
21427#[doc = "Vector reinterpret cast operation"]
21428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
21429#[inline]
21430#[target_feature(enable = "neon")]
21431#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21432#[cfg_attr(test, assert_instr(nop))]
21433pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
21434    unsafe { transmute(a) }
21435}
21436#[doc = "Vector reinterpret cast operation"]
21437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
21438#[inline]
21439#[target_feature(enable = "neon")]
21440#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21441#[cfg_attr(test, assert_instr(nop))]
21442pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
21443    unsafe { transmute(a) }
21444}
21445#[doc = "Vector reinterpret cast operation"]
21446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"]
21447#[inline]
21448#[target_feature(enable = "neon")]
21449#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21450#[cfg_attr(test, assert_instr(nop))]
21451pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
21452    unsafe { transmute(a) }
21453}
21454#[doc = "Vector reinterpret cast operation"]
21455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"]
21456#[inline]
21457#[target_feature(enable = "neon")]
21458#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21459#[cfg_attr(test, assert_instr(nop))]
21460pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t {
21461    unsafe { transmute(a) }
21462}
21463#[doc = "Vector reinterpret cast operation"]
21464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"]
21465#[inline]
21466#[target_feature(enable = "neon")]
21467#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21468#[cfg_attr(test, assert_instr(nop))]
21469pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t {
21470    unsafe { transmute(a) }
21471}
21472#[doc = "Vector reinterpret cast operation"]
21473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"]
21474#[inline]
21475#[target_feature(enable = "neon")]
21476#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21477#[cfg_attr(test, assert_instr(nop))]
21478pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t {
21479    unsafe { transmute(a) }
21480}
21481#[doc = "Vector reinterpret cast operation"]
21482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"]
21483#[inline]
21484#[target_feature(enable = "neon")]
21485#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21486#[cfg_attr(test, assert_instr(nop))]
21487pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
21488    unsafe { transmute(a) }
21489}
21490#[doc = "Vector reinterpret cast operation"]
21491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
21492#[inline]
21493#[target_feature(enable = "neon")]
21494#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21495#[cfg_attr(test, assert_instr(nop))]
21496pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t {
21497    unsafe { transmute(a) }
21498}
21499#[doc = "Vector reinterpret cast operation"]
21500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"]
21501#[inline]
21502#[target_feature(enable = "neon")]
21503#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21504#[cfg_attr(test, assert_instr(nop))]
21505pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t {
21506    unsafe { transmute(a) }
21507}
21508#[doc = "Vector reinterpret cast operation"]
21509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"]
21510#[inline]
21511#[target_feature(enable = "neon")]
21512#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21513#[cfg_attr(test, assert_instr(nop))]
21514pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
21515    unsafe { transmute(a) }
21516}
21517#[doc = "Vector reinterpret cast operation"]
21518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
21519#[inline]
21520#[target_feature(enable = "neon")]
21521#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21522#[cfg_attr(test, assert_instr(nop))]
21523pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t {
21524    unsafe { transmute(a) }
21525}
21526#[doc = "Vector reinterpret cast operation"]
21527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"]
21528#[inline]
21529#[target_feature(enable = "neon")]
21530#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21531#[cfg_attr(test, assert_instr(nop))]
21532pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
21533    unsafe { transmute(a) }
21534}
21535#[doc = "Vector reinterpret cast operation"]
21536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
21537#[inline]
21538#[target_feature(enable = "neon")]
21539#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21540#[cfg_attr(test, assert_instr(nop))]
21541pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
21542    unsafe { transmute(a) }
21543}
21544#[doc = "Vector reinterpret cast operation"]
21545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
21546#[inline]
21547#[target_feature(enable = "neon")]
21548#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21549#[cfg_attr(test, assert_instr(nop))]
21550pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
21551    unsafe { transmute(a) }
21552}
21553#[doc = "Vector reinterpret cast operation"]
21554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"]
21555#[inline]
21556#[target_feature(enable = "neon")]
21557#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21558#[cfg_attr(test, assert_instr(nop))]
21559pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
21560    unsafe { transmute(a) }
21561}
21562#[doc = "Vector reinterpret cast operation"]
21563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"]
21564#[inline]
21565#[target_feature(enable = "neon")]
21566#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21567#[cfg_attr(test, assert_instr(nop))]
21568pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
21569    unsafe { transmute(a) }
21570}
21571#[doc = "Vector reinterpret cast operation"]
21572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"]
21573#[inline]
21574#[target_feature(enable = "neon")]
21575#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21576#[cfg_attr(test, assert_instr(nop))]
21577pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
21578    unsafe { transmute(a) }
21579}
21580#[doc = "Vector reinterpret cast operation"]
21581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
21582#[inline]
21583#[target_feature(enable = "neon")]
21584#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21585#[cfg_attr(test, assert_instr(nop))]
21586pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
21587    unsafe { transmute(a) }
21588}
21589#[doc = "Vector reinterpret cast operation"]
21590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"]
21591#[inline]
21592#[target_feature(enable = "neon")]
21593#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21594#[cfg_attr(test, assert_instr(nop))]
21595pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
21596    unsafe { transmute(a) }
21597}
21598#[doc = "Vector reinterpret cast operation"]
21599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"]
21600#[inline]
21601#[target_feature(enable = "neon")]
21602#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21603#[cfg_attr(test, assert_instr(nop))]
21604pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
21605    unsafe { transmute(a) }
21606}
21607#[doc = "Vector reinterpret cast operation"]
21608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
21609#[inline]
21610#[target_feature(enable = "neon")]
21611#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21612#[cfg_attr(test, assert_instr(nop))]
21613pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
21614    unsafe { transmute(a) }
21615}
21616#[doc = "Vector reinterpret cast operation"]
21617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"]
21618#[inline]
21619#[target_feature(enable = "neon")]
21620#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21621#[cfg_attr(test, assert_instr(nop))]
21622pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
21623    unsafe { transmute(a) }
21624}
21625#[doc = "Vector reinterpret cast operation"]
21626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
21627#[inline]
21628#[target_feature(enable = "neon")]
21629#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21630#[cfg_attr(test, assert_instr(nop))]
21631pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
21632    unsafe { transmute(a) }
21633}
21634#[doc = "Vector reinterpret cast operation"]
21635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
21636#[inline]
21637#[target_feature(enable = "neon")]
21638#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21639#[cfg_attr(test, assert_instr(nop))]
21640pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
21641    unsafe { transmute(a) }
21642}
21643#[doc = "Vector reinterpret cast operation"]
21644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"]
21645#[inline]
21646#[target_feature(enable = "neon")]
21647#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21648#[cfg_attr(test, assert_instr(nop))]
21649pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
21650    unsafe { transmute(a) }
21651}
21652#[doc = "Vector reinterpret cast operation"]
21653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
21654#[inline]
21655#[target_feature(enable = "neon")]
21656#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21657#[cfg_attr(test, assert_instr(nop))]
21658pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
21659    unsafe { transmute(a) }
21660}
21661#[doc = "Vector reinterpret cast operation"]
21662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"]
21663#[inline]
21664#[target_feature(enable = "neon")]
21665#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21666#[cfg_attr(test, assert_instr(nop))]
21667pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
21668    unsafe { transmute(a) }
21669}
21670#[doc = "Vector reinterpret cast operation"]
21671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
21672#[inline]
21673#[target_feature(enable = "neon")]
21674#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21675#[cfg_attr(test, assert_instr(nop))]
21676pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
21677    unsafe { transmute(a) }
21678}
21679#[doc = "Vector reinterpret cast operation"]
21680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
21681#[inline]
21682#[target_feature(enable = "neon")]
21683#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21684#[cfg_attr(test, assert_instr(nop))]
21685pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
21686    unsafe { transmute(a) }
21687}
21688#[doc = "Vector reinterpret cast operation"]
21689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
21690#[inline]
21691#[target_feature(enable = "neon")]
21692#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21693#[cfg_attr(test, assert_instr(nop))]
21694pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
21695    unsafe { transmute(a) }
21696}
21697#[doc = "Vector reinterpret cast operation"]
21698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"]
21699#[inline]
21700#[target_feature(enable = "neon")]
21701#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21702#[cfg_attr(test, assert_instr(nop))]
21703pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
21704    unsafe { transmute(a) }
21705}
21706#[doc = "Vector reinterpret cast operation"]
21707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
21708#[inline]
21709#[target_feature(enable = "neon")]
21710#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21711#[cfg_attr(test, assert_instr(nop))]
21712pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
21713    unsafe { transmute(a) }
21714}
21715#[doc = "Vector reinterpret cast operation"]
21716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"]
21717#[inline]
21718#[target_feature(enable = "neon")]
21719#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21720#[cfg_attr(test, assert_instr(nop))]
21721pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
21722    unsafe { transmute(a) }
21723}
21724#[doc = "Vector reinterpret cast operation"]
21725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
21726#[inline]
21727#[target_feature(enable = "neon")]
21728#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21729#[cfg_attr(test, assert_instr(nop))]
21730pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
21731    unsafe { transmute(a) }
21732}
21733#[doc = "Vector reinterpret cast operation"]
21734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
21735#[inline]
21736#[target_feature(enable = "neon")]
21737#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21738#[cfg_attr(test, assert_instr(nop))]
21739pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
21740    unsafe { transmute(a) }
21741}
21742#[doc = "Vector reinterpret cast operation"]
21743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
21744#[inline]
21745#[target_feature(enable = "neon")]
21746#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21747#[cfg_attr(test, assert_instr(nop))]
21748pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
21749    unsafe { transmute(a) }
21750}
21751#[doc = "Vector reinterpret cast operation"]
21752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"]
21753#[inline]
21754#[target_feature(enable = "neon")]
21755#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21756#[cfg_attr(test, assert_instr(nop))]
21757pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
21758    unsafe { transmute(a) }
21759}
21760#[doc = "Vector reinterpret cast operation"]
21761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
21762#[inline]
21763#[target_feature(enable = "neon")]
21764#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21765#[cfg_attr(test, assert_instr(nop))]
21766pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
21767    unsafe { transmute(a) }
21768}
21769#[doc = "Vector reinterpret cast operation"]
21770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"]
21771#[inline]
21772#[target_feature(enable = "neon")]
21773#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21774#[cfg_attr(test, assert_instr(nop))]
21775pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
21776    unsafe { transmute(a) }
21777}
21778#[doc = "Vector reinterpret cast operation"]
21779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
21780#[inline]
21781#[target_feature(enable = "neon")]
21782#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21783#[cfg_attr(test, assert_instr(nop))]
21784pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
21785    unsafe { transmute(a) }
21786}
21787#[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
21788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"]
21789#[inline]
21790#[target_feature(enable = "neon,frintts")]
21791#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21792#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
21793pub fn vrnd32x_f32(a: float32x2_t) -> float32x2_t {
21794    unsafe extern "unadjusted" {
21795        #[cfg_attr(
21796            any(target_arch = "aarch64", target_arch = "arm64ec"),
21797            link_name = "llvm.aarch64.neon.frint32x.v2f32"
21798        )]
21799        fn _vrnd32x_f32(a: float32x2_t) -> float32x2_t;
21800    }
21801    unsafe { _vrnd32x_f32(a) }
21802}
21803#[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
21804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32)"]
21805#[inline]
21806#[target_feature(enable = "neon,frintts")]
21807#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21808#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
21809pub fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t {
21810    unsafe extern "unadjusted" {
21811        #[cfg_attr(
21812            any(target_arch = "aarch64", target_arch = "arm64ec"),
21813            link_name = "llvm.aarch64.neon.frint32x.v4f32"
21814        )]
21815        fn _vrnd32xq_f32(a: float32x4_t) -> float32x4_t;
21816    }
21817    unsafe { _vrnd32xq_f32(a) }
21818}
21819#[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
21820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64)"]
21821#[inline]
21822#[target_feature(enable = "neon,frintts")]
21823#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21824#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
21825pub fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t {
21826    unsafe extern "unadjusted" {
21827        #[cfg_attr(
21828            any(target_arch = "aarch64", target_arch = "arm64ec"),
21829            link_name = "llvm.aarch64.neon.frint32x.v2f64"
21830        )]
21831        fn _vrnd32xq_f64(a: float64x2_t) -> float64x2_t;
21832    }
21833    unsafe { _vrnd32xq_f64(a) }
21834}
21835#[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
21836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64)"]
21837#[inline]
21838#[target_feature(enable = "neon,frintts")]
21839#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21840#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
21841pub fn vrnd32x_f64(a: float64x1_t) -> float64x1_t {
21842    unsafe extern "unadjusted" {
21843        #[cfg_attr(
21844            any(target_arch = "aarch64", target_arch = "arm64ec"),
21845            link_name = "llvm.aarch64.frint32x.f64"
21846        )]
21847        fn _vrnd32x_f64(a: f64) -> f64;
21848    }
21849    unsafe { transmute(_vrnd32x_f64(vget_lane_f64::<0>(a))) }
21850}
21851#[doc = "Floating-point round to 32-bit integer toward zero"]
21852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"]
21853#[inline]
21854#[target_feature(enable = "neon,frintts")]
21855#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21856#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
21857pub fn vrnd32z_f32(a: float32x2_t) -> float32x2_t {
21858    unsafe extern "unadjusted" {
21859        #[cfg_attr(
21860            any(target_arch = "aarch64", target_arch = "arm64ec"),
21861            link_name = "llvm.aarch64.neon.frint32z.v2f32"
21862        )]
21863        fn _vrnd32z_f32(a: float32x2_t) -> float32x2_t;
21864    }
21865    unsafe { _vrnd32z_f32(a) }
21866}
21867#[doc = "Floating-point round to 32-bit integer toward zero"]
21868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32)"]
21869#[inline]
21870#[target_feature(enable = "neon,frintts")]
21871#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21872#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
21873pub fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t {
21874    unsafe extern "unadjusted" {
21875        #[cfg_attr(
21876            any(target_arch = "aarch64", target_arch = "arm64ec"),
21877            link_name = "llvm.aarch64.neon.frint32z.v4f32"
21878        )]
21879        fn _vrnd32zq_f32(a: float32x4_t) -> float32x4_t;
21880    }
21881    unsafe { _vrnd32zq_f32(a) }
21882}
21883#[doc = "Floating-point round to 32-bit integer toward zero"]
21884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64)"]
21885#[inline]
21886#[target_feature(enable = "neon,frintts")]
21887#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21888#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
21889pub fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t {
21890    unsafe extern "unadjusted" {
21891        #[cfg_attr(
21892            any(target_arch = "aarch64", target_arch = "arm64ec"),
21893            link_name = "llvm.aarch64.neon.frint32z.v2f64"
21894        )]
21895        fn _vrnd32zq_f64(a: float64x2_t) -> float64x2_t;
21896    }
21897    unsafe { _vrnd32zq_f64(a) }
21898}
21899#[doc = "Floating-point round to 32-bit integer toward zero"]
21900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64)"]
21901#[inline]
21902#[target_feature(enable = "neon,frintts")]
21903#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21904#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
21905pub fn vrnd32z_f64(a: float64x1_t) -> float64x1_t {
21906    unsafe extern "unadjusted" {
21907        #[cfg_attr(
21908            any(target_arch = "aarch64", target_arch = "arm64ec"),
21909            link_name = "llvm.aarch64.frint32z.f64"
21910        )]
21911        fn _vrnd32z_f64(a: f64) -> f64;
21912    }
21913    unsafe { transmute(_vrnd32z_f64(vget_lane_f64::<0>(a))) }
21914}
21915#[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
21916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"]
21917#[inline]
21918#[target_feature(enable = "neon,frintts")]
21919#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21920#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
21921pub fn vrnd64x_f32(a: float32x2_t) -> float32x2_t {
21922    unsafe extern "unadjusted" {
21923        #[cfg_attr(
21924            any(target_arch = "aarch64", target_arch = "arm64ec"),
21925            link_name = "llvm.aarch64.neon.frint64x.v2f32"
21926        )]
21927        fn _vrnd64x_f32(a: float32x2_t) -> float32x2_t;
21928    }
21929    unsafe { _vrnd64x_f32(a) }
21930}
21931#[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
21932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32)"]
21933#[inline]
21934#[target_feature(enable = "neon,frintts")]
21935#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21936#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
21937pub fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t {
21938    unsafe extern "unadjusted" {
21939        #[cfg_attr(
21940            any(target_arch = "aarch64", target_arch = "arm64ec"),
21941            link_name = "llvm.aarch64.neon.frint64x.v4f32"
21942        )]
21943        fn _vrnd64xq_f32(a: float32x4_t) -> float32x4_t;
21944    }
21945    unsafe { _vrnd64xq_f32(a) }
21946}
21947#[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
21948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64)"]
21949#[inline]
21950#[target_feature(enable = "neon,frintts")]
21951#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21952#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
21953pub fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t {
21954    unsafe extern "unadjusted" {
21955        #[cfg_attr(
21956            any(target_arch = "aarch64", target_arch = "arm64ec"),
21957            link_name = "llvm.aarch64.neon.frint64x.v2f64"
21958        )]
21959        fn _vrnd64xq_f64(a: float64x2_t) -> float64x2_t;
21960    }
21961    unsafe { _vrnd64xq_f64(a) }
21962}
21963#[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
21964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64)"]
21965#[inline]
21966#[target_feature(enable = "neon,frintts")]
21967#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21968#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
21969pub fn vrnd64x_f64(a: float64x1_t) -> float64x1_t {
21970    unsafe extern "unadjusted" {
21971        #[cfg_attr(
21972            any(target_arch = "aarch64", target_arch = "arm64ec"),
21973            link_name = "llvm.aarch64.frint64x.f64"
21974        )]
21975        fn _vrnd64x_f64(a: f64) -> f64;
21976    }
21977    unsafe { transmute(_vrnd64x_f64(vget_lane_f64::<0>(a))) }
21978}
21979#[doc = "Floating-point round to 64-bit integer toward zero"]
21980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"]
21981#[inline]
21982#[target_feature(enable = "neon,frintts")]
21983#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
21984#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
21985pub fn vrnd64z_f32(a: float32x2_t) -> float32x2_t {
21986    unsafe extern "unadjusted" {
21987        #[cfg_attr(
21988            any(target_arch = "aarch64", target_arch = "arm64ec"),
21989            link_name = "llvm.aarch64.neon.frint64z.v2f32"
21990        )]
21991        fn _vrnd64z_f32(a: float32x2_t) -> float32x2_t;
21992    }
21993    unsafe { _vrnd64z_f32(a) }
21994}
21995#[doc = "Floating-point round to 64-bit integer toward zero"]
21996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32)"]
21997#[inline]
21998#[target_feature(enable = "neon,frintts")]
21999#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
22000#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
22001pub fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t {
22002    unsafe extern "unadjusted" {
22003        #[cfg_attr(
22004            any(target_arch = "aarch64", target_arch = "arm64ec"),
22005            link_name = "llvm.aarch64.neon.frint64z.v4f32"
22006        )]
22007        fn _vrnd64zq_f32(a: float32x4_t) -> float32x4_t;
22008    }
22009    unsafe { _vrnd64zq_f32(a) }
22010}
22011#[doc = "Floating-point round to 64-bit integer toward zero"]
22012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64)"]
22013#[inline]
22014#[target_feature(enable = "neon,frintts")]
22015#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
22016#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
22017pub fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t {
22018    unsafe extern "unadjusted" {
22019        #[cfg_attr(
22020            any(target_arch = "aarch64", target_arch = "arm64ec"),
22021            link_name = "llvm.aarch64.neon.frint64z.v2f64"
22022        )]
22023        fn _vrnd64zq_f64(a: float64x2_t) -> float64x2_t;
22024    }
22025    unsafe { _vrnd64zq_f64(a) }
22026}
22027#[doc = "Floating-point round to 64-bit integer toward zero"]
22028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64)"]
22029#[inline]
22030#[target_feature(enable = "neon,frintts")]
22031#[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
22032#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
22033pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t {
22034    unsafe extern "unadjusted" {
22035        #[cfg_attr(
22036            any(target_arch = "aarch64", target_arch = "arm64ec"),
22037            link_name = "llvm.aarch64.frint64z.f64"
22038        )]
22039        fn _vrnd64z_f64(a: f64) -> f64;
22040    }
22041    unsafe { transmute(_vrnd64z_f64(vget_lane_f64::<0>(a))) }
22042}
22043#[doc = "Floating-point round to integral, toward zero"]
22044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"]
22045#[inline]
22046#[target_feature(enable = "neon,fp16")]
22047#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22048#[cfg(not(target_arch = "arm64ec"))]
22049#[cfg_attr(test, assert_instr(frintz))]
22050pub fn vrnd_f16(a: float16x4_t) -> float16x4_t {
22051    unsafe { simd_trunc(a) }
22052}
22053#[doc = "Floating-point round to integral, toward zero"]
22054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"]
22055#[inline]
22056#[target_feature(enable = "neon,fp16")]
22057#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22058#[cfg(not(target_arch = "arm64ec"))]
22059#[cfg_attr(test, assert_instr(frintz))]
22060pub fn vrndq_f16(a: float16x8_t) -> float16x8_t {
22061    unsafe { simd_trunc(a) }
22062}
22063#[doc = "Floating-point round to integral, toward zero"]
22064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)"]
22065#[inline]
22066#[target_feature(enable = "neon")]
22067#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22068#[cfg_attr(test, assert_instr(frintz))]
22069pub fn vrnd_f32(a: float32x2_t) -> float32x2_t {
22070    unsafe { simd_trunc(a) }
22071}
22072#[doc = "Floating-point round to integral, toward zero"]
22073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)"]
22074#[inline]
22075#[target_feature(enable = "neon")]
22076#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22077#[cfg_attr(test, assert_instr(frintz))]
22078pub fn vrndq_f32(a: float32x4_t) -> float32x4_t {
22079    unsafe { simd_trunc(a) }
22080}
22081#[doc = "Floating-point round to integral, toward zero"]
22082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)"]
22083#[inline]
22084#[target_feature(enable = "neon")]
22085#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22086#[cfg_attr(test, assert_instr(frintz))]
22087pub fn vrnd_f64(a: float64x1_t) -> float64x1_t {
22088    unsafe { simd_trunc(a) }
22089}
22090#[doc = "Floating-point round to integral, toward zero"]
22091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)"]
22092#[inline]
22093#[target_feature(enable = "neon")]
22094#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22095#[cfg_attr(test, assert_instr(frintz))]
22096pub fn vrndq_f64(a: float64x2_t) -> float64x2_t {
22097    unsafe { simd_trunc(a) }
22098}
22099#[doc = "Floating-point round to integral, to nearest with ties to away"]
22100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"]
22101#[inline]
22102#[target_feature(enable = "neon,fp16")]
22103#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22104#[cfg(not(target_arch = "arm64ec"))]
22105#[cfg_attr(test, assert_instr(frinta))]
22106pub fn vrnda_f16(a: float16x4_t) -> float16x4_t {
22107    unsafe { simd_round(a) }
22108}
22109#[doc = "Floating-point round to integral, to nearest with ties to away"]
22110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"]
22111#[inline]
22112#[target_feature(enable = "neon,fp16")]
22113#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22114#[cfg(not(target_arch = "arm64ec"))]
22115#[cfg_attr(test, assert_instr(frinta))]
22116pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t {
22117    unsafe { simd_round(a) }
22118}
22119#[doc = "Floating-point round to integral, to nearest with ties to away"]
22120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)"]
22121#[inline]
22122#[target_feature(enable = "neon")]
22123#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22124#[cfg_attr(test, assert_instr(frinta))]
22125pub fn vrnda_f32(a: float32x2_t) -> float32x2_t {
22126    unsafe { simd_round(a) }
22127}
22128#[doc = "Floating-point round to integral, to nearest with ties to away"]
22129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)"]
22130#[inline]
22131#[target_feature(enable = "neon")]
22132#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22133#[cfg_attr(test, assert_instr(frinta))]
22134pub fn vrndaq_f32(a: float32x4_t) -> float32x4_t {
22135    unsafe { simd_round(a) }
22136}
22137#[doc = "Floating-point round to integral, to nearest with ties to away"]
22138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)"]
22139#[inline]
22140#[target_feature(enable = "neon")]
22141#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22142#[cfg_attr(test, assert_instr(frinta))]
22143pub fn vrnda_f64(a: float64x1_t) -> float64x1_t {
22144    unsafe { simd_round(a) }
22145}
22146#[doc = "Floating-point round to integral, to nearest with ties to away"]
22147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)"]
22148#[inline]
22149#[target_feature(enable = "neon")]
22150#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22151#[cfg_attr(test, assert_instr(frinta))]
22152pub fn vrndaq_f64(a: float64x2_t) -> float64x2_t {
22153    unsafe { simd_round(a) }
22154}
22155#[doc = "Floating-point round to integral, to nearest with ties to away"]
22156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndah_f16)"]
22157#[inline]
22158#[target_feature(enable = "neon,fp16")]
22159#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22160#[cfg(not(target_arch = "arm64ec"))]
22161#[cfg_attr(test, assert_instr(frinta))]
22162pub fn vrndah_f16(a: f16) -> f16 {
22163    roundf16(a)
22164}
22165#[doc = "Floating-point round to integral, to nearest with ties to away"]
22166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndh_f16)"]
22167#[inline]
22168#[target_feature(enable = "neon,fp16")]
22169#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22170#[cfg(not(target_arch = "arm64ec"))]
22171#[cfg_attr(test, assert_instr(frintz))]
22172pub fn vrndh_f16(a: f16) -> f16 {
22173    truncf16(a)
22174}
22175#[doc = "Floating-point round to integral, using current rounding mode"]
22176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"]
22177#[inline]
22178#[target_feature(enable = "neon,fp16")]
22179#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22180#[cfg(not(target_arch = "arm64ec"))]
22181#[cfg_attr(test, assert_instr(frinti))]
22182pub fn vrndi_f16(a: float16x4_t) -> float16x4_t {
22183    unsafe extern "unadjusted" {
22184        #[cfg_attr(
22185            any(target_arch = "aarch64", target_arch = "arm64ec"),
22186            link_name = "llvm.nearbyint.v4f16"
22187        )]
22188        fn _vrndi_f16(a: float16x4_t) -> float16x4_t;
22189    }
22190    unsafe { _vrndi_f16(a) }
22191}
22192#[doc = "Floating-point round to integral, using current rounding mode"]
22193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"]
22194#[inline]
22195#[target_feature(enable = "neon,fp16")]
22196#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22197#[cfg(not(target_arch = "arm64ec"))]
22198#[cfg_attr(test, assert_instr(frinti))]
22199pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t {
22200    unsafe extern "unadjusted" {
22201        #[cfg_attr(
22202            any(target_arch = "aarch64", target_arch = "arm64ec"),
22203            link_name = "llvm.nearbyint.v8f16"
22204        )]
22205        fn _vrndiq_f16(a: float16x8_t) -> float16x8_t;
22206    }
22207    unsafe { _vrndiq_f16(a) }
22208}
22209#[doc = "Floating-point round to integral, using current rounding mode"]
22210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32)"]
22211#[inline]
22212#[target_feature(enable = "neon")]
22213#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22214#[cfg_attr(test, assert_instr(frinti))]
22215pub fn vrndi_f32(a: float32x2_t) -> float32x2_t {
22216    unsafe extern "unadjusted" {
22217        #[cfg_attr(
22218            any(target_arch = "aarch64", target_arch = "arm64ec"),
22219            link_name = "llvm.nearbyint.v2f32"
22220        )]
22221        fn _vrndi_f32(a: float32x2_t) -> float32x2_t;
22222    }
22223    unsafe { _vrndi_f32(a) }
22224}
22225#[doc = "Floating-point round to integral, using current rounding mode"]
22226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32)"]
22227#[inline]
22228#[target_feature(enable = "neon")]
22229#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22230#[cfg_attr(test, assert_instr(frinti))]
22231pub fn vrndiq_f32(a: float32x4_t) -> float32x4_t {
22232    unsafe extern "unadjusted" {
22233        #[cfg_attr(
22234            any(target_arch = "aarch64", target_arch = "arm64ec"),
22235            link_name = "llvm.nearbyint.v4f32"
22236        )]
22237        fn _vrndiq_f32(a: float32x4_t) -> float32x4_t;
22238    }
22239    unsafe { _vrndiq_f32(a) }
22240}
22241#[doc = "Floating-point round to integral, using current rounding mode"]
22242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64)"]
22243#[inline]
22244#[target_feature(enable = "neon")]
22245#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22246#[cfg_attr(test, assert_instr(frinti))]
22247pub fn vrndi_f64(a: float64x1_t) -> float64x1_t {
22248    unsafe extern "unadjusted" {
22249        #[cfg_attr(
22250            any(target_arch = "aarch64", target_arch = "arm64ec"),
22251            link_name = "llvm.nearbyint.v1f64"
22252        )]
22253        fn _vrndi_f64(a: float64x1_t) -> float64x1_t;
22254    }
22255    unsafe { _vrndi_f64(a) }
22256}
22257#[doc = "Floating-point round to integral, using current rounding mode"]
22258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64)"]
22259#[inline]
22260#[target_feature(enable = "neon")]
22261#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22262#[cfg_attr(test, assert_instr(frinti))]
22263pub fn vrndiq_f64(a: float64x2_t) -> float64x2_t {
22264    unsafe extern "unadjusted" {
22265        #[cfg_attr(
22266            any(target_arch = "aarch64", target_arch = "arm64ec"),
22267            link_name = "llvm.nearbyint.v2f64"
22268        )]
22269        fn _vrndiq_f64(a: float64x2_t) -> float64x2_t;
22270    }
22271    unsafe { _vrndiq_f64(a) }
22272}
22273#[doc = "Floating-point round to integral, using current rounding mode"]
22274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndih_f16)"]
22275#[inline]
22276#[target_feature(enable = "neon,fp16")]
22277#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22278#[cfg(not(target_arch = "arm64ec"))]
22279#[cfg_attr(test, assert_instr(frinti))]
22280pub fn vrndih_f16(a: f16) -> f16 {
22281    unsafe extern "unadjusted" {
22282        #[cfg_attr(
22283            any(target_arch = "aarch64", target_arch = "arm64ec"),
22284            link_name = "llvm.nearbyint.f16"
22285        )]
22286        fn _vrndih_f16(a: f16) -> f16;
22287    }
22288    unsafe { _vrndih_f16(a) }
22289}
22290#[doc = "Floating-point round to integral, toward minus infinity"]
22291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"]
22292#[inline]
22293#[target_feature(enable = "neon,fp16")]
22294#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22295#[cfg(not(target_arch = "arm64ec"))]
22296#[cfg_attr(test, assert_instr(frintm))]
22297pub fn vrndm_f16(a: float16x4_t) -> float16x4_t {
22298    unsafe { simd_floor(a) }
22299}
22300#[doc = "Floating-point round to integral, toward minus infinity"]
22301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"]
22302#[inline]
22303#[target_feature(enable = "neon,fp16")]
22304#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22305#[cfg(not(target_arch = "arm64ec"))]
22306#[cfg_attr(test, assert_instr(frintm))]
22307pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t {
22308    unsafe { simd_floor(a) }
22309}
22310#[doc = "Floating-point round to integral, toward minus infinity"]
22311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)"]
22312#[inline]
22313#[target_feature(enable = "neon")]
22314#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22315#[cfg_attr(test, assert_instr(frintm))]
22316pub fn vrndm_f32(a: float32x2_t) -> float32x2_t {
22317    unsafe { simd_floor(a) }
22318}
22319#[doc = "Floating-point round to integral, toward minus infinity"]
22320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)"]
22321#[inline]
22322#[target_feature(enable = "neon")]
22323#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22324#[cfg_attr(test, assert_instr(frintm))]
22325pub fn vrndmq_f32(a: float32x4_t) -> float32x4_t {
22326    unsafe { simd_floor(a) }
22327}
22328#[doc = "Floating-point round to integral, toward minus infinity"]
22329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)"]
22330#[inline]
22331#[target_feature(enable = "neon")]
22332#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22333#[cfg_attr(test, assert_instr(frintm))]
22334pub fn vrndm_f64(a: float64x1_t) -> float64x1_t {
22335    unsafe { simd_floor(a) }
22336}
22337#[doc = "Floating-point round to integral, toward minus infinity"]
22338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)"]
22339#[inline]
22340#[target_feature(enable = "neon")]
22341#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22342#[cfg_attr(test, assert_instr(frintm))]
22343pub fn vrndmq_f64(a: float64x2_t) -> float64x2_t {
22344    unsafe { simd_floor(a) }
22345}
22346#[doc = "Floating-point round to integral, toward minus infinity"]
22347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmh_f16)"]
22348#[inline]
22349#[target_feature(enable = "neon,fp16")]
22350#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22351#[cfg(not(target_arch = "arm64ec"))]
22352#[cfg_attr(test, assert_instr(frintm))]
22353pub fn vrndmh_f16(a: f16) -> f16 {
22354    floorf16(a)
22355}
22356#[doc = "Floating-point round to integral, to nearest with ties to even"]
22357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"]
22358#[inline]
22359#[target_feature(enable = "neon")]
22360#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22361#[cfg_attr(test, assert_instr(frintn))]
22362pub fn vrndn_f64(a: float64x1_t) -> float64x1_t {
22363    unsafe extern "unadjusted" {
22364        #[cfg_attr(
22365            any(target_arch = "aarch64", target_arch = "arm64ec"),
22366            link_name = "llvm.roundeven.v1f64"
22367        )]
22368        fn _vrndn_f64(a: float64x1_t) -> float64x1_t;
22369    }
22370    unsafe { _vrndn_f64(a) }
22371}
22372#[doc = "Floating-point round to integral, to nearest with ties to even"]
22373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)"]
22374#[inline]
22375#[target_feature(enable = "neon")]
22376#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22377#[cfg_attr(test, assert_instr(frintn))]
22378pub fn vrndnq_f64(a: float64x2_t) -> float64x2_t {
22379    unsafe extern "unadjusted" {
22380        #[cfg_attr(
22381            any(target_arch = "aarch64", target_arch = "arm64ec"),
22382            link_name = "llvm.roundeven.v2f64"
22383        )]
22384        fn _vrndnq_f64(a: float64x2_t) -> float64x2_t;
22385    }
22386    unsafe { _vrndnq_f64(a) }
22387}
22388#[doc = "Floating-point round to integral, toward minus infinity"]
22389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnh_f16)"]
22390#[inline]
22391#[target_feature(enable = "neon,fp16")]
22392#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22393#[cfg(not(target_arch = "arm64ec"))]
22394#[cfg_attr(test, assert_instr(frintn))]
22395pub fn vrndnh_f16(a: f16) -> f16 {
22396    unsafe extern "unadjusted" {
22397        #[cfg_attr(
22398            any(target_arch = "aarch64", target_arch = "arm64ec"),
22399            link_name = "llvm.roundeven.f16"
22400        )]
22401        fn _vrndnh_f16(a: f16) -> f16;
22402    }
22403    unsafe { _vrndnh_f16(a) }
22404}
22405#[doc = "Floating-point round to integral, to nearest with ties to even"]
22406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)"]
22407#[inline]
22408#[target_feature(enable = "neon")]
22409#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22410#[cfg_attr(test, assert_instr(frintn))]
22411pub fn vrndns_f32(a: f32) -> f32 {
22412    unsafe extern "unadjusted" {
22413        #[cfg_attr(
22414            any(target_arch = "aarch64", target_arch = "arm64ec"),
22415            link_name = "llvm.roundeven.f32"
22416        )]
22417        fn _vrndns_f32(a: f32) -> f32;
22418    }
22419    unsafe { _vrndns_f32(a) }
22420}
22421#[doc = "Floating-point round to integral, toward plus infinity"]
22422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"]
22423#[inline]
22424#[target_feature(enable = "neon,fp16")]
22425#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22426#[cfg(not(target_arch = "arm64ec"))]
22427#[cfg_attr(test, assert_instr(frintp))]
22428pub fn vrndp_f16(a: float16x4_t) -> float16x4_t {
22429    unsafe { simd_ceil(a) }
22430}
22431#[doc = "Floating-point round to integral, toward plus infinity"]
22432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"]
22433#[inline]
22434#[target_feature(enable = "neon,fp16")]
22435#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22436#[cfg(not(target_arch = "arm64ec"))]
22437#[cfg_attr(test, assert_instr(frintp))]
22438pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t {
22439    unsafe { simd_ceil(a) }
22440}
22441#[doc = "Floating-point round to integral, toward plus infinity"]
22442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)"]
22443#[inline]
22444#[target_feature(enable = "neon")]
22445#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22446#[cfg_attr(test, assert_instr(frintp))]
22447pub fn vrndp_f32(a: float32x2_t) -> float32x2_t {
22448    unsafe { simd_ceil(a) }
22449}
22450#[doc = "Floating-point round to integral, toward plus infinity"]
22451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)"]
22452#[inline]
22453#[target_feature(enable = "neon")]
22454#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22455#[cfg_attr(test, assert_instr(frintp))]
22456pub fn vrndpq_f32(a: float32x4_t) -> float32x4_t {
22457    unsafe { simd_ceil(a) }
22458}
22459#[doc = "Floating-point round to integral, toward plus infinity"]
22460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)"]
22461#[inline]
22462#[target_feature(enable = "neon")]
22463#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22464#[cfg_attr(test, assert_instr(frintp))]
22465pub fn vrndp_f64(a: float64x1_t) -> float64x1_t {
22466    unsafe { simd_ceil(a) }
22467}
22468#[doc = "Floating-point round to integral, toward plus infinity"]
22469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)"]
22470#[inline]
22471#[target_feature(enable = "neon")]
22472#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22473#[cfg_attr(test, assert_instr(frintp))]
22474pub fn vrndpq_f64(a: float64x2_t) -> float64x2_t {
22475    unsafe { simd_ceil(a) }
22476}
22477#[doc = "Floating-point round to integral, toward plus infinity"]
22478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndph_f16)"]
22479#[inline]
22480#[target_feature(enable = "neon,fp16")]
22481#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22482#[cfg(not(target_arch = "arm64ec"))]
22483#[cfg_attr(test, assert_instr(frintp))]
22484pub fn vrndph_f16(a: f16) -> f16 {
22485    ceilf16(a)
22486}
22487#[doc = "Floating-point round to integral exact, using current rounding mode"]
22488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"]
22489#[inline]
22490#[target_feature(enable = "neon,fp16")]
22491#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22492#[cfg(not(target_arch = "arm64ec"))]
22493#[cfg_attr(test, assert_instr(frintx))]
22494pub fn vrndx_f16(a: float16x4_t) -> float16x4_t {
22495    unsafe { simd_round_ties_even(a) }
22496}
22497#[doc = "Floating-point round to integral exact, using current rounding mode"]
22498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"]
22499#[inline]
22500#[target_feature(enable = "neon,fp16")]
22501#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
22502#[cfg(not(target_arch = "arm64ec"))]
22503#[cfg_attr(test, assert_instr(frintx))]
22504pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t {
22505    unsafe { simd_round_ties_even(a) }
22506}
22507#[doc = "Floating-point round to integral exact, using current rounding mode"]
22508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32)"]
22509#[inline]
22510#[target_feature(enable = "neon")]
22511#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22512#[cfg_attr(test, assert_instr(frintx))]
22513pub fn vrndx_f32(a: float32x2_t) -> float32x2_t {
22514    unsafe { simd_round_ties_even(a) }
22515}
22516#[doc = "Floating-point round to integral exact, using current rounding mode"]
22517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32)"]
22518#[inline]
22519#[target_feature(enable = "neon")]
22520#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22521#[cfg_attr(test, assert_instr(frintx))]
22522pub fn vrndxq_f32(a: float32x4_t) -> float32x4_t {
22523    unsafe { simd_round_ties_even(a) }
22524}
22525#[doc = "Floating-point round to integral exact, using current rounding mode"]
22526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64)"]
22527#[inline]
22528#[target_feature(enable = "neon")]
22529#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22530#[cfg_attr(test, assert_instr(frintx))]
22531pub fn vrndx_f64(a: float64x1_t) -> float64x1_t {
22532    unsafe { simd_round_ties_even(a) }
22533}
22534#[doc = "Floating-point round to integral exact, using current rounding mode"]
22535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64)"]
22536#[inline]
22537#[target_feature(enable = "neon")]
22538#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22539#[cfg_attr(test, assert_instr(frintx))]
22540pub fn vrndxq_f64(a: float64x2_t) -> float64x2_t {
22541    unsafe { simd_round_ties_even(a) }
22542}
22543#[doc = "Floating-point round to integral, using current rounding mode"]
22544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxh_f16)"]
22545#[inline]
22546#[target_feature(enable = "neon,fp16")]
22547#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22548#[cfg(not(target_arch = "arm64ec"))]
22549#[cfg_attr(test, assert_instr(frintx))]
22550pub fn vrndxh_f16(a: f16) -> f16 {
22551    round_ties_even_f16(a)
22552}
22553#[doc = "Signed rounding shift left"]
22554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64)"]
22555#[inline]
22556#[target_feature(enable = "neon")]
22557#[cfg_attr(test, assert_instr(srshl))]
22558#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22559pub fn vrshld_s64(a: i64, b: i64) -> i64 {
22560    unsafe extern "unadjusted" {
22561        #[cfg_attr(
22562            any(target_arch = "aarch64", target_arch = "arm64ec"),
22563            link_name = "llvm.aarch64.neon.srshl.i64"
22564        )]
22565        fn _vrshld_s64(a: i64, b: i64) -> i64;
22566    }
22567    unsafe { _vrshld_s64(a, b) }
22568}
22569#[doc = "Unsigned rounding shift left"]
22570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64)"]
22571#[inline]
22572#[target_feature(enable = "neon")]
22573#[cfg_attr(test, assert_instr(urshl))]
22574#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22575pub fn vrshld_u64(a: u64, b: i64) -> u64 {
22576    unsafe extern "unadjusted" {
22577        #[cfg_attr(
22578            any(target_arch = "aarch64", target_arch = "arm64ec"),
22579            link_name = "llvm.aarch64.neon.urshl.i64"
22580        )]
22581        fn _vrshld_u64(a: u64, b: i64) -> u64;
22582    }
22583    unsafe { _vrshld_u64(a, b) }
22584}
22585#[doc = "Signed rounding shift right"]
22586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64)"]
22587#[inline]
22588#[target_feature(enable = "neon")]
22589#[cfg_attr(test, assert_instr(srshr, N = 2))]
22590#[rustc_legacy_const_generics(1)]
22591#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22592pub fn vrshrd_n_s64<const N: i32>(a: i64) -> i64 {
22593    static_assert!(N >= 1 && N <= 64);
22594    vrshld_s64(a, -N as i64)
22595}
22596#[doc = "Unsigned rounding shift right"]
22597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64)"]
22598#[inline]
22599#[target_feature(enable = "neon")]
22600#[cfg_attr(test, assert_instr(urshr, N = 2))]
22601#[rustc_legacy_const_generics(1)]
22602#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22603pub fn vrshrd_n_u64<const N: i32>(a: u64) -> u64 {
22604    static_assert!(N >= 1 && N <= 64);
22605    vrshld_u64(a, -N as i64)
22606}
22607#[doc = "Rounding shift right narrow"]
22608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"]
22609#[inline]
22610#[target_feature(enable = "neon")]
22611#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
22612#[rustc_legacy_const_generics(2)]
22613#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22614pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
22615    static_assert!(N >= 1 && N <= 8);
22616    vcombine_s8(a, vrshrn_n_s16::<N>(b))
22617}
22618#[doc = "Rounding shift right narrow"]
22619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"]
22620#[inline]
22621#[target_feature(enable = "neon")]
22622#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
22623#[rustc_legacy_const_generics(2)]
22624#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22625pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
22626    static_assert!(N >= 1 && N <= 16);
22627    vcombine_s16(a, vrshrn_n_s32::<N>(b))
22628}
22629#[doc = "Rounding shift right narrow"]
22630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"]
22631#[inline]
22632#[target_feature(enable = "neon")]
22633#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
22634#[rustc_legacy_const_generics(2)]
22635#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22636pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
22637    static_assert!(N >= 1 && N <= 32);
22638    vcombine_s32(a, vrshrn_n_s64::<N>(b))
22639}
22640#[doc = "Rounding shift right narrow"]
22641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"]
22642#[inline]
22643#[target_feature(enable = "neon")]
22644#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
22645#[rustc_legacy_const_generics(2)]
22646#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22647pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
22648    static_assert!(N >= 1 && N <= 8);
22649    vcombine_u8(a, vrshrn_n_u16::<N>(b))
22650}
22651#[doc = "Rounding shift right narrow"]
22652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"]
22653#[inline]
22654#[target_feature(enable = "neon")]
22655#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
22656#[rustc_legacy_const_generics(2)]
22657#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22658pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
22659    static_assert!(N >= 1 && N <= 16);
22660    vcombine_u16(a, vrshrn_n_u32::<N>(b))
22661}
22662#[doc = "Rounding shift right narrow"]
22663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"]
22664#[inline]
22665#[target_feature(enable = "neon")]
22666#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
22667#[rustc_legacy_const_generics(2)]
22668#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22669pub fn vrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
22670    static_assert!(N >= 1 && N <= 32);
22671    vcombine_u32(a, vrshrn_n_u64::<N>(b))
22672}
22673#[doc = "Reciprocal square-root estimate."]
22674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"]
22675#[inline]
22676#[target_feature(enable = "neon")]
22677#[cfg_attr(test, assert_instr(frsqrte))]
22678#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22679pub fn vrsqrte_f64(a: float64x1_t) -> float64x1_t {
22680    unsafe extern "unadjusted" {
22681        #[cfg_attr(
22682            any(target_arch = "aarch64", target_arch = "arm64ec"),
22683            link_name = "llvm.aarch64.neon.frsqrte.v1f64"
22684        )]
22685        fn _vrsqrte_f64(a: float64x1_t) -> float64x1_t;
22686    }
22687    unsafe { _vrsqrte_f64(a) }
22688}
22689#[doc = "Reciprocal square-root estimate."]
22690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)"]
22691#[inline]
22692#[target_feature(enable = "neon")]
22693#[cfg_attr(test, assert_instr(frsqrte))]
22694#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22695pub fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t {
22696    unsafe extern "unadjusted" {
22697        #[cfg_attr(
22698            any(target_arch = "aarch64", target_arch = "arm64ec"),
22699            link_name = "llvm.aarch64.neon.frsqrte.v2f64"
22700        )]
22701        fn _vrsqrteq_f64(a: float64x2_t) -> float64x2_t;
22702    }
22703    unsafe { _vrsqrteq_f64(a) }
22704}
22705#[doc = "Reciprocal square-root estimate."]
22706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64)"]
22707#[inline]
22708#[target_feature(enable = "neon")]
22709#[cfg_attr(test, assert_instr(frsqrte))]
22710#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22711pub fn vrsqrted_f64(a: f64) -> f64 {
22712    unsafe extern "unadjusted" {
22713        #[cfg_attr(
22714            any(target_arch = "aarch64", target_arch = "arm64ec"),
22715            link_name = "llvm.aarch64.neon.frsqrte.f64"
22716        )]
22717        fn _vrsqrted_f64(a: f64) -> f64;
22718    }
22719    unsafe { _vrsqrted_f64(a) }
22720}
22721#[doc = "Reciprocal square-root estimate."]
22722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)"]
22723#[inline]
22724#[target_feature(enable = "neon")]
22725#[cfg_attr(test, assert_instr(frsqrte))]
22726#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22727pub fn vrsqrtes_f32(a: f32) -> f32 {
22728    unsafe extern "unadjusted" {
22729        #[cfg_attr(
22730            any(target_arch = "aarch64", target_arch = "arm64ec"),
22731            link_name = "llvm.aarch64.neon.frsqrte.f32"
22732        )]
22733        fn _vrsqrtes_f32(a: f32) -> f32;
22734    }
22735    unsafe { _vrsqrtes_f32(a) }
22736}
22737#[doc = "Reciprocal square-root estimate."]
22738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteh_f16)"]
22739#[inline]
22740#[cfg_attr(test, assert_instr(frsqrte))]
22741#[target_feature(enable = "neon,fp16")]
22742#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22743#[cfg(not(target_arch = "arm64ec"))]
22744pub fn vrsqrteh_f16(a: f16) -> f16 {
22745    unsafe extern "unadjusted" {
22746        #[cfg_attr(
22747            any(target_arch = "aarch64", target_arch = "arm64ec"),
22748            link_name = "llvm.aarch64.neon.frsqrte.f16"
22749        )]
22750        fn _vrsqrteh_f16(a: f16) -> f16;
22751    }
22752    unsafe { _vrsqrteh_f16(a) }
22753}
22754#[doc = "Floating-point reciprocal square root step"]
22755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)"]
22756#[inline]
22757#[target_feature(enable = "neon")]
22758#[cfg_attr(test, assert_instr(frsqrts))]
22759#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22760pub fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
22761    unsafe extern "unadjusted" {
22762        #[cfg_attr(
22763            any(target_arch = "aarch64", target_arch = "arm64ec"),
22764            link_name = "llvm.aarch64.neon.frsqrts.v1f64"
22765        )]
22766        fn _vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
22767    }
22768    unsafe { _vrsqrts_f64(a, b) }
22769}
22770#[doc = "Floating-point reciprocal square root step"]
22771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)"]
22772#[inline]
22773#[target_feature(enable = "neon")]
22774#[cfg_attr(test, assert_instr(frsqrts))]
22775#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22776pub fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
22777    unsafe extern "unadjusted" {
22778        #[cfg_attr(
22779            any(target_arch = "aarch64", target_arch = "arm64ec"),
22780            link_name = "llvm.aarch64.neon.frsqrts.v2f64"
22781        )]
22782        fn _vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
22783    }
22784    unsafe { _vrsqrtsq_f64(a, b) }
22785}
22786#[doc = "Floating-point reciprocal square root step"]
22787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64)"]
22788#[inline]
22789#[target_feature(enable = "neon")]
22790#[cfg_attr(test, assert_instr(frsqrts))]
22791#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22792pub fn vrsqrtsd_f64(a: f64, b: f64) -> f64 {
22793    unsafe extern "unadjusted" {
22794        #[cfg_attr(
22795            any(target_arch = "aarch64", target_arch = "arm64ec"),
22796            link_name = "llvm.aarch64.neon.frsqrts.f64"
22797        )]
22798        fn _vrsqrtsd_f64(a: f64, b: f64) -> f64;
22799    }
22800    unsafe { _vrsqrtsd_f64(a, b) }
22801}
22802#[doc = "Floating-point reciprocal square root step"]
22803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)"]
22804#[inline]
22805#[target_feature(enable = "neon")]
22806#[cfg_attr(test, assert_instr(frsqrts))]
22807#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22808pub fn vrsqrtss_f32(a: f32, b: f32) -> f32 {
22809    unsafe extern "unadjusted" {
22810        #[cfg_attr(
22811            any(target_arch = "aarch64", target_arch = "arm64ec"),
22812            link_name = "llvm.aarch64.neon.frsqrts.f32"
22813        )]
22814        fn _vrsqrtss_f32(a: f32, b: f32) -> f32;
22815    }
22816    unsafe { _vrsqrtss_f32(a, b) }
22817}
22818#[doc = "Floating-point reciprocal square root step"]
22819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsh_f16)"]
22820#[inline]
22821#[target_feature(enable = "neon,fp16")]
22822#[cfg_attr(test, assert_instr(frsqrts))]
22823#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22824#[cfg(not(target_arch = "arm64ec"))]
22825pub fn vrsqrtsh_f16(a: f16, b: f16) -> f16 {
22826    unsafe extern "unadjusted" {
22827        #[cfg_attr(
22828            any(target_arch = "aarch64", target_arch = "arm64ec"),
22829            link_name = "llvm.aarch64.neon.frsqrts.f16"
22830        )]
22831        fn _vrsqrtsh_f16(a: f16, b: f16) -> f16;
22832    }
22833    unsafe { _vrsqrtsh_f16(a, b) }
22834}
22835#[doc = "Signed rounding shift right and accumulate."]
22836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64)"]
22837#[inline]
22838#[target_feature(enable = "neon")]
22839#[cfg_attr(test, assert_instr(srshr, N = 2))]
22840#[rustc_legacy_const_generics(2)]
22841#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22842pub fn vrsrad_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
22843    static_assert!(N >= 1 && N <= 64);
22844    let b: i64 = vrshrd_n_s64::<N>(b);
22845    a.wrapping_add(b)
22846}
22847#[doc = "Unsigned rounding shift right and accumulate."]
22848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64)"]
22849#[inline]
22850#[target_feature(enable = "neon")]
22851#[cfg_attr(test, assert_instr(urshr, N = 2))]
22852#[rustc_legacy_const_generics(2)]
22853#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22854pub fn vrsrad_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
22855    static_assert!(N >= 1 && N <= 64);
22856    let b: u64 = vrshrd_n_u64::<N>(b);
22857    a.wrapping_add(b)
22858}
22859#[doc = "Rounding subtract returning high narrow"]
22860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"]
22861#[inline]
22862#[target_feature(enable = "neon")]
22863#[cfg(target_endian = "little")]
22864#[cfg_attr(test, assert_instr(rsubhn2))]
22865#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22866pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
22867    vcombine_s8(a, vrsubhn_s16(b, c))
22868}
22869#[doc = "Rounding subtract returning high narrow"]
22870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
22871#[inline]
22872#[target_feature(enable = "neon")]
22873#[cfg(target_endian = "little")]
22874#[cfg_attr(test, assert_instr(rsubhn2))]
22875#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22876pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
22877    vcombine_s16(a, vrsubhn_s32(b, c))
22878}
22879#[doc = "Rounding subtract returning high narrow"]
22880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
22881#[inline]
22882#[target_feature(enable = "neon")]
22883#[cfg(target_endian = "little")]
22884#[cfg_attr(test, assert_instr(rsubhn2))]
22885#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22886pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
22887    vcombine_s32(a, vrsubhn_s64(b, c))
22888}
22889#[doc = "Rounding subtract returning high narrow"]
22890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
22891#[inline]
22892#[target_feature(enable = "neon")]
22893#[cfg(target_endian = "little")]
22894#[cfg_attr(test, assert_instr(rsubhn2))]
22895#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22896pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
22897    vcombine_u8(a, vrsubhn_u16(b, c))
22898}
22899#[doc = "Rounding subtract returning high narrow"]
22900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
22901#[inline]
22902#[target_feature(enable = "neon")]
22903#[cfg(target_endian = "little")]
22904#[cfg_attr(test, assert_instr(rsubhn2))]
22905#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22906pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
22907    vcombine_u16(a, vrsubhn_u32(b, c))
22908}
22909#[doc = "Rounding subtract returning high narrow"]
22910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
22911#[inline]
22912#[target_feature(enable = "neon")]
22913#[cfg(target_endian = "little")]
22914#[cfg_attr(test, assert_instr(rsubhn2))]
22915#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22916pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
22917    vcombine_u32(a, vrsubhn_u64(b, c))
22918}
22919#[doc = "Rounding subtract returning high narrow"]
22920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"]
22921#[inline]
22922#[target_feature(enable = "neon")]
22923#[cfg(target_endian = "big")]
22924#[cfg_attr(test, assert_instr(rsubhn))]
22925#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22926pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
22927    vcombine_s8(a, vrsubhn_s16(b, c))
22928}
22929#[doc = "Rounding subtract returning high narrow"]
22930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
22931#[inline]
22932#[target_feature(enable = "neon")]
22933#[cfg(target_endian = "big")]
22934#[cfg_attr(test, assert_instr(rsubhn))]
22935#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22936pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
22937    vcombine_s16(a, vrsubhn_s32(b, c))
22938}
22939#[doc = "Rounding subtract returning high narrow"]
22940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
22941#[inline]
22942#[target_feature(enable = "neon")]
22943#[cfg(target_endian = "big")]
22944#[cfg_attr(test, assert_instr(rsubhn))]
22945#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22946pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
22947    vcombine_s32(a, vrsubhn_s64(b, c))
22948}
22949#[doc = "Rounding subtract returning high narrow"]
22950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
22951#[inline]
22952#[target_feature(enable = "neon")]
22953#[cfg(target_endian = "big")]
22954#[cfg_attr(test, assert_instr(rsubhn))]
22955#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22956pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
22957    vcombine_u8(a, vrsubhn_u16(b, c))
22958}
22959#[doc = "Rounding subtract returning high narrow"]
22960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
22961#[inline]
22962#[target_feature(enable = "neon")]
22963#[cfg(target_endian = "big")]
22964#[cfg_attr(test, assert_instr(rsubhn))]
22965#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22966pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
22967    vcombine_u16(a, vrsubhn_u32(b, c))
22968}
22969#[doc = "Rounding subtract returning high narrow"]
22970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
22971#[inline]
22972#[target_feature(enable = "neon")]
22973#[cfg(target_endian = "big")]
22974#[cfg_attr(test, assert_instr(rsubhn))]
22975#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22976pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
22977    vcombine_u32(a, vrsubhn_u64(b, c))
22978}
22979#[doc = "Multi-vector floating-point adjust exponent"]
22980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"]
22981#[inline]
22982#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
22983#[target_feature(enable = "neon,fp8")]
22984#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
22985pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
22986    unsafe extern "unadjusted" {
22987        #[cfg_attr(
22988            any(target_arch = "aarch64", target_arch = "arm64ec"),
22989            link_name = "llvm.aarch64.neon.fp8.fscale.v4f16"
22990        )]
22991        fn _vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t;
22992    }
22993    unsafe { _vscale_f16(vn, vm) }
22994}
22995#[doc = "Multi-vector floating-point adjust exponent"]
22996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"]
22997#[inline]
22998#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
22999#[target_feature(enable = "neon,fp8")]
23000#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
23001pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
23002    unsafe extern "unadjusted" {
23003        #[cfg_attr(
23004            any(target_arch = "aarch64", target_arch = "arm64ec"),
23005            link_name = "llvm.aarch64.neon.fp8.fscale.v8f16"
23006        )]
23007        fn _vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t;
23008    }
23009    unsafe { _vscaleq_f16(vn, vm) }
23010}
23011#[doc = "Multi-vector floating-point adjust exponent"]
23012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"]
23013#[inline]
23014#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
23015#[target_feature(enable = "neon,fp8")]
23016#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
23017pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
23018    unsafe extern "unadjusted" {
23019        #[cfg_attr(
23020            any(target_arch = "aarch64", target_arch = "arm64ec"),
23021            link_name = "llvm.aarch64.neon.fp8.fscale.v2f32"
23022        )]
23023        fn _vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t;
23024    }
23025    unsafe { _vscale_f32(vn, vm) }
23026}
23027#[doc = "Multi-vector floating-point adjust exponent"]
23028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"]
23029#[inline]
23030#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
23031#[target_feature(enable = "neon,fp8")]
23032#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
23033pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
23034    unsafe extern "unadjusted" {
23035        #[cfg_attr(
23036            any(target_arch = "aarch64", target_arch = "arm64ec"),
23037            link_name = "llvm.aarch64.neon.fp8.fscale.v4f32"
23038        )]
23039        fn _vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t;
23040    }
23041    unsafe { _vscaleq_f32(vn, vm) }
23042}
23043#[doc = "Multi-vector floating-point adjust exponent"]
23044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"]
23045#[inline]
23046#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
23047#[target_feature(enable = "neon,fp8")]
23048#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
23049pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t {
23050    unsafe extern "unadjusted" {
23051        #[cfg_attr(
23052            any(target_arch = "aarch64", target_arch = "arm64ec"),
23053            link_name = "llvm.aarch64.neon.fp8.fscale.v2f64"
23054        )]
23055        fn _vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t;
23056    }
23057    unsafe { _vscaleq_f64(vn, vm) }
23058}
23059#[doc = "Insert vector element from another vector element"]
23060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"]
23061#[inline]
23062#[target_feature(enable = "neon")]
23063#[cfg_attr(test, assert_instr(nop, LANE = 0))]
23064#[rustc_legacy_const_generics(2)]
23065#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23066pub fn vset_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> float64x1_t {
23067    static_assert!(LANE == 0);
23068    unsafe { simd_insert!(b, LANE as u32, a) }
23069}
23070#[doc = "Insert vector element from another vector element"]
23071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"]
23072#[inline]
23073#[cfg(target_endian = "little")]
23074#[target_feature(enable = "neon")]
23075#[cfg_attr(test, assert_instr(nop, LANE = 0))]
23076#[rustc_legacy_const_generics(2)]
23077#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23078pub fn vsetq_lane_f64<const LANE: i32>(a: f64, b: float64x2_t) -> float64x2_t {
23079    static_assert_uimm_bits!(LANE, 1);
23080    unsafe { simd_insert!(b, LANE as u32, a) }
23081}
23082#[doc = "Insert vector element from another vector element"]
23083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"]
23084#[inline]
23085#[cfg(target_endian = "big")]
23086#[target_feature(enable = "neon")]
23087#[cfg_attr(test, assert_instr(nop, LANE = 0))]
23088#[rustc_legacy_const_generics(2)]
23089#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23090pub fn vsetq_lane_f64<const LANE: i32>(a: f64, b: float64x2_t) -> float64x2_t {
23091    static_assert_uimm_bits!(LANE, 1);
23092    unsafe {
23093        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
23094        let ret_val: float64x2_t = simd_insert!(b, LANE as u32, a);
23095        simd_shuffle!(ret_val, ret_val, [1, 0])
23096    }
23097}
23098#[doc = "SHA512 hash update part 2"]
23099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"]
23100#[inline]
23101#[cfg(target_endian = "little")]
23102#[target_feature(enable = "neon,sha3")]
23103#[cfg_attr(test, assert_instr(sha512h2))]
23104#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
23105pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
23106    unsafe extern "unadjusted" {
23107        #[cfg_attr(
23108            any(target_arch = "aarch64", target_arch = "arm64ec"),
23109            link_name = "llvm.aarch64.crypto.sha512h2"
23110        )]
23111        fn _vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t;
23112    }
23113    unsafe { _vsha512h2q_u64(a, b, c) }
23114}
23115#[doc = "SHA512 hash update part 2"]
23116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"]
23117#[inline]
23118#[cfg(target_endian = "big")]
23119#[target_feature(enable = "neon,sha3")]
23120#[cfg_attr(test, assert_instr(sha512h2))]
23121#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
23122pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
23123    unsafe extern "unadjusted" {
23124        #[cfg_attr(
23125            any(target_arch = "aarch64", target_arch = "arm64ec"),
23126            link_name = "llvm.aarch64.crypto.sha512h2"
23127        )]
23128        fn _vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t;
23129    }
23130    unsafe {
23131        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
23132        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
23133        let c: uint64x2_t = simd_shuffle!(c, c, [1, 0]);
23134        let ret_val: uint64x2_t = _vsha512h2q_u64(a, b, c);
23135        simd_shuffle!(ret_val, ret_val, [1, 0])
23136    }
23137}
23138#[doc = "SHA512 hash update part 1"]
23139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"]
23140#[inline]
23141#[cfg(target_endian = "little")]
23142#[target_feature(enable = "neon,sha3")]
23143#[cfg_attr(test, assert_instr(sha512h))]
23144#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
23145pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
23146    unsafe extern "unadjusted" {
23147        #[cfg_attr(
23148            any(target_arch = "aarch64", target_arch = "arm64ec"),
23149            link_name = "llvm.aarch64.crypto.sha512h"
23150        )]
23151        fn _vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t;
23152    }
23153    unsafe { _vsha512hq_u64(a, b, c) }
23154}
23155#[doc = "SHA512 hash update part 1"]
23156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"]
23157#[inline]
23158#[cfg(target_endian = "big")]
23159#[target_feature(enable = "neon,sha3")]
23160#[cfg_attr(test, assert_instr(sha512h))]
23161#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
23162pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
23163    unsafe extern "unadjusted" {
23164        #[cfg_attr(
23165            any(target_arch = "aarch64", target_arch = "arm64ec"),
23166            link_name = "llvm.aarch64.crypto.sha512h"
23167        )]
23168        fn _vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t;
23169    }
23170    unsafe {
23171        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
23172        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
23173        let c: uint64x2_t = simd_shuffle!(c, c, [1, 0]);
23174        let ret_val: uint64x2_t = _vsha512hq_u64(a, b, c);
23175        simd_shuffle!(ret_val, ret_val, [1, 0])
23176    }
23177}
23178#[doc = "SHA512 schedule update 0"]
23179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"]
23180#[inline]
23181#[cfg(target_endian = "little")]
23182#[target_feature(enable = "neon,sha3")]
23183#[cfg_attr(test, assert_instr(sha512su0))]
23184#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
23185pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
23186    unsafe extern "unadjusted" {
23187        #[cfg_attr(
23188            any(target_arch = "aarch64", target_arch = "arm64ec"),
23189            link_name = "llvm.aarch64.crypto.sha512su0"
23190        )]
23191        fn _vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
23192    }
23193    unsafe { _vsha512su0q_u64(a, b) }
23194}
23195#[doc = "SHA512 schedule update 0"]
23196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"]
23197#[inline]
23198#[cfg(target_endian = "big")]
23199#[target_feature(enable = "neon,sha3")]
23200#[cfg_attr(test, assert_instr(sha512su0))]
23201#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
23202pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
23203    unsafe extern "unadjusted" {
23204        #[cfg_attr(
23205            any(target_arch = "aarch64", target_arch = "arm64ec"),
23206            link_name = "llvm.aarch64.crypto.sha512su0"
23207        )]
23208        fn _vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
23209    }
23210    unsafe {
23211        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
23212        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
23213        let ret_val: uint64x2_t = _vsha512su0q_u64(a, b);
23214        simd_shuffle!(ret_val, ret_val, [1, 0])
23215    }
23216}
23217#[doc = "SHA512 schedule update 1"]
23218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"]
23219#[inline]
23220#[cfg(target_endian = "little")]
23221#[target_feature(enable = "neon,sha3")]
23222#[cfg_attr(test, assert_instr(sha512su1))]
23223#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
23224pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
23225    unsafe extern "unadjusted" {
23226        #[cfg_attr(
23227            any(target_arch = "aarch64", target_arch = "arm64ec"),
23228            link_name = "llvm.aarch64.crypto.sha512su1"
23229        )]
23230        fn _vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t;
23231    }
23232    unsafe { _vsha512su1q_u64(a, b, c) }
23233}
23234#[doc = "SHA512 schedule update 1"]
23235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"]
23236#[inline]
23237#[cfg(target_endian = "big")]
23238#[target_feature(enable = "neon,sha3")]
23239#[cfg_attr(test, assert_instr(sha512su1))]
23240#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
23241pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
23242    unsafe extern "unadjusted" {
23243        #[cfg_attr(
23244            any(target_arch = "aarch64", target_arch = "arm64ec"),
23245            link_name = "llvm.aarch64.crypto.sha512su1"
23246        )]
23247        fn _vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t;
23248    }
23249    unsafe {
23250        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
23251        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
23252        let c: uint64x2_t = simd_shuffle!(c, c, [1, 0]);
23253        let ret_val: uint64x2_t = _vsha512su1q_u64(a, b, c);
23254        simd_shuffle!(ret_val, ret_val, [1, 0])
23255    }
23256}
23257#[doc = "Signed Shift left"]
23258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64)"]
23259#[inline]
23260#[target_feature(enable = "neon")]
23261#[cfg_attr(test, assert_instr(sshl))]
23262#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23263pub fn vshld_s64(a: i64, b: i64) -> i64 {
23264    unsafe { transmute(vshl_s64(transmute(a), transmute(b))) }
23265}
23266#[doc = "Unsigned Shift left"]
23267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64)"]
23268#[inline]
23269#[target_feature(enable = "neon")]
23270#[cfg_attr(test, assert_instr(ushl))]
23271#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23272pub fn vshld_u64(a: u64, b: i64) -> u64 {
23273    unsafe { transmute(vshl_u64(transmute(a), transmute(b))) }
23274}
23275#[doc = "Signed shift left long"]
23276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"]
23277#[inline]
23278#[target_feature(enable = "neon")]
23279#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))]
23280#[rustc_legacy_const_generics(1)]
23281#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23282pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
23283    static_assert!(N >= 0 && N <= 8);
23284    let b = vget_high_s8(a);
23285    vshll_n_s8::<N>(b)
23286}
23287#[doc = "Signed shift left long"]
23288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"]
23289#[inline]
23290#[target_feature(enable = "neon")]
23291#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))]
23292#[rustc_legacy_const_generics(1)]
23293#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23294pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
23295    static_assert!(N >= 0 && N <= 16);
23296    let b = vget_high_s16(a);
23297    vshll_n_s16::<N>(b)
23298}
23299#[doc = "Signed shift left long"]
23300#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"]
23301#[inline]
23302#[target_feature(enable = "neon")]
23303#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))]
23304#[rustc_legacy_const_generics(1)]
23305#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23306pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
23307    static_assert!(N >= 0 && N <= 32);
23308    let b = vget_high_s32(a);
23309    vshll_n_s32::<N>(b)
23310}
23311#[doc = "Signed shift left long"]
23312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"]
23313#[inline]
23314#[target_feature(enable = "neon")]
23315#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))]
23316#[rustc_legacy_const_generics(1)]
23317#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23318pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
23319    static_assert!(N >= 0 && N <= 8);
23320    let b: uint8x8_t = vget_high_u8(a);
23321    vshll_n_u8::<N>(b)
23322}
23323#[doc = "Signed shift left long"]
23324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"]
23325#[inline]
23326#[target_feature(enable = "neon")]
23327#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))]
23328#[rustc_legacy_const_generics(1)]
23329#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23330pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
23331    static_assert!(N >= 0 && N <= 16);
23332    let b: uint16x4_t = vget_high_u16(a);
23333    vshll_n_u16::<N>(b)
23334}
23335#[doc = "Signed shift left long"]
23336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"]
23337#[inline]
23338#[target_feature(enable = "neon")]
23339#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))]
23340#[rustc_legacy_const_generics(1)]
23341#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23342pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
23343    static_assert!(N >= 0 && N <= 32);
23344    let b: uint32x2_t = vget_high_u32(a);
23345    vshll_n_u32::<N>(b)
23346}
23347#[doc = "Shift right narrow"]
23348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"]
23349#[inline]
23350#[target_feature(enable = "neon")]
23351#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
23352#[rustc_legacy_const_generics(2)]
23353#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23354pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
23355    static_assert!(N >= 1 && N <= 8);
23356    vcombine_s8(a, vshrn_n_s16::<N>(b))
23357}
23358#[doc = "Shift right narrow"]
23359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"]
23360#[inline]
23361#[target_feature(enable = "neon")]
23362#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
23363#[rustc_legacy_const_generics(2)]
23364#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23365pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
23366    static_assert!(N >= 1 && N <= 16);
23367    vcombine_s16(a, vshrn_n_s32::<N>(b))
23368}
23369#[doc = "Shift right narrow"]
23370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"]
23371#[inline]
23372#[target_feature(enable = "neon")]
23373#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
23374#[rustc_legacy_const_generics(2)]
23375#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23376pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
23377    static_assert!(N >= 1 && N <= 32);
23378    vcombine_s32(a, vshrn_n_s64::<N>(b))
23379}
23380#[doc = "Shift right narrow"]
23381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"]
23382#[inline]
23383#[target_feature(enable = "neon")]
23384#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
23385#[rustc_legacy_const_generics(2)]
23386#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23387pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
23388    static_assert!(N >= 1 && N <= 8);
23389    vcombine_u8(a, vshrn_n_u16::<N>(b))
23390}
23391#[doc = "Shift right narrow"]
23392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"]
23393#[inline]
23394#[target_feature(enable = "neon")]
23395#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
23396#[rustc_legacy_const_generics(2)]
23397#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23398pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
23399    static_assert!(N >= 1 && N <= 16);
23400    vcombine_u16(a, vshrn_n_u32::<N>(b))
23401}
23402#[doc = "Shift right narrow"]
23403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"]
23404#[inline]
23405#[target_feature(enable = "neon")]
23406#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
23407#[rustc_legacy_const_generics(2)]
23408#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23409pub fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
23410    static_assert!(N >= 1 && N <= 32);
23411    vcombine_u32(a, vshrn_n_u64::<N>(b))
23412}
23413#[doc = "Shift Left and Insert (immediate)"]
23414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
23415#[inline]
23416#[target_feature(enable = "neon")]
23417#[cfg_attr(test, assert_instr(sli, N = 1))]
23418#[rustc_legacy_const_generics(2)]
23419#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23420pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
23421    static_assert_uimm_bits!(N, 3);
23422    unsafe extern "unadjusted" {
23423        #[cfg_attr(
23424            any(target_arch = "aarch64", target_arch = "arm64ec"),
23425            link_name = "llvm.aarch64.neon.vsli.v8i8"
23426        )]
23427        fn _vsli_n_s8(a: int8x8_t, b: int8x8_t, n: i32) -> int8x8_t;
23428    }
23429    unsafe { _vsli_n_s8(a, b, N) }
23430}
23431#[doc = "Shift Left and Insert (immediate)"]
23432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
23433#[inline]
23434#[target_feature(enable = "neon")]
23435#[cfg_attr(test, assert_instr(sli, N = 1))]
23436#[rustc_legacy_const_generics(2)]
23437#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23438pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
23439    static_assert_uimm_bits!(N, 3);
23440    unsafe extern "unadjusted" {
23441        #[cfg_attr(
23442            any(target_arch = "aarch64", target_arch = "arm64ec"),
23443            link_name = "llvm.aarch64.neon.vsli.v16i8"
23444        )]
23445        fn _vsliq_n_s8(a: int8x16_t, b: int8x16_t, n: i32) -> int8x16_t;
23446    }
23447    unsafe { _vsliq_n_s8(a, b, N) }
23448}
23449#[doc = "Shift Left and Insert (immediate)"]
23450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
23451#[inline]
23452#[target_feature(enable = "neon")]
23453#[cfg_attr(test, assert_instr(sli, N = 1))]
23454#[rustc_legacy_const_generics(2)]
23455#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23456pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
23457    static_assert_uimm_bits!(N, 4);
23458    unsafe extern "unadjusted" {
23459        #[cfg_attr(
23460            any(target_arch = "aarch64", target_arch = "arm64ec"),
23461            link_name = "llvm.aarch64.neon.vsli.v4i16"
23462        )]
23463        fn _vsli_n_s16(a: int16x4_t, b: int16x4_t, n: i32) -> int16x4_t;
23464    }
23465    unsafe { _vsli_n_s16(a, b, N) }
23466}
23467#[doc = "Shift Left and Insert (immediate)"]
23468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
23469#[inline]
23470#[target_feature(enable = "neon")]
23471#[cfg_attr(test, assert_instr(sli, N = 1))]
23472#[rustc_legacy_const_generics(2)]
23473#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23474pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
23475    static_assert_uimm_bits!(N, 4);
23476    unsafe extern "unadjusted" {
23477        #[cfg_attr(
23478            any(target_arch = "aarch64", target_arch = "arm64ec"),
23479            link_name = "llvm.aarch64.neon.vsli.v8i16"
23480        )]
23481        fn _vsliq_n_s16(a: int16x8_t, b: int16x8_t, n: i32) -> int16x8_t;
23482    }
23483    unsafe { _vsliq_n_s16(a, b, N) }
23484}
23485#[doc = "Shift Left and Insert (immediate)"]
23486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
23487#[inline]
23488#[target_feature(enable = "neon")]
23489#[cfg_attr(test, assert_instr(sli, N = 1))]
23490#[rustc_legacy_const_generics(2)]
23491#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23492pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
23493    static_assert!(N >= 0 && N <= 31);
23494    unsafe extern "unadjusted" {
23495        #[cfg_attr(
23496            any(target_arch = "aarch64", target_arch = "arm64ec"),
23497            link_name = "llvm.aarch64.neon.vsli.v2i32"
23498        )]
23499        fn _vsli_n_s32(a: int32x2_t, b: int32x2_t, n: i32) -> int32x2_t;
23500    }
23501    unsafe { _vsli_n_s32(a, b, N) }
23502}
23503#[doc = "Shift Left and Insert (immediate)"]
23504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
23505#[inline]
23506#[target_feature(enable = "neon")]
23507#[cfg_attr(test, assert_instr(sli, N = 1))]
23508#[rustc_legacy_const_generics(2)]
23509#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23510pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
23511    static_assert!(N >= 0 && N <= 31);
23512    unsafe extern "unadjusted" {
23513        #[cfg_attr(
23514            any(target_arch = "aarch64", target_arch = "arm64ec"),
23515            link_name = "llvm.aarch64.neon.vsli.v4i32"
23516        )]
23517        fn _vsliq_n_s32(a: int32x4_t, b: int32x4_t, n: i32) -> int32x4_t;
23518    }
23519    unsafe { _vsliq_n_s32(a, b, N) }
23520}
23521#[doc = "Shift Left and Insert (immediate)"]
23522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
23523#[inline]
23524#[target_feature(enable = "neon")]
23525#[cfg_attr(test, assert_instr(sli, N = 1))]
23526#[rustc_legacy_const_generics(2)]
23527#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23528pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
23529    static_assert!(N >= 0 && N <= 63);
23530    unsafe extern "unadjusted" {
23531        #[cfg_attr(
23532            any(target_arch = "aarch64", target_arch = "arm64ec"),
23533            link_name = "llvm.aarch64.neon.vsli.v1i64"
23534        )]
23535        fn _vsli_n_s64(a: int64x1_t, b: int64x1_t, n: i32) -> int64x1_t;
23536    }
23537    unsafe { _vsli_n_s64(a, b, N) }
23538}
23539#[doc = "Shift Left and Insert (immediate)"]
23540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
23541#[inline]
23542#[target_feature(enable = "neon")]
23543#[cfg_attr(test, assert_instr(sli, N = 1))]
23544#[rustc_legacy_const_generics(2)]
23545#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23546pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
23547    static_assert!(N >= 0 && N <= 63);
23548    unsafe extern "unadjusted" {
23549        #[cfg_attr(
23550            any(target_arch = "aarch64", target_arch = "arm64ec"),
23551            link_name = "llvm.aarch64.neon.vsli.v2i64"
23552        )]
23553        fn _vsliq_n_s64(a: int64x2_t, b: int64x2_t, n: i32) -> int64x2_t;
23554    }
23555    unsafe { _vsliq_n_s64(a, b, N) }
23556}
23557#[doc = "Shift Left and Insert (immediate)"]
23558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
23559#[inline]
23560#[target_feature(enable = "neon")]
23561#[cfg_attr(test, assert_instr(sli, N = 1))]
23562#[rustc_legacy_const_generics(2)]
23563#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23564pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
23565    static_assert_uimm_bits!(N, 3);
23566    unsafe { transmute(vsli_n_s8::<N>(transmute(a), transmute(b))) }
23567}
23568#[doc = "Shift Left and Insert (immediate)"]
23569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
23570#[inline]
23571#[target_feature(enable = "neon")]
23572#[cfg_attr(test, assert_instr(sli, N = 1))]
23573#[rustc_legacy_const_generics(2)]
23574#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23575pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
23576    static_assert_uimm_bits!(N, 3);
23577    unsafe { transmute(vsliq_n_s8::<N>(transmute(a), transmute(b))) }
23578}
23579#[doc = "Shift Left and Insert (immediate)"]
23580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
23581#[inline]
23582#[target_feature(enable = "neon")]
23583#[cfg_attr(test, assert_instr(sli, N = 1))]
23584#[rustc_legacy_const_generics(2)]
23585#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23586pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
23587    static_assert_uimm_bits!(N, 4);
23588    unsafe { transmute(vsli_n_s16::<N>(transmute(a), transmute(b))) }
23589}
23590#[doc = "Shift Left and Insert (immediate)"]
23591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
23592#[inline]
23593#[target_feature(enable = "neon")]
23594#[cfg_attr(test, assert_instr(sli, N = 1))]
23595#[rustc_legacy_const_generics(2)]
23596#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23597pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
23598    static_assert_uimm_bits!(N, 4);
23599    unsafe { transmute(vsliq_n_s16::<N>(transmute(a), transmute(b))) }
23600}
23601#[doc = "Shift Left and Insert (immediate)"]
23602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
23603#[inline]
23604#[target_feature(enable = "neon")]
23605#[cfg_attr(test, assert_instr(sli, N = 1))]
23606#[rustc_legacy_const_generics(2)]
23607#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23608pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
23609    static_assert!(N >= 0 && N <= 31);
23610    unsafe { transmute(vsli_n_s32::<N>(transmute(a), transmute(b))) }
23611}
23612#[doc = "Shift Left and Insert (immediate)"]
23613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
23614#[inline]
23615#[target_feature(enable = "neon")]
23616#[cfg_attr(test, assert_instr(sli, N = 1))]
23617#[rustc_legacy_const_generics(2)]
23618#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23619pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
23620    static_assert!(N >= 0 && N <= 31);
23621    unsafe { transmute(vsliq_n_s32::<N>(transmute(a), transmute(b))) }
23622}
23623#[doc = "Shift Left and Insert (immediate)"]
23624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
23625#[inline]
23626#[target_feature(enable = "neon")]
23627#[cfg_attr(test, assert_instr(sli, N = 1))]
23628#[rustc_legacy_const_generics(2)]
23629#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23630pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
23631    static_assert!(N >= 0 && N <= 63);
23632    unsafe { transmute(vsli_n_s64::<N>(transmute(a), transmute(b))) }
23633}
23634#[doc = "Shift Left and Insert (immediate)"]
23635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
23636#[inline]
23637#[target_feature(enable = "neon")]
23638#[cfg_attr(test, assert_instr(sli, N = 1))]
23639#[rustc_legacy_const_generics(2)]
23640#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23641pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
23642    static_assert!(N >= 0 && N <= 63);
23643    unsafe { transmute(vsliq_n_s64::<N>(transmute(a), transmute(b))) }
23644}
23645#[doc = "Shift Left and Insert (immediate)"]
23646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
23647#[inline]
23648#[target_feature(enable = "neon")]
23649#[cfg_attr(test, assert_instr(sli, N = 1))]
23650#[rustc_legacy_const_generics(2)]
23651#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23652pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
23653    static_assert_uimm_bits!(N, 3);
23654    unsafe { transmute(vsli_n_s8::<N>(transmute(a), transmute(b))) }
23655}
23656#[doc = "Shift Left and Insert (immediate)"]
23657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
23658#[inline]
23659#[target_feature(enable = "neon")]
23660#[cfg_attr(test, assert_instr(sli, N = 1))]
23661#[rustc_legacy_const_generics(2)]
23662#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23663pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
23664    static_assert_uimm_bits!(N, 3);
23665    unsafe { transmute(vsliq_n_s8::<N>(transmute(a), transmute(b))) }
23666}
23667#[doc = "Shift Left and Insert (immediate)"]
23668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
23669#[inline]
23670#[target_feature(enable = "neon")]
23671#[cfg_attr(test, assert_instr(sli, N = 1))]
23672#[rustc_legacy_const_generics(2)]
23673#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23674pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
23675    static_assert_uimm_bits!(N, 4);
23676    unsafe { transmute(vsli_n_s16::<N>(transmute(a), transmute(b))) }
23677}
23678#[doc = "Shift Left and Insert (immediate)"]
23679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
23680#[inline]
23681#[target_feature(enable = "neon")]
23682#[cfg_attr(test, assert_instr(sli, N = 1))]
23683#[rustc_legacy_const_generics(2)]
23684#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23685pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
23686    static_assert_uimm_bits!(N, 4);
23687    unsafe { transmute(vsliq_n_s16::<N>(transmute(a), transmute(b))) }
23688}
23689#[doc = "Shift Left and Insert (immediate)"]
23690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p64)"]
23691#[inline]
23692#[target_feature(enable = "neon,aes")]
23693#[cfg_attr(test, assert_instr(sli, N = 1))]
23694#[rustc_legacy_const_generics(2)]
23695#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23696pub fn vsli_n_p64<const N: i32>(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
23697    static_assert!(N >= 0 && N <= 63);
23698    unsafe { transmute(vsli_n_s64::<N>(transmute(a), transmute(b))) }
23699}
23700#[doc = "Shift Left and Insert (immediate)"]
23701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p64)"]
23702#[inline]
23703#[target_feature(enable = "neon,aes")]
23704#[cfg_attr(test, assert_instr(sli, N = 1))]
23705#[rustc_legacy_const_generics(2)]
23706#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23707pub fn vsliq_n_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
23708    static_assert!(N >= 0 && N <= 63);
23709    unsafe { transmute(vsliq_n_s64::<N>(transmute(a), transmute(b))) }
23710}
23711#[doc = "Shift left and insert"]
23712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64)"]
23713#[inline]
23714#[target_feature(enable = "neon")]
23715#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23716#[rustc_legacy_const_generics(2)]
23717#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sli, N = 2))]
23718pub fn vslid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
23719    static_assert!(N >= 0 && N <= 63);
23720    unsafe { transmute(vsli_n_s64::<N>(transmute(a), transmute(b))) }
23721}
23722#[doc = "Shift left and insert"]
23723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64)"]
23724#[inline]
23725#[target_feature(enable = "neon")]
23726#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23727#[rustc_legacy_const_generics(2)]
23728#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sli, N = 2))]
23729pub fn vslid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
23730    static_assert!(N >= 0 && N <= 63);
23731    unsafe { transmute(vsli_n_u64::<N>(transmute(a), transmute(b))) }
23732}
23733#[doc = "SM3PARTW1"]
23734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"]
23735#[inline]
23736#[cfg(target_endian = "little")]
23737#[target_feature(enable = "neon,sm4")]
23738#[cfg_attr(test, assert_instr(sm3partw1))]
23739#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23740pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23741    unsafe extern "unadjusted" {
23742        #[cfg_attr(
23743            any(target_arch = "aarch64", target_arch = "arm64ec"),
23744            link_name = "llvm.aarch64.crypto.sm3partw1"
23745        )]
23746        fn _vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t;
23747    }
23748    unsafe { _vsm3partw1q_u32(a, b, c) }
23749}
23750#[doc = "SM3PARTW1"]
23751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"]
23752#[inline]
23753#[cfg(target_endian = "big")]
23754#[target_feature(enable = "neon,sm4")]
23755#[cfg_attr(test, assert_instr(sm3partw1))]
23756#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23757pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23758    unsafe extern "unadjusted" {
23759        #[cfg_attr(
23760            any(target_arch = "aarch64", target_arch = "arm64ec"),
23761            link_name = "llvm.aarch64.crypto.sm3partw1"
23762        )]
23763        fn _vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t;
23764    }
23765    unsafe {
23766        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
23767        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
23768        let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
23769        let ret_val: uint32x4_t = _vsm3partw1q_u32(a, b, c);
23770        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
23771    }
23772}
23773#[doc = "SM3PARTW2"]
23774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"]
23775#[inline]
23776#[cfg(target_endian = "little")]
23777#[target_feature(enable = "neon,sm4")]
23778#[cfg_attr(test, assert_instr(sm3partw2))]
23779#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23780pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23781    unsafe extern "unadjusted" {
23782        #[cfg_attr(
23783            any(target_arch = "aarch64", target_arch = "arm64ec"),
23784            link_name = "llvm.aarch64.crypto.sm3partw2"
23785        )]
23786        fn _vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t;
23787    }
23788    unsafe { _vsm3partw2q_u32(a, b, c) }
23789}
23790#[doc = "SM3PARTW2"]
23791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"]
23792#[inline]
23793#[cfg(target_endian = "big")]
23794#[target_feature(enable = "neon,sm4")]
23795#[cfg_attr(test, assert_instr(sm3partw2))]
23796#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23797pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23798    unsafe extern "unadjusted" {
23799        #[cfg_attr(
23800            any(target_arch = "aarch64", target_arch = "arm64ec"),
23801            link_name = "llvm.aarch64.crypto.sm3partw2"
23802        )]
23803        fn _vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t;
23804    }
23805    unsafe {
23806        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
23807        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
23808        let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
23809        let ret_val: uint32x4_t = _vsm3partw2q_u32(a, b, c);
23810        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
23811    }
23812}
23813#[doc = "SM3SS1"]
23814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"]
23815#[inline]
23816#[cfg(target_endian = "little")]
23817#[target_feature(enable = "neon,sm4")]
23818#[cfg_attr(test, assert_instr(sm3ss1))]
23819#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23820pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23821    unsafe extern "unadjusted" {
23822        #[cfg_attr(
23823            any(target_arch = "aarch64", target_arch = "arm64ec"),
23824            link_name = "llvm.aarch64.crypto.sm3ss1"
23825        )]
23826        fn _vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t;
23827    }
23828    unsafe { _vsm3ss1q_u32(a, b, c) }
23829}
23830#[doc = "SM3SS1"]
23831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"]
23832#[inline]
23833#[cfg(target_endian = "big")]
23834#[target_feature(enable = "neon,sm4")]
23835#[cfg_attr(test, assert_instr(sm3ss1))]
23836#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23837pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23838    unsafe extern "unadjusted" {
23839        #[cfg_attr(
23840            any(target_arch = "aarch64", target_arch = "arm64ec"),
23841            link_name = "llvm.aarch64.crypto.sm3ss1"
23842        )]
23843        fn _vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t;
23844    }
23845    unsafe {
23846        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
23847        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
23848        let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
23849        let ret_val: uint32x4_t = _vsm3ss1q_u32(a, b, c);
23850        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
23851    }
23852}
23853#[doc = "SM3TT1A"]
23854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"]
23855#[inline]
23856#[cfg(target_endian = "little")]
23857#[target_feature(enable = "neon,sm4")]
23858#[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))]
23859#[rustc_legacy_const_generics(3)]
23860#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23861pub fn vsm3tt1aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23862    static_assert_uimm_bits!(IMM2, 2);
23863    unsafe extern "unadjusted" {
23864        #[cfg_attr(
23865            any(target_arch = "aarch64", target_arch = "arm64ec"),
23866            link_name = "llvm.aarch64.crypto.sm3tt1a"
23867        )]
23868        fn _vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t;
23869    }
23870    unsafe { _vsm3tt1aq_u32(a, b, c, IMM2 as i64) }
23871}
23872#[doc = "SM3TT1A"]
23873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"]
23874#[inline]
23875#[cfg(target_endian = "big")]
23876#[target_feature(enable = "neon,sm4")]
23877#[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))]
23878#[rustc_legacy_const_generics(3)]
23879#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23880pub fn vsm3tt1aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23881    static_assert_uimm_bits!(IMM2, 2);
23882    unsafe extern "unadjusted" {
23883        #[cfg_attr(
23884            any(target_arch = "aarch64", target_arch = "arm64ec"),
23885            link_name = "llvm.aarch64.crypto.sm3tt1a"
23886        )]
23887        fn _vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t;
23888    }
23889    unsafe {
23890        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
23891        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
23892        let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
23893        let ret_val: uint32x4_t = _vsm3tt1aq_u32(a, b, c, IMM2 as i64);
23894        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
23895    }
23896}
23897#[doc = "SM3TT1B"]
23898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"]
23899#[inline]
23900#[cfg(target_endian = "little")]
23901#[target_feature(enable = "neon,sm4")]
23902#[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))]
23903#[rustc_legacy_const_generics(3)]
23904#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23905pub fn vsm3tt1bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23906    static_assert_uimm_bits!(IMM2, 2);
23907    unsafe extern "unadjusted" {
23908        #[cfg_attr(
23909            any(target_arch = "aarch64", target_arch = "arm64ec"),
23910            link_name = "llvm.aarch64.crypto.sm3tt1b"
23911        )]
23912        fn _vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t;
23913    }
23914    unsafe { _vsm3tt1bq_u32(a, b, c, IMM2 as i64) }
23915}
23916#[doc = "SM3TT1B"]
23917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"]
23918#[inline]
23919#[cfg(target_endian = "big")]
23920#[target_feature(enable = "neon,sm4")]
23921#[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))]
23922#[rustc_legacy_const_generics(3)]
23923#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23924pub fn vsm3tt1bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23925    static_assert_uimm_bits!(IMM2, 2);
23926    unsafe extern "unadjusted" {
23927        #[cfg_attr(
23928            any(target_arch = "aarch64", target_arch = "arm64ec"),
23929            link_name = "llvm.aarch64.crypto.sm3tt1b"
23930        )]
23931        fn _vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t;
23932    }
23933    unsafe {
23934        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
23935        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
23936        let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
23937        let ret_val: uint32x4_t = _vsm3tt1bq_u32(a, b, c, IMM2 as i64);
23938        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
23939    }
23940}
23941#[doc = "SM3TT2A"]
23942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"]
23943#[inline]
23944#[cfg(target_endian = "little")]
23945#[target_feature(enable = "neon,sm4")]
23946#[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))]
23947#[rustc_legacy_const_generics(3)]
23948#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23949pub fn vsm3tt2aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23950    static_assert_uimm_bits!(IMM2, 2);
23951    unsafe extern "unadjusted" {
23952        #[cfg_attr(
23953            any(target_arch = "aarch64", target_arch = "arm64ec"),
23954            link_name = "llvm.aarch64.crypto.sm3tt2a"
23955        )]
23956        fn _vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t;
23957    }
23958    unsafe { _vsm3tt2aq_u32(a, b, c, IMM2 as i64) }
23959}
23960#[doc = "SM3TT2A"]
23961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"]
23962#[inline]
23963#[cfg(target_endian = "big")]
23964#[target_feature(enable = "neon,sm4")]
23965#[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))]
23966#[rustc_legacy_const_generics(3)]
23967#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23968pub fn vsm3tt2aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23969    static_assert_uimm_bits!(IMM2, 2);
23970    unsafe extern "unadjusted" {
23971        #[cfg_attr(
23972            any(target_arch = "aarch64", target_arch = "arm64ec"),
23973            link_name = "llvm.aarch64.crypto.sm3tt2a"
23974        )]
23975        fn _vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t;
23976    }
23977    unsafe {
23978        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
23979        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
23980        let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
23981        let ret_val: uint32x4_t = _vsm3tt2aq_u32(a, b, c, IMM2 as i64);
23982        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
23983    }
23984}
23985#[doc = "SM3TT2B"]
23986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"]
23987#[inline]
23988#[cfg(target_endian = "little")]
23989#[target_feature(enable = "neon,sm4")]
23990#[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))]
23991#[rustc_legacy_const_generics(3)]
23992#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
23993pub fn vsm3tt2bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
23994    static_assert_uimm_bits!(IMM2, 2);
23995    unsafe extern "unadjusted" {
23996        #[cfg_attr(
23997            any(target_arch = "aarch64", target_arch = "arm64ec"),
23998            link_name = "llvm.aarch64.crypto.sm3tt2b"
23999        )]
24000        fn _vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t;
24001    }
24002    unsafe { _vsm3tt2bq_u32(a, b, c, IMM2 as i64) }
24003}
24004#[doc = "SM3TT2B"]
24005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"]
24006#[inline]
24007#[cfg(target_endian = "big")]
24008#[target_feature(enable = "neon,sm4")]
24009#[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))]
24010#[rustc_legacy_const_generics(3)]
24011#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
24012pub fn vsm3tt2bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
24013    static_assert_uimm_bits!(IMM2, 2);
24014    unsafe extern "unadjusted" {
24015        #[cfg_attr(
24016            any(target_arch = "aarch64", target_arch = "arm64ec"),
24017            link_name = "llvm.aarch64.crypto.sm3tt2b"
24018        )]
24019        fn _vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t;
24020    }
24021    unsafe {
24022        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
24023        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
24024        let c: uint32x4_t = simd_shuffle!(c, c, [3, 2, 1, 0]);
24025        let ret_val: uint32x4_t = _vsm3tt2bq_u32(a, b, c, IMM2 as i64);
24026        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
24027    }
24028}
24029#[doc = "SM4 key"]
24030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"]
24031#[inline]
24032#[cfg(target_endian = "little")]
24033#[target_feature(enable = "neon,sm4")]
24034#[cfg_attr(test, assert_instr(sm4ekey))]
24035#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
24036pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
24037    unsafe extern "unadjusted" {
24038        #[cfg_attr(
24039            any(target_arch = "aarch64", target_arch = "arm64ec"),
24040            link_name = "llvm.aarch64.crypto.sm4ekey"
24041        )]
24042        fn _vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
24043    }
24044    unsafe { _vsm4ekeyq_u32(a, b) }
24045}
24046#[doc = "SM4 key"]
24047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"]
24048#[inline]
24049#[cfg(target_endian = "big")]
24050#[target_feature(enable = "neon,sm4")]
24051#[cfg_attr(test, assert_instr(sm4ekey))]
24052#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
24053pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
24054    unsafe extern "unadjusted" {
24055        #[cfg_attr(
24056            any(target_arch = "aarch64", target_arch = "arm64ec"),
24057            link_name = "llvm.aarch64.crypto.sm4ekey"
24058        )]
24059        fn _vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
24060    }
24061    unsafe {
24062        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
24063        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
24064        let ret_val: uint32x4_t = _vsm4ekeyq_u32(a, b);
24065        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
24066    }
24067}
24068#[doc = "SM4 encode"]
24069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"]
24070#[inline]
24071#[cfg(target_endian = "little")]
24072#[target_feature(enable = "neon,sm4")]
24073#[cfg_attr(test, assert_instr(sm4e))]
24074#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
24075pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
24076    unsafe extern "unadjusted" {
24077        #[cfg_attr(
24078            any(target_arch = "aarch64", target_arch = "arm64ec"),
24079            link_name = "llvm.aarch64.crypto.sm4e"
24080        )]
24081        fn _vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
24082    }
24083    unsafe { _vsm4eq_u32(a, b) }
24084}
24085#[doc = "SM4 encode"]
24086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"]
24087#[inline]
24088#[cfg(target_endian = "big")]
24089#[target_feature(enable = "neon,sm4")]
24090#[cfg_attr(test, assert_instr(sm4e))]
24091#[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
24092pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
24093    unsafe extern "unadjusted" {
24094        #[cfg_attr(
24095            any(target_arch = "aarch64", target_arch = "arm64ec"),
24096            link_name = "llvm.aarch64.crypto.sm4e"
24097        )]
24098        fn _vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
24099    }
24100    unsafe {
24101        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
24102        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
24103        let ret_val: uint32x4_t = _vsm4eq_u32(a, b);
24104        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
24105    }
24106}
24107#[doc = "Unsigned saturating Accumulate of Signed value."]
24108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u8)"]
24109#[inline]
24110#[target_feature(enable = "neon")]
24111#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24112#[cfg_attr(test, assert_instr(usqadd))]
24113pub fn vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
24114    unsafe extern "unadjusted" {
24115        #[cfg_attr(
24116            any(target_arch = "aarch64", target_arch = "arm64ec"),
24117            link_name = "llvm.aarch64.neon.usqadd.v8i8"
24118        )]
24119        fn _vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
24120    }
24121    unsafe { _vsqadd_u8(a, b) }
24122}
24123#[doc = "Unsigned saturating Accumulate of Signed value."]
24124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u8)"]
24125#[inline]
24126#[target_feature(enable = "neon")]
24127#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24128#[cfg_attr(test, assert_instr(usqadd))]
24129pub fn vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
24130    unsafe extern "unadjusted" {
24131        #[cfg_attr(
24132            any(target_arch = "aarch64", target_arch = "arm64ec"),
24133            link_name = "llvm.aarch64.neon.usqadd.v16i8"
24134        )]
24135        fn _vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
24136    }
24137    unsafe { _vsqaddq_u8(a, b) }
24138}
24139#[doc = "Unsigned saturating Accumulate of Signed value."]
24140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u16)"]
24141#[inline]
24142#[target_feature(enable = "neon")]
24143#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24144#[cfg_attr(test, assert_instr(usqadd))]
24145pub fn vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
24146    unsafe extern "unadjusted" {
24147        #[cfg_attr(
24148            any(target_arch = "aarch64", target_arch = "arm64ec"),
24149            link_name = "llvm.aarch64.neon.usqadd.v4i16"
24150        )]
24151        fn _vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
24152    }
24153    unsafe { _vsqadd_u16(a, b) }
24154}
24155#[doc = "Unsigned saturating Accumulate of Signed value."]
24156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u16)"]
24157#[inline]
24158#[target_feature(enable = "neon")]
24159#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24160#[cfg_attr(test, assert_instr(usqadd))]
24161pub fn vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
24162    unsafe extern "unadjusted" {
24163        #[cfg_attr(
24164            any(target_arch = "aarch64", target_arch = "arm64ec"),
24165            link_name = "llvm.aarch64.neon.usqadd.v8i16"
24166        )]
24167        fn _vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
24168    }
24169    unsafe { _vsqaddq_u16(a, b) }
24170}
24171#[doc = "Unsigned saturating Accumulate of Signed value."]
24172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u32)"]
24173#[inline]
24174#[target_feature(enable = "neon")]
24175#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24176#[cfg_attr(test, assert_instr(usqadd))]
24177pub fn vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
24178    unsafe extern "unadjusted" {
24179        #[cfg_attr(
24180            any(target_arch = "aarch64", target_arch = "arm64ec"),
24181            link_name = "llvm.aarch64.neon.usqadd.v2i32"
24182        )]
24183        fn _vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
24184    }
24185    unsafe { _vsqadd_u32(a, b) }
24186}
24187#[doc = "Unsigned saturating Accumulate of Signed value."]
24188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u32)"]
24189#[inline]
24190#[target_feature(enable = "neon")]
24191#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24192#[cfg_attr(test, assert_instr(usqadd))]
24193pub fn vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
24194    unsafe extern "unadjusted" {
24195        #[cfg_attr(
24196            any(target_arch = "aarch64", target_arch = "arm64ec"),
24197            link_name = "llvm.aarch64.neon.usqadd.v4i32"
24198        )]
24199        fn _vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
24200    }
24201    unsafe { _vsqaddq_u32(a, b) }
24202}
24203#[doc = "Unsigned saturating Accumulate of Signed value."]
24204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u64)"]
24205#[inline]
24206#[target_feature(enable = "neon")]
24207#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24208#[cfg_attr(test, assert_instr(usqadd))]
24209pub fn vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
24210    unsafe extern "unadjusted" {
24211        #[cfg_attr(
24212            any(target_arch = "aarch64", target_arch = "arm64ec"),
24213            link_name = "llvm.aarch64.neon.usqadd.v1i64"
24214        )]
24215        fn _vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
24216    }
24217    unsafe { _vsqadd_u64(a, b) }
24218}
24219#[doc = "Unsigned saturating Accumulate of Signed value."]
24220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u64)"]
24221#[inline]
24222#[target_feature(enable = "neon")]
24223#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24224#[cfg_attr(test, assert_instr(usqadd))]
24225pub fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
24226    unsafe extern "unadjusted" {
24227        #[cfg_attr(
24228            any(target_arch = "aarch64", target_arch = "arm64ec"),
24229            link_name = "llvm.aarch64.neon.usqadd.v2i64"
24230        )]
24231        fn _vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
24232    }
24233    unsafe { _vsqaddq_u64(a, b) }
24234}
24235#[doc = "Unsigned saturating accumulate of signed value"]
24236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)"]
24237#[inline]
24238#[target_feature(enable = "neon")]
24239#[cfg_attr(test, assert_instr(usqadd))]
24240#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24241pub fn vsqaddb_u8(a: u8, b: i8) -> u8 {
24242    vget_lane_u8::<0>(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)))
24243}
24244#[doc = "Unsigned saturating accumulate of signed value"]
24245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"]
24246#[inline]
24247#[target_feature(enable = "neon")]
24248#[cfg_attr(test, assert_instr(usqadd))]
24249#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24250pub fn vsqaddh_u16(a: u16, b: i16) -> u16 {
24251    vget_lane_u16::<0>(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)))
24252}
24253#[doc = "Unsigned saturating accumulate of signed value"]
24254#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"]
24255#[inline]
24256#[target_feature(enable = "neon")]
24257#[cfg_attr(test, assert_instr(usqadd))]
24258#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24259pub fn vsqaddd_u64(a: u64, b: i64) -> u64 {
24260    unsafe extern "unadjusted" {
24261        #[cfg_attr(
24262            any(target_arch = "aarch64", target_arch = "arm64ec"),
24263            link_name = "llvm.aarch64.neon.usqadd.i64"
24264        )]
24265        fn _vsqaddd_u64(a: u64, b: i64) -> u64;
24266    }
24267    unsafe { _vsqaddd_u64(a, b) }
24268}
24269#[doc = "Unsigned saturating accumulate of signed value"]
24270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)"]
24271#[inline]
24272#[target_feature(enable = "neon")]
24273#[cfg_attr(test, assert_instr(usqadd))]
24274#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24275pub fn vsqadds_u32(a: u32, b: i32) -> u32 {
24276    unsafe extern "unadjusted" {
24277        #[cfg_attr(
24278            any(target_arch = "aarch64", target_arch = "arm64ec"),
24279            link_name = "llvm.aarch64.neon.usqadd.i32"
24280        )]
24281        fn _vsqadds_u32(a: u32, b: i32) -> u32;
24282    }
24283    unsafe { _vsqadds_u32(a, b) }
24284}
24285#[doc = "Calculates the square root of each lane."]
24286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f16)"]
24287#[inline]
24288#[cfg_attr(test, assert_instr(fsqrt))]
24289#[target_feature(enable = "neon,fp16")]
24290#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
24291#[cfg(not(target_arch = "arm64ec"))]
24292pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t {
24293    unsafe { simd_fsqrt(a) }
24294}
24295#[doc = "Calculates the square root of each lane."]
24296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f16)"]
24297#[inline]
24298#[cfg_attr(test, assert_instr(fsqrt))]
24299#[target_feature(enable = "neon,fp16")]
24300#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
24301#[cfg(not(target_arch = "arm64ec"))]
24302pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t {
24303    unsafe { simd_fsqrt(a) }
24304}
24305#[doc = "Calculates the square root of each lane."]
24306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)"]
24307#[inline]
24308#[target_feature(enable = "neon")]
24309#[cfg_attr(test, assert_instr(fsqrt))]
24310#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24311pub fn vsqrt_f32(a: float32x2_t) -> float32x2_t {
24312    unsafe { simd_fsqrt(a) }
24313}
24314#[doc = "Calculates the square root of each lane."]
24315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)"]
24316#[inline]
24317#[target_feature(enable = "neon")]
24318#[cfg_attr(test, assert_instr(fsqrt))]
24319#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24320pub fn vsqrtq_f32(a: float32x4_t) -> float32x4_t {
24321    unsafe { simd_fsqrt(a) }
24322}
24323#[doc = "Calculates the square root of each lane."]
24324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)"]
24325#[inline]
24326#[target_feature(enable = "neon")]
24327#[cfg_attr(test, assert_instr(fsqrt))]
24328#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24329pub fn vsqrt_f64(a: float64x1_t) -> float64x1_t {
24330    unsafe { simd_fsqrt(a) }
24331}
24332#[doc = "Calculates the square root of each lane."]
24333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)"]
24334#[inline]
24335#[target_feature(enable = "neon")]
24336#[cfg_attr(test, assert_instr(fsqrt))]
24337#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24338pub fn vsqrtq_f64(a: float64x2_t) -> float64x2_t {
24339    unsafe { simd_fsqrt(a) }
24340}
24341#[doc = "Floating-point round to integral, using current rounding mode"]
24342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrth_f16)"]
24343#[inline]
24344#[target_feature(enable = "neon,fp16")]
24345#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24346#[cfg(not(target_arch = "arm64ec"))]
24347#[cfg_attr(test, assert_instr(fsqrt))]
24348pub fn vsqrth_f16(a: f16) -> f16 {
24349    sqrtf16(a)
24350}
24351#[doc = "Shift Right and Insert (immediate)"]
24352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
24353#[inline]
24354#[target_feature(enable = "neon")]
24355#[cfg_attr(test, assert_instr(sri, N = 1))]
24356#[rustc_legacy_const_generics(2)]
24357#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24358pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
24359    static_assert!(N >= 1 && N <= 8);
24360    unsafe { super::shift_right_and_insert!(u8, 8, N, a, b) }
24361}
24362#[doc = "Shift Right and Insert (immediate)"]
24363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
24364#[inline]
24365#[target_feature(enable = "neon")]
24366#[cfg_attr(test, assert_instr(sri, N = 1))]
24367#[rustc_legacy_const_generics(2)]
24368#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24369pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
24370    static_assert!(N >= 1 && N <= 8);
24371    unsafe { super::shift_right_and_insert!(u8, 16, N, a, b) }
24372}
24373#[doc = "Shift Right and Insert (immediate)"]
24374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
24375#[inline]
24376#[target_feature(enable = "neon")]
24377#[cfg_attr(test, assert_instr(sri, N = 1))]
24378#[rustc_legacy_const_generics(2)]
24379#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24380pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
24381    static_assert!(N >= 1 && N <= 16);
24382    unsafe { super::shift_right_and_insert!(u16, 4, N, a, b) }
24383}
24384#[doc = "Shift Right and Insert (immediate)"]
24385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
24386#[inline]
24387#[target_feature(enable = "neon")]
24388#[cfg_attr(test, assert_instr(sri, N = 1))]
24389#[rustc_legacy_const_generics(2)]
24390#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24391pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
24392    static_assert!(N >= 1 && N <= 16);
24393    unsafe { super::shift_right_and_insert!(u16, 8, N, a, b) }
24394}
24395#[doc = "Shift Right and Insert (immediate)"]
24396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
24397#[inline]
24398#[target_feature(enable = "neon")]
24399#[cfg_attr(test, assert_instr(sri, N = 1))]
24400#[rustc_legacy_const_generics(2)]
24401#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24402pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
24403    static_assert!(N >= 1 && N <= 32);
24404    unsafe { super::shift_right_and_insert!(u32, 2, N, a, b) }
24405}
24406#[doc = "Shift Right and Insert (immediate)"]
24407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
24408#[inline]
24409#[target_feature(enable = "neon")]
24410#[cfg_attr(test, assert_instr(sri, N = 1))]
24411#[rustc_legacy_const_generics(2)]
24412#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24413pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
24414    static_assert!(N >= 1 && N <= 32);
24415    unsafe { super::shift_right_and_insert!(u32, 4, N, a, b) }
24416}
24417#[doc = "Shift Right and Insert (immediate)"]
24418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
24419#[inline]
24420#[target_feature(enable = "neon")]
24421#[cfg_attr(test, assert_instr(sri, N = 1))]
24422#[rustc_legacy_const_generics(2)]
24423#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24424pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
24425    static_assert!(N >= 1 && N <= 64);
24426    unsafe { super::shift_right_and_insert!(u64, 1, N, a, b) }
24427}
24428#[doc = "Shift Right and Insert (immediate)"]
24429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
24430#[inline]
24431#[target_feature(enable = "neon")]
24432#[cfg_attr(test, assert_instr(sri, N = 1))]
24433#[rustc_legacy_const_generics(2)]
24434#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24435pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
24436    static_assert!(N >= 1 && N <= 64);
24437    unsafe { super::shift_right_and_insert!(u64, 2, N, a, b) }
24438}
24439#[doc = "Shift Right and Insert (immediate)"]
24440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
24441#[inline]
24442#[target_feature(enable = "neon")]
24443#[cfg_attr(test, assert_instr(sri, N = 1))]
24444#[rustc_legacy_const_generics(2)]
24445#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24446pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
24447    static_assert!(N >= 1 && N <= 8);
24448    unsafe { transmute(vsri_n_s8::<N>(transmute(a), transmute(b))) }
24449}
24450#[doc = "Shift Right and Insert (immediate)"]
24451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
24452#[inline]
24453#[target_feature(enable = "neon")]
24454#[cfg_attr(test, assert_instr(sri, N = 1))]
24455#[rustc_legacy_const_generics(2)]
24456#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24457pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
24458    static_assert!(N >= 1 && N <= 8);
24459    unsafe { transmute(vsriq_n_s8::<N>(transmute(a), transmute(b))) }
24460}
24461#[doc = "Shift Right and Insert (immediate)"]
24462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
24463#[inline]
24464#[target_feature(enable = "neon")]
24465#[cfg_attr(test, assert_instr(sri, N = 1))]
24466#[rustc_legacy_const_generics(2)]
24467#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24468pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
24469    static_assert!(N >= 1 && N <= 16);
24470    unsafe { transmute(vsri_n_s16::<N>(transmute(a), transmute(b))) }
24471}
24472#[doc = "Shift Right and Insert (immediate)"]
24473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
24474#[inline]
24475#[target_feature(enable = "neon")]
24476#[cfg_attr(test, assert_instr(sri, N = 1))]
24477#[rustc_legacy_const_generics(2)]
24478#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24479pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
24480    static_assert!(N >= 1 && N <= 16);
24481    unsafe { transmute(vsriq_n_s16::<N>(transmute(a), transmute(b))) }
24482}
24483#[doc = "Shift Right and Insert (immediate)"]
24484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
24485#[inline]
24486#[target_feature(enable = "neon")]
24487#[cfg_attr(test, assert_instr(sri, N = 1))]
24488#[rustc_legacy_const_generics(2)]
24489#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24490pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
24491    static_assert!(N >= 1 && N <= 32);
24492    unsafe { transmute(vsri_n_s32::<N>(transmute(a), transmute(b))) }
24493}
24494#[doc = "Shift Right and Insert (immediate)"]
24495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
24496#[inline]
24497#[target_feature(enable = "neon")]
24498#[cfg_attr(test, assert_instr(sri, N = 1))]
24499#[rustc_legacy_const_generics(2)]
24500#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24501pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
24502    static_assert!(N >= 1 && N <= 32);
24503    unsafe { transmute(vsriq_n_s32::<N>(transmute(a), transmute(b))) }
24504}
24505#[doc = "Shift Right and Insert (immediate)"]
24506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
24507#[inline]
24508#[target_feature(enable = "neon")]
24509#[cfg_attr(test, assert_instr(sri, N = 1))]
24510#[rustc_legacy_const_generics(2)]
24511#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24512pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
24513    static_assert!(N >= 1 && N <= 64);
24514    unsafe { transmute(vsri_n_s64::<N>(transmute(a), transmute(b))) }
24515}
24516#[doc = "Shift Right and Insert (immediate)"]
24517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
24518#[inline]
24519#[target_feature(enable = "neon")]
24520#[cfg_attr(test, assert_instr(sri, N = 1))]
24521#[rustc_legacy_const_generics(2)]
24522#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24523pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
24524    static_assert!(N >= 1 && N <= 64);
24525    unsafe { transmute(vsriq_n_s64::<N>(transmute(a), transmute(b))) }
24526}
24527#[doc = "Shift Right and Insert (immediate)"]
24528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
24529#[inline]
24530#[target_feature(enable = "neon")]
24531#[cfg_attr(test, assert_instr(sri, N = 1))]
24532#[rustc_legacy_const_generics(2)]
24533#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24534pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
24535    static_assert!(N >= 1 && N <= 8);
24536    unsafe { transmute(vsri_n_s8::<N>(transmute(a), transmute(b))) }
24537}
24538#[doc = "Shift Right and Insert (immediate)"]
24539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
24540#[inline]
24541#[target_feature(enable = "neon")]
24542#[cfg_attr(test, assert_instr(sri, N = 1))]
24543#[rustc_legacy_const_generics(2)]
24544#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24545pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
24546    static_assert!(N >= 1 && N <= 8);
24547    unsafe { transmute(vsriq_n_s8::<N>(transmute(a), transmute(b))) }
24548}
24549#[doc = "Shift Right and Insert (immediate)"]
24550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
24551#[inline]
24552#[target_feature(enable = "neon")]
24553#[cfg_attr(test, assert_instr(sri, N = 1))]
24554#[rustc_legacy_const_generics(2)]
24555#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24556pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
24557    static_assert!(N >= 1 && N <= 16);
24558    unsafe { transmute(vsri_n_s16::<N>(transmute(a), transmute(b))) }
24559}
24560#[doc = "Shift Right and Insert (immediate)"]
24561#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
24562#[inline]
24563#[target_feature(enable = "neon")]
24564#[cfg_attr(test, assert_instr(sri, N = 1))]
24565#[rustc_legacy_const_generics(2)]
24566#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24567pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
24568    static_assert!(N >= 1 && N <= 16);
24569    unsafe { transmute(vsriq_n_s16::<N>(transmute(a), transmute(b))) }
24570}
24571#[doc = "Shift Right and Insert (immediate)"]
24572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p64)"]
24573#[inline]
24574#[target_feature(enable = "neon,aes")]
24575#[cfg_attr(test, assert_instr(sri, N = 1))]
24576#[rustc_legacy_const_generics(2)]
24577#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24578pub fn vsri_n_p64<const N: i32>(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
24579    static_assert!(N >= 1 && N <= 64);
24580    unsafe { transmute(vsri_n_s64::<N>(transmute(a), transmute(b))) }
24581}
24582#[doc = "Shift Right and Insert (immediate)"]
24583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p64)"]
24584#[inline]
24585#[target_feature(enable = "neon,aes")]
24586#[cfg_attr(test, assert_instr(sri, N = 1))]
24587#[rustc_legacy_const_generics(2)]
24588#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24589pub fn vsriq_n_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
24590    static_assert!(N >= 1 && N <= 64);
24591    unsafe { transmute(vsriq_n_s64::<N>(transmute(a), transmute(b))) }
24592}
24593#[doc = "Shift right and insert"]
24594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64)"]
24595#[inline]
24596#[target_feature(enable = "neon")]
24597#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24598#[rustc_legacy_const_generics(2)]
24599#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))]
24600pub fn vsrid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
24601    static_assert!(N >= 1 && N <= 64);
24602    unsafe { transmute(vsri_n_s64::<N>(transmute(a), transmute(b))) }
24603}
24604#[doc = "Shift right and insert"]
24605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64)"]
24606#[inline]
24607#[target_feature(enable = "neon")]
24608#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24609#[rustc_legacy_const_generics(2)]
24610#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))]
24611pub fn vsrid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
24612    static_assert!(N >= 1 && N <= 64);
24613    unsafe { transmute(vsri_n_u64::<N>(transmute(a), transmute(b))) }
24614}
24615#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
24617#[doc = "## Safety"]
24618#[doc = "  * Neon intrinsic unsafe"]
24619#[inline]
24620#[target_feature(enable = "neon,fp16")]
24621#[cfg_attr(test, assert_instr(str))]
24622#[allow(clippy::cast_ptr_alignment)]
24623#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24624#[cfg(not(target_arch = "arm64ec"))]
24625pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
24626    crate::ptr::write_unaligned(ptr.cast(), a)
24627}
24628#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
24630#[doc = "## Safety"]
24631#[doc = "  * Neon intrinsic unsafe"]
24632#[inline]
24633#[target_feature(enable = "neon,fp16")]
24634#[cfg_attr(test, assert_instr(str))]
24635#[allow(clippy::cast_ptr_alignment)]
24636#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24637#[cfg(not(target_arch = "arm64ec"))]
24638pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
24639    crate::ptr::write_unaligned(ptr.cast(), a)
24640}
24641#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
24643#[doc = "## Safety"]
24644#[doc = "  * Neon intrinsic unsafe"]
24645#[inline]
24646#[target_feature(enable = "neon")]
24647#[cfg_attr(test, assert_instr(str))]
24648#[allow(clippy::cast_ptr_alignment)]
24649#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24650pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
24651    crate::ptr::write_unaligned(ptr.cast(), a)
24652}
24653#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
24655#[doc = "## Safety"]
24656#[doc = "  * Neon intrinsic unsafe"]
24657#[inline]
24658#[target_feature(enable = "neon")]
24659#[cfg_attr(test, assert_instr(str))]
24660#[allow(clippy::cast_ptr_alignment)]
24661#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24662pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
24663    crate::ptr::write_unaligned(ptr.cast(), a)
24664}
24665#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"]
24667#[doc = "## Safety"]
24668#[doc = "  * Neon intrinsic unsafe"]
24669#[inline]
24670#[target_feature(enable = "neon")]
24671#[cfg_attr(test, assert_instr(str))]
24672#[allow(clippy::cast_ptr_alignment)]
24673#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24674pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) {
24675    crate::ptr::write_unaligned(ptr.cast(), a)
24676}
24677#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"]
24679#[doc = "## Safety"]
24680#[doc = "  * Neon intrinsic unsafe"]
24681#[inline]
24682#[target_feature(enable = "neon")]
24683#[cfg_attr(test, assert_instr(str))]
24684#[allow(clippy::cast_ptr_alignment)]
24685#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24686pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) {
24687    crate::ptr::write_unaligned(ptr.cast(), a)
24688}
24689#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
24691#[doc = "## Safety"]
24692#[doc = "  * Neon intrinsic unsafe"]
24693#[inline]
24694#[target_feature(enable = "neon")]
24695#[cfg_attr(test, assert_instr(str))]
24696#[allow(clippy::cast_ptr_alignment)]
24697#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24698pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
24699    crate::ptr::write_unaligned(ptr.cast(), a)
24700}
24701#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
24703#[doc = "## Safety"]
24704#[doc = "  * Neon intrinsic unsafe"]
24705#[inline]
24706#[target_feature(enable = "neon")]
24707#[cfg_attr(test, assert_instr(str))]
24708#[allow(clippy::cast_ptr_alignment)]
24709#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24710pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
24711    crate::ptr::write_unaligned(ptr.cast(), a)
24712}
24713#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
24715#[doc = "## Safety"]
24716#[doc = "  * Neon intrinsic unsafe"]
24717#[inline]
24718#[target_feature(enable = "neon")]
24719#[cfg_attr(test, assert_instr(str))]
24720#[allow(clippy::cast_ptr_alignment)]
24721#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24722pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
24723    crate::ptr::write_unaligned(ptr.cast(), a)
24724}
24725#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
24727#[doc = "## Safety"]
24728#[doc = "  * Neon intrinsic unsafe"]
24729#[inline]
24730#[target_feature(enable = "neon")]
24731#[cfg_attr(test, assert_instr(str))]
24732#[allow(clippy::cast_ptr_alignment)]
24733#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24734pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
24735    crate::ptr::write_unaligned(ptr.cast(), a)
24736}
24737#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
24739#[doc = "## Safety"]
24740#[doc = "  * Neon intrinsic unsafe"]
24741#[inline]
24742#[target_feature(enable = "neon")]
24743#[cfg_attr(test, assert_instr(str))]
24744#[allow(clippy::cast_ptr_alignment)]
24745#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24746pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
24747    crate::ptr::write_unaligned(ptr.cast(), a)
24748}
24749#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
24751#[doc = "## Safety"]
24752#[doc = "  * Neon intrinsic unsafe"]
24753#[inline]
24754#[target_feature(enable = "neon")]
24755#[cfg_attr(test, assert_instr(str))]
24756#[allow(clippy::cast_ptr_alignment)]
24757#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24758pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
24759    crate::ptr::write_unaligned(ptr.cast(), a)
24760}
24761#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
24763#[doc = "## Safety"]
24764#[doc = "  * Neon intrinsic unsafe"]
24765#[inline]
24766#[target_feature(enable = "neon")]
24767#[cfg_attr(test, assert_instr(str))]
24768#[allow(clippy::cast_ptr_alignment)]
24769#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24770pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
24771    crate::ptr::write_unaligned(ptr.cast(), a)
24772}
24773#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
24775#[doc = "## Safety"]
24776#[doc = "  * Neon intrinsic unsafe"]
24777#[inline]
24778#[target_feature(enable = "neon")]
24779#[cfg_attr(test, assert_instr(str))]
24780#[allow(clippy::cast_ptr_alignment)]
24781#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24782pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
24783    crate::ptr::write_unaligned(ptr.cast(), a)
24784}
24785#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
24787#[doc = "## Safety"]
24788#[doc = "  * Neon intrinsic unsafe"]
24789#[inline]
24790#[target_feature(enable = "neon")]
24791#[cfg_attr(test, assert_instr(str))]
24792#[allow(clippy::cast_ptr_alignment)]
24793#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24794pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
24795    crate::ptr::write_unaligned(ptr.cast(), a)
24796}
24797#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
24799#[doc = "## Safety"]
24800#[doc = "  * Neon intrinsic unsafe"]
24801#[inline]
24802#[target_feature(enable = "neon")]
24803#[cfg_attr(test, assert_instr(str))]
24804#[allow(clippy::cast_ptr_alignment)]
24805#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24806pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
24807    crate::ptr::write_unaligned(ptr.cast(), a)
24808}
24809#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
24811#[doc = "## Safety"]
24812#[doc = "  * Neon intrinsic unsafe"]
24813#[inline]
24814#[target_feature(enable = "neon")]
24815#[cfg_attr(test, assert_instr(str))]
24816#[allow(clippy::cast_ptr_alignment)]
24817#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24818pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
24819    crate::ptr::write_unaligned(ptr.cast(), a)
24820}
24821#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
24823#[doc = "## Safety"]
24824#[doc = "  * Neon intrinsic unsafe"]
24825#[inline]
24826#[target_feature(enable = "neon")]
24827#[cfg_attr(test, assert_instr(str))]
24828#[allow(clippy::cast_ptr_alignment)]
24829#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24830pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
24831    crate::ptr::write_unaligned(ptr.cast(), a)
24832}
24833#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
24835#[doc = "## Safety"]
24836#[doc = "  * Neon intrinsic unsafe"]
24837#[inline]
24838#[target_feature(enable = "neon")]
24839#[cfg_attr(test, assert_instr(str))]
24840#[allow(clippy::cast_ptr_alignment)]
24841#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24842pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
24843    crate::ptr::write_unaligned(ptr.cast(), a)
24844}
24845#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
24847#[doc = "## Safety"]
24848#[doc = "  * Neon intrinsic unsafe"]
24849#[inline]
24850#[target_feature(enable = "neon")]
24851#[cfg_attr(test, assert_instr(str))]
24852#[allow(clippy::cast_ptr_alignment)]
24853#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24854pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
24855    crate::ptr::write_unaligned(ptr.cast(), a)
24856}
24857#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
24859#[doc = "## Safety"]
24860#[doc = "  * Neon intrinsic unsafe"]
24861#[inline]
24862#[target_feature(enable = "neon")]
24863#[cfg_attr(test, assert_instr(str))]
24864#[allow(clippy::cast_ptr_alignment)]
24865#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24866pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
24867    crate::ptr::write_unaligned(ptr.cast(), a)
24868}
24869#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
24871#[doc = "## Safety"]
24872#[doc = "  * Neon intrinsic unsafe"]
24873#[inline]
24874#[target_feature(enable = "neon")]
24875#[cfg_attr(test, assert_instr(str))]
24876#[allow(clippy::cast_ptr_alignment)]
24877#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24878pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
24879    crate::ptr::write_unaligned(ptr.cast(), a)
24880}
24881#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
24883#[doc = "## Safety"]
24884#[doc = "  * Neon intrinsic unsafe"]
24885#[inline]
24886#[target_feature(enable = "neon")]
24887#[cfg_attr(test, assert_instr(str))]
24888#[allow(clippy::cast_ptr_alignment)]
24889#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24890pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
24891    crate::ptr::write_unaligned(ptr.cast(), a)
24892}
24893#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
24895#[doc = "## Safety"]
24896#[doc = "  * Neon intrinsic unsafe"]
24897#[inline]
24898#[target_feature(enable = "neon")]
24899#[cfg_attr(test, assert_instr(str))]
24900#[allow(clippy::cast_ptr_alignment)]
24901#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24902pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
24903    crate::ptr::write_unaligned(ptr.cast(), a)
24904}
24905#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
24907#[doc = "## Safety"]
24908#[doc = "  * Neon intrinsic unsafe"]
24909#[inline]
24910#[target_feature(enable = "neon")]
24911#[cfg_attr(test, assert_instr(str))]
24912#[allow(clippy::cast_ptr_alignment)]
24913#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24914pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
24915    crate::ptr::write_unaligned(ptr.cast(), a)
24916}
24917#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
24919#[doc = "## Safety"]
24920#[doc = "  * Neon intrinsic unsafe"]
24921#[inline]
24922#[target_feature(enable = "neon")]
24923#[cfg_attr(test, assert_instr(str))]
24924#[allow(clippy::cast_ptr_alignment)]
24925#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24926pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
24927    crate::ptr::write_unaligned(ptr.cast(), a)
24928}
24929#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
24931#[doc = "## Safety"]
24932#[doc = "  * Neon intrinsic unsafe"]
24933#[inline]
24934#[target_feature(enable = "neon,aes")]
24935#[cfg_attr(test, assert_instr(str))]
24936#[allow(clippy::cast_ptr_alignment)]
24937#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24938pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
24939    crate::ptr::write_unaligned(ptr.cast(), a)
24940}
24941#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
24942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
24943#[doc = "## Safety"]
24944#[doc = "  * Neon intrinsic unsafe"]
24945#[inline]
24946#[target_feature(enable = "neon,aes")]
24947#[cfg_attr(test, assert_instr(str))]
24948#[allow(clippy::cast_ptr_alignment)]
24949#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24950pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
24951    crate::ptr::write_unaligned(ptr.cast(), a)
24952}
24953#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
24954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"]
24955#[doc = "## Safety"]
24956#[doc = "  * Neon intrinsic unsafe"]
24957#[inline]
24958#[target_feature(enable = "neon")]
24959#[cfg_attr(test, assert_instr(st1))]
24960#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24961pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) {
24962    unsafe extern "unadjusted" {
24963        #[cfg_attr(
24964            any(target_arch = "aarch64", target_arch = "arm64ec"),
24965            link_name = "llvm.aarch64.neon.st1x2.v1f64.p0"
24966        )]
24967        fn _vst1_f64_x2(a: float64x1_t, b: float64x1_t, ptr: *mut f64);
24968    }
24969    _vst1_f64_x2(b.0, b.1, a)
24970}
24971#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
24972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"]
24973#[doc = "## Safety"]
24974#[doc = "  * Neon intrinsic unsafe"]
24975#[inline]
24976#[target_feature(enable = "neon")]
24977#[cfg_attr(test, assert_instr(st1))]
24978#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24979pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) {
24980    unsafe extern "unadjusted" {
24981        #[cfg_attr(
24982            any(target_arch = "aarch64", target_arch = "arm64ec"),
24983            link_name = "llvm.aarch64.neon.st1x2.v2f64.p0"
24984        )]
24985        fn _vst1q_f64_x2(a: float64x2_t, b: float64x2_t, ptr: *mut f64);
24986    }
24987    _vst1q_f64_x2(b.0, b.1, a)
24988}
24989#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
24990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"]
24991#[doc = "## Safety"]
24992#[doc = "  * Neon intrinsic unsafe"]
24993#[inline]
24994#[target_feature(enable = "neon")]
24995#[cfg_attr(test, assert_instr(st1))]
24996#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24997pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) {
24998    unsafe extern "unadjusted" {
24999        #[cfg_attr(
25000            any(target_arch = "aarch64", target_arch = "arm64ec"),
25001            link_name = "llvm.aarch64.neon.st1x3.v1f64.p0"
25002        )]
25003        fn _vst1_f64_x3(a: float64x1_t, b: float64x1_t, c: float64x1_t, ptr: *mut f64);
25004    }
25005    _vst1_f64_x3(b.0, b.1, b.2, a)
25006}
25007#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
25008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"]
25009#[doc = "## Safety"]
25010#[doc = "  * Neon intrinsic unsafe"]
25011#[inline]
25012#[target_feature(enable = "neon")]
25013#[cfg_attr(test, assert_instr(st1))]
25014#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25015pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) {
25016    unsafe extern "unadjusted" {
25017        #[cfg_attr(
25018            any(target_arch = "aarch64", target_arch = "arm64ec"),
25019            link_name = "llvm.aarch64.neon.st1x3.v2f64.p0"
25020        )]
25021        fn _vst1q_f64_x3(a: float64x2_t, b: float64x2_t, c: float64x2_t, ptr: *mut f64);
25022    }
25023    _vst1q_f64_x3(b.0, b.1, b.2, a)
25024}
25025#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
25026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"]
25027#[doc = "## Safety"]
25028#[doc = "  * Neon intrinsic unsafe"]
25029#[inline]
25030#[target_feature(enable = "neon")]
25031#[cfg_attr(test, assert_instr(st1))]
25032#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25033pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) {
25034    unsafe extern "unadjusted" {
25035        #[cfg_attr(
25036            any(target_arch = "aarch64", target_arch = "arm64ec"),
25037            link_name = "llvm.aarch64.neon.st1x4.v1f64.p0"
25038        )]
25039        fn _vst1_f64_x4(
25040            a: float64x1_t,
25041            b: float64x1_t,
25042            c: float64x1_t,
25043            d: float64x1_t,
25044            ptr: *mut f64,
25045        );
25046    }
25047    _vst1_f64_x4(b.0, b.1, b.2, b.3, a)
25048}
25049#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
25050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"]
25051#[doc = "## Safety"]
25052#[doc = "  * Neon intrinsic unsafe"]
25053#[inline]
25054#[target_feature(enable = "neon")]
25055#[cfg_attr(test, assert_instr(st1))]
25056#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25057pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) {
25058    unsafe extern "unadjusted" {
25059        #[cfg_attr(
25060            any(target_arch = "aarch64", target_arch = "arm64ec"),
25061            link_name = "llvm.aarch64.neon.st1x4.v2f64.p0"
25062        )]
25063        fn _vst1q_f64_x4(
25064            a: float64x2_t,
25065            b: float64x2_t,
25066            c: float64x2_t,
25067            d: float64x2_t,
25068            ptr: *mut f64,
25069        );
25070    }
25071    _vst1q_f64_x4(b.0, b.1, b.2, b.3, a)
25072}
25073#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
25074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"]
25075#[doc = "## Safety"]
25076#[doc = "  * Neon intrinsic unsafe"]
25077#[inline]
25078#[target_feature(enable = "neon")]
25079#[cfg_attr(test, assert_instr(nop, LANE = 0))]
25080#[rustc_legacy_const_generics(2)]
25081#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25082pub unsafe fn vst1_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1_t) {
25083    static_assert!(LANE == 0);
25084    *a = simd_extract!(b, LANE as u32);
25085}
25086#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
25087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"]
25088#[doc = "## Safety"]
25089#[doc = "  * Neon intrinsic unsafe"]
25090#[inline]
25091#[target_feature(enable = "neon")]
25092#[cfg_attr(test, assert_instr(nop, LANE = 0))]
25093#[rustc_legacy_const_generics(2)]
25094#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25095pub unsafe fn vst1q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2_t) {
25096    static_assert_uimm_bits!(LANE, 1);
25097    *a = simd_extract!(b, LANE as u32);
25098}
25099#[doc = "Store multiple 2-element structures from two registers"]
25100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"]
25101#[doc = "## Safety"]
25102#[doc = "  * Neon intrinsic unsafe"]
25103#[inline]
25104#[target_feature(enable = "neon")]
25105#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25106#[cfg_attr(test, assert_instr(stp))]
25107pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) {
25108    core::ptr::write_unaligned(a.cast(), b)
25109}
25110#[doc = "Store multiple 2-element structures from two registers"]
25111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"]
25112#[doc = "## Safety"]
25113#[doc = "  * Neon intrinsic unsafe"]
25114#[inline]
25115#[target_feature(enable = "neon")]
25116#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25117#[rustc_legacy_const_generics(2)]
25118#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25119pub unsafe fn vst2_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x2_t) {
25120    static_assert!(LANE == 0);
25121    unsafe extern "unadjusted" {
25122        #[cfg_attr(
25123            any(target_arch = "aarch64", target_arch = "arm64ec"),
25124            link_name = "llvm.aarch64.neon.st2lane.v1f64.p0"
25125        )]
25126        fn _vst2_lane_f64(a: float64x1_t, b: float64x1_t, n: i64, ptr: *mut i8);
25127    }
25128    _vst2_lane_f64(b.0, b.1, LANE as i64, a as _)
25129}
25130#[doc = "Store multiple 2-element structures from two registers"]
25131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"]
25132#[doc = "## Safety"]
25133#[doc = "  * Neon intrinsic unsafe"]
25134#[inline]
25135#[target_feature(enable = "neon")]
25136#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25137#[rustc_legacy_const_generics(2)]
25138#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25139pub unsafe fn vst2_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x2_t) {
25140    static_assert!(LANE == 0);
25141    unsafe extern "unadjusted" {
25142        #[cfg_attr(
25143            any(target_arch = "aarch64", target_arch = "arm64ec"),
25144            link_name = "llvm.aarch64.neon.st2lane.v1i64.p0"
25145        )]
25146        fn _vst2_lane_s64(a: int64x1_t, b: int64x1_t, n: i64, ptr: *mut i8);
25147    }
25148    _vst2_lane_s64(b.0, b.1, LANE as i64, a as _)
25149}
25150#[doc = "Store multiple 2-element structures from two registers"]
25151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"]
25152#[doc = "## Safety"]
25153#[doc = "  * Neon intrinsic unsafe"]
25154#[inline]
25155#[target_feature(enable = "neon,aes")]
25156#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25157#[rustc_legacy_const_generics(2)]
25158#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25159pub unsafe fn vst2_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x2_t) {
25160    static_assert!(LANE == 0);
25161    vst2_lane_s64::<LANE>(transmute(a), transmute(b))
25162}
25163#[doc = "Store multiple 2-element structures from two registers"]
25164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"]
25165#[doc = "## Safety"]
25166#[doc = "  * Neon intrinsic unsafe"]
25167#[inline]
25168#[target_feature(enable = "neon")]
25169#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25170#[rustc_legacy_const_generics(2)]
25171#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25172pub unsafe fn vst2_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x2_t) {
25173    static_assert!(LANE == 0);
25174    vst2_lane_s64::<LANE>(transmute(a), transmute(b))
25175}
25176#[doc = "Store multiple 2-element structures from two registers"]
25177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"]
25178#[doc = "## Safety"]
25179#[doc = "  * Neon intrinsic unsafe"]
25180#[inline]
25181#[target_feature(enable = "neon")]
25182#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25183#[cfg_attr(test, assert_instr(st2))]
25184pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) {
25185    crate::core_arch::macros::interleaving_store!(f64, 2, 2, a, b)
25186}
25187#[doc = "Store multiple 2-element structures from two registers"]
25188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"]
25189#[doc = "## Safety"]
25190#[doc = "  * Neon intrinsic unsafe"]
25191#[inline]
25192#[target_feature(enable = "neon")]
25193#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25194#[cfg_attr(test, assert_instr(st2))]
25195pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) {
25196    crate::core_arch::macros::interleaving_store!(i64, 2, 2, a, b)
25197}
25198#[doc = "Store multiple 2-element structures from two registers"]
25199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"]
25200#[doc = "## Safety"]
25201#[doc = "  * Neon intrinsic unsafe"]
25202#[inline]
25203#[target_feature(enable = "neon")]
25204#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25205#[rustc_legacy_const_generics(2)]
25206#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25207pub unsafe fn vst2q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x2_t) {
25208    static_assert_uimm_bits!(LANE, 1);
25209    unsafe extern "unadjusted" {
25210        #[cfg_attr(
25211            any(target_arch = "aarch64", target_arch = "arm64ec"),
25212            link_name = "llvm.aarch64.neon.st2lane.v2f64.p0"
25213        )]
25214        fn _vst2q_lane_f64(a: float64x2_t, b: float64x2_t, n: i64, ptr: *mut i8);
25215    }
25216    _vst2q_lane_f64(b.0, b.1, LANE as i64, a as _)
25217}
25218#[doc = "Store multiple 2-element structures from two registers"]
25219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"]
25220#[doc = "## Safety"]
25221#[doc = "  * Neon intrinsic unsafe"]
25222#[inline]
25223#[target_feature(enable = "neon")]
25224#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25225#[rustc_legacy_const_generics(2)]
25226#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25227pub unsafe fn vst2q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x2_t) {
25228    static_assert_uimm_bits!(LANE, 4);
25229    unsafe extern "unadjusted" {
25230        #[cfg_attr(
25231            any(target_arch = "aarch64", target_arch = "arm64ec"),
25232            link_name = "llvm.aarch64.neon.st2lane.v16i8.p0"
25233        )]
25234        fn _vst2q_lane_s8(a: int8x16_t, b: int8x16_t, n: i64, ptr: *mut i8);
25235    }
25236    _vst2q_lane_s8(b.0, b.1, LANE as i64, a as _)
25237}
25238#[doc = "Store multiple 2-element structures from two registers"]
25239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"]
25240#[doc = "## Safety"]
25241#[doc = "  * Neon intrinsic unsafe"]
25242#[inline]
25243#[target_feature(enable = "neon")]
25244#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25245#[rustc_legacy_const_generics(2)]
25246#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25247pub unsafe fn vst2q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x2_t) {
25248    static_assert_uimm_bits!(LANE, 1);
25249    unsafe extern "unadjusted" {
25250        #[cfg_attr(
25251            any(target_arch = "aarch64", target_arch = "arm64ec"),
25252            link_name = "llvm.aarch64.neon.st2lane.v2i64.p0"
25253        )]
25254        fn _vst2q_lane_s64(a: int64x2_t, b: int64x2_t, n: i64, ptr: *mut i8);
25255    }
25256    _vst2q_lane_s64(b.0, b.1, LANE as i64, a as _)
25257}
25258#[doc = "Store multiple 2-element structures from two registers"]
25259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"]
25260#[doc = "## Safety"]
25261#[doc = "  * Neon intrinsic unsafe"]
25262#[inline]
25263#[target_feature(enable = "neon,aes")]
25264#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25265#[rustc_legacy_const_generics(2)]
25266#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25267pub unsafe fn vst2q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x2_t) {
25268    static_assert_uimm_bits!(LANE, 1);
25269    vst2q_lane_s64::<LANE>(transmute(a), transmute(b))
25270}
25271#[doc = "Store multiple 2-element structures from two registers"]
25272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"]
25273#[doc = "## Safety"]
25274#[doc = "  * Neon intrinsic unsafe"]
25275#[inline]
25276#[target_feature(enable = "neon")]
25277#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25278#[rustc_legacy_const_generics(2)]
25279#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25280pub unsafe fn vst2q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x2_t) {
25281    static_assert_uimm_bits!(LANE, 4);
25282    vst2q_lane_s8::<LANE>(transmute(a), transmute(b))
25283}
25284#[doc = "Store multiple 2-element structures from two registers"]
25285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"]
25286#[doc = "## Safety"]
25287#[doc = "  * Neon intrinsic unsafe"]
25288#[inline]
25289#[target_feature(enable = "neon")]
25290#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25291#[rustc_legacy_const_generics(2)]
25292#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25293pub unsafe fn vst2q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x2_t) {
25294    static_assert_uimm_bits!(LANE, 1);
25295    vst2q_lane_s64::<LANE>(transmute(a), transmute(b))
25296}
25297#[doc = "Store multiple 2-element structures from two registers"]
25298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"]
25299#[doc = "## Safety"]
25300#[doc = "  * Neon intrinsic unsafe"]
25301#[inline]
25302#[target_feature(enable = "neon")]
25303#[cfg_attr(test, assert_instr(st2, LANE = 0))]
25304#[rustc_legacy_const_generics(2)]
25305#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25306pub unsafe fn vst2q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x2_t) {
25307    static_assert_uimm_bits!(LANE, 4);
25308    vst2q_lane_s8::<LANE>(transmute(a), transmute(b))
25309}
25310#[doc = "Store multiple 2-element structures from two registers"]
25311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"]
25312#[doc = "## Safety"]
25313#[doc = "  * Neon intrinsic unsafe"]
25314#[inline]
25315#[target_feature(enable = "neon,aes")]
25316#[cfg_attr(test, assert_instr(st2))]
25317#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25318pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) {
25319    vst2q_s64(transmute(a), transmute(b))
25320}
25321#[doc = "Store multiple 2-element structures from two registers"]
25322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"]
25323#[doc = "## Safety"]
25324#[doc = "  * Neon intrinsic unsafe"]
25325#[inline]
25326#[target_feature(enable = "neon")]
25327#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25328#[cfg_attr(test, assert_instr(st2))]
25329pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) {
25330    vst2q_s64(transmute(a), transmute(b))
25331}
25332#[doc = "Store multiple 3-element structures from three registers"]
25333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"]
25334#[doc = "## Safety"]
25335#[doc = "  * Neon intrinsic unsafe"]
25336#[inline]
25337#[target_feature(enable = "neon")]
25338#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25339#[cfg_attr(test, assert_instr(nop))]
25340pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) {
25341    core::ptr::write_unaligned(a.cast(), b)
25342}
25343#[doc = "Store multiple 3-element structures from three registers"]
25344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"]
25345#[doc = "## Safety"]
25346#[doc = "  * Neon intrinsic unsafe"]
25347#[inline]
25348#[target_feature(enable = "neon")]
25349#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25350#[rustc_legacy_const_generics(2)]
25351#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25352pub unsafe fn vst3_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x3_t) {
25353    static_assert!(LANE == 0);
25354    unsafe extern "unadjusted" {
25355        #[cfg_attr(
25356            any(target_arch = "aarch64", target_arch = "arm64ec"),
25357            link_name = "llvm.aarch64.neon.st3lane.v1f64.p0"
25358        )]
25359        fn _vst3_lane_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, n: i64, ptr: *mut i8);
25360    }
25361    _vst3_lane_f64(b.0, b.1, b.2, LANE as i64, a as _)
25362}
25363#[doc = "Store multiple 3-element structures from three registers"]
25364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"]
25365#[doc = "## Safety"]
25366#[doc = "  * Neon intrinsic unsafe"]
25367#[inline]
25368#[target_feature(enable = "neon")]
25369#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25370#[rustc_legacy_const_generics(2)]
25371#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25372pub unsafe fn vst3_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x3_t) {
25373    static_assert!(LANE == 0);
25374    unsafe extern "unadjusted" {
25375        #[cfg_attr(
25376            any(target_arch = "aarch64", target_arch = "arm64ec"),
25377            link_name = "llvm.aarch64.neon.st3lane.v1i64.p0"
25378        )]
25379        fn _vst3_lane_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, n: i64, ptr: *mut i8);
25380    }
25381    _vst3_lane_s64(b.0, b.1, b.2, LANE as i64, a as _)
25382}
25383#[doc = "Store multiple 3-element structures from three registers"]
25384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"]
25385#[doc = "## Safety"]
25386#[doc = "  * Neon intrinsic unsafe"]
25387#[inline]
25388#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25389#[target_feature(enable = "neon,aes")]
25390#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25391#[rustc_legacy_const_generics(2)]
25392pub unsafe fn vst3_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x3_t) {
25393    static_assert!(LANE == 0);
25394    vst3_lane_s64::<LANE>(transmute(a), transmute(b))
25395}
25396#[doc = "Store multiple 3-element structures from three registers"]
25397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"]
25398#[doc = "## Safety"]
25399#[doc = "  * Neon intrinsic unsafe"]
25400#[inline]
25401#[target_feature(enable = "neon")]
25402#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25403#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25404#[rustc_legacy_const_generics(2)]
25405pub unsafe fn vst3_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x3_t) {
25406    static_assert!(LANE == 0);
25407    vst3_lane_s64::<LANE>(transmute(a), transmute(b))
25408}
25409#[doc = "Store multiple 3-element structures from three registers"]
25410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"]
25411#[doc = "## Safety"]
25412#[doc = "  * Neon intrinsic unsafe"]
25413#[inline]
25414#[target_feature(enable = "neon")]
25415#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25416#[cfg_attr(test, assert_instr(st3))]
25417pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) {
25418    crate::core_arch::macros::interleaving_store!(f64, 2, 3, a, b)
25419}
25420#[doc = "Store multiple 3-element structures from three registers"]
25421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"]
25422#[doc = "## Safety"]
25423#[doc = "  * Neon intrinsic unsafe"]
25424#[inline]
25425#[target_feature(enable = "neon")]
25426#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25427#[cfg_attr(test, assert_instr(st3))]
25428pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) {
25429    crate::core_arch::macros::interleaving_store!(i64, 2, 3, a, b)
25430}
25431#[doc = "Store multiple 3-element structures from three registers"]
25432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"]
25433#[doc = "## Safety"]
25434#[doc = "  * Neon intrinsic unsafe"]
25435#[inline]
25436#[target_feature(enable = "neon")]
25437#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25438#[rustc_legacy_const_generics(2)]
25439#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25440pub unsafe fn vst3q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x3_t) {
25441    static_assert_uimm_bits!(LANE, 1);
25442    unsafe extern "unadjusted" {
25443        #[cfg_attr(
25444            any(target_arch = "aarch64", target_arch = "arm64ec"),
25445            link_name = "llvm.aarch64.neon.st3lane.v2f64.p0"
25446        )]
25447        fn _vst3q_lane_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, n: i64, ptr: *mut i8);
25448    }
25449    _vst3q_lane_f64(b.0, b.1, b.2, LANE as i64, a as _)
25450}
25451#[doc = "Store multiple 3-element structures from three registers"]
25452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"]
25453#[doc = "## Safety"]
25454#[doc = "  * Neon intrinsic unsafe"]
25455#[inline]
25456#[target_feature(enable = "neon")]
25457#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25458#[rustc_legacy_const_generics(2)]
25459#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25460pub unsafe fn vst3q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x3_t) {
25461    static_assert_uimm_bits!(LANE, 4);
25462    unsafe extern "unadjusted" {
25463        #[cfg_attr(
25464            any(target_arch = "aarch64", target_arch = "arm64ec"),
25465            link_name = "llvm.aarch64.neon.st3lane.v16i8.p0"
25466        )]
25467        fn _vst3q_lane_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, n: i64, ptr: *mut i8);
25468    }
25469    _vst3q_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
25470}
25471#[doc = "Store multiple 3-element structures from three registers"]
25472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"]
25473#[doc = "## Safety"]
25474#[doc = "  * Neon intrinsic unsafe"]
25475#[inline]
25476#[target_feature(enable = "neon")]
25477#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25478#[rustc_legacy_const_generics(2)]
25479#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25480pub unsafe fn vst3q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x3_t) {
25481    static_assert_uimm_bits!(LANE, 1);
25482    unsafe extern "unadjusted" {
25483        #[cfg_attr(
25484            any(target_arch = "aarch64", target_arch = "arm64ec"),
25485            link_name = "llvm.aarch64.neon.st3lane.v2i64.p0"
25486        )]
25487        fn _vst3q_lane_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, n: i64, ptr: *mut i8);
25488    }
25489    _vst3q_lane_s64(b.0, b.1, b.2, LANE as i64, a as _)
25490}
25491#[doc = "Store multiple 3-element structures from three registers"]
25492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"]
25493#[doc = "## Safety"]
25494#[doc = "  * Neon intrinsic unsafe"]
25495#[inline]
25496#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25497#[target_feature(enable = "neon,aes")]
25498#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25499#[rustc_legacy_const_generics(2)]
25500pub unsafe fn vst3q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x3_t) {
25501    static_assert_uimm_bits!(LANE, 1);
25502    vst3q_lane_s64::<LANE>(transmute(a), transmute(b))
25503}
25504#[doc = "Store multiple 3-element structures from three registers"]
25505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"]
25506#[doc = "## Safety"]
25507#[doc = "  * Neon intrinsic unsafe"]
25508#[inline]
25509#[target_feature(enable = "neon")]
25510#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25511#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25512#[rustc_legacy_const_generics(2)]
25513pub unsafe fn vst3q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x3_t) {
25514    static_assert_uimm_bits!(LANE, 4);
25515    vst3q_lane_s8::<LANE>(transmute(a), transmute(b))
25516}
25517#[doc = "Store multiple 3-element structures from three registers"]
25518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"]
25519#[doc = "## Safety"]
25520#[doc = "  * Neon intrinsic unsafe"]
25521#[inline]
25522#[target_feature(enable = "neon")]
25523#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25524#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25525#[rustc_legacy_const_generics(2)]
25526pub unsafe fn vst3q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x3_t) {
25527    static_assert_uimm_bits!(LANE, 1);
25528    vst3q_lane_s64::<LANE>(transmute(a), transmute(b))
25529}
25530#[doc = "Store multiple 3-element structures from three registers"]
25531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"]
25532#[doc = "## Safety"]
25533#[doc = "  * Neon intrinsic unsafe"]
25534#[inline]
25535#[target_feature(enable = "neon")]
25536#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25537#[cfg_attr(test, assert_instr(st3, LANE = 0))]
25538#[rustc_legacy_const_generics(2)]
25539pub unsafe fn vst3q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x3_t) {
25540    static_assert_uimm_bits!(LANE, 4);
25541    vst3q_lane_s8::<LANE>(transmute(a), transmute(b))
25542}
25543#[doc = "Store multiple 3-element structures from three registers"]
25544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"]
25545#[doc = "## Safety"]
25546#[doc = "  * Neon intrinsic unsafe"]
25547#[inline]
25548#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25549#[target_feature(enable = "neon,aes")]
25550#[cfg_attr(test, assert_instr(st3))]
25551pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) {
25552    vst3q_s64(transmute(a), transmute(b))
25553}
25554#[doc = "Store multiple 3-element structures from three registers"]
25555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"]
25556#[doc = "## Safety"]
25557#[doc = "  * Neon intrinsic unsafe"]
25558#[inline]
25559#[target_feature(enable = "neon")]
25560#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25561#[cfg_attr(test, assert_instr(st3))]
25562pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) {
25563    vst3q_s64(transmute(a), transmute(b))
25564}
25565#[doc = "Store multiple 4-element structures from four registers"]
25566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"]
25567#[doc = "## Safety"]
25568#[doc = "  * Neon intrinsic unsafe"]
25569#[inline]
25570#[target_feature(enable = "neon")]
25571#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25572#[cfg_attr(test, assert_instr(nop))]
25573pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) {
25574    core::ptr::write_unaligned(a.cast(), b)
25575}
25576#[doc = "Store multiple 4-element structures from four registers"]
25577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"]
25578#[doc = "## Safety"]
25579#[doc = "  * Neon intrinsic unsafe"]
25580#[inline]
25581#[target_feature(enable = "neon")]
25582#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25583#[rustc_legacy_const_generics(2)]
25584#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25585pub unsafe fn vst4_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x4_t) {
25586    static_assert!(LANE == 0);
25587    unsafe extern "unadjusted" {
25588        #[cfg_attr(
25589            any(target_arch = "aarch64", target_arch = "arm64ec"),
25590            link_name = "llvm.aarch64.neon.st4lane.v1f64.p0"
25591        )]
25592        fn _vst4_lane_f64(
25593            a: float64x1_t,
25594            b: float64x1_t,
25595            c: float64x1_t,
25596            d: float64x1_t,
25597            n: i64,
25598            ptr: *mut i8,
25599        );
25600    }
25601    _vst4_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _)
25602}
25603#[doc = "Store multiple 4-element structures from four registers"]
25604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"]
25605#[doc = "## Safety"]
25606#[doc = "  * Neon intrinsic unsafe"]
25607#[inline]
25608#[target_feature(enable = "neon")]
25609#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25610#[rustc_legacy_const_generics(2)]
25611#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25612pub unsafe fn vst4_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x4_t) {
25613    static_assert!(LANE == 0);
25614    unsafe extern "unadjusted" {
25615        #[cfg_attr(
25616            any(target_arch = "aarch64", target_arch = "arm64ec"),
25617            link_name = "llvm.aarch64.neon.st4lane.v1i64.p0"
25618        )]
25619        fn _vst4_lane_s64(
25620            a: int64x1_t,
25621            b: int64x1_t,
25622            c: int64x1_t,
25623            d: int64x1_t,
25624            n: i64,
25625            ptr: *mut i8,
25626        );
25627    }
25628    _vst4_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _)
25629}
25630#[doc = "Store multiple 4-element structures from four registers"]
25631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"]
25632#[doc = "## Safety"]
25633#[doc = "  * Neon intrinsic unsafe"]
25634#[inline]
25635#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25636#[target_feature(enable = "neon,aes")]
25637#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25638#[rustc_legacy_const_generics(2)]
25639pub unsafe fn vst4_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x4_t) {
25640    static_assert!(LANE == 0);
25641    vst4_lane_s64::<LANE>(transmute(a), transmute(b))
25642}
25643#[doc = "Store multiple 4-element structures from four registers"]
25644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"]
25645#[doc = "## Safety"]
25646#[doc = "  * Neon intrinsic unsafe"]
25647#[inline]
25648#[target_feature(enable = "neon")]
25649#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25650#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25651#[rustc_legacy_const_generics(2)]
25652pub unsafe fn vst4_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x4_t) {
25653    static_assert!(LANE == 0);
25654    vst4_lane_s64::<LANE>(transmute(a), transmute(b))
25655}
25656#[doc = "Store multiple 4-element structures from four registers"]
25657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"]
25658#[doc = "## Safety"]
25659#[doc = "  * Neon intrinsic unsafe"]
25660#[inline]
25661#[target_feature(enable = "neon")]
25662#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25663#[cfg_attr(test, assert_instr(st4))]
25664pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) {
25665    crate::core_arch::macros::interleaving_store!(f64, 2, 4, a, b)
25666}
25667#[doc = "Store multiple 4-element structures from four registers"]
25668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"]
25669#[doc = "## Safety"]
25670#[doc = "  * Neon intrinsic unsafe"]
25671#[inline]
25672#[target_feature(enable = "neon")]
25673#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25674#[cfg_attr(test, assert_instr(st4))]
25675pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) {
25676    crate::core_arch::macros::interleaving_store!(i64, 2, 4, a, b)
25677}
25678#[doc = "Store multiple 4-element structures from four registers"]
25679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"]
25680#[doc = "## Safety"]
25681#[doc = "  * Neon intrinsic unsafe"]
25682#[inline]
25683#[target_feature(enable = "neon")]
25684#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25685#[rustc_legacy_const_generics(2)]
25686#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25687pub unsafe fn vst4q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x4_t) {
25688    static_assert_uimm_bits!(LANE, 1);
25689    unsafe extern "unadjusted" {
25690        #[cfg_attr(
25691            any(target_arch = "aarch64", target_arch = "arm64ec"),
25692            link_name = "llvm.aarch64.neon.st4lane.v2f64.p0"
25693        )]
25694        fn _vst4q_lane_f64(
25695            a: float64x2_t,
25696            b: float64x2_t,
25697            c: float64x2_t,
25698            d: float64x2_t,
25699            n: i64,
25700            ptr: *mut i8,
25701        );
25702    }
25703    _vst4q_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _)
25704}
25705#[doc = "Store multiple 4-element structures from four registers"]
25706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"]
25707#[doc = "## Safety"]
25708#[doc = "  * Neon intrinsic unsafe"]
25709#[inline]
25710#[target_feature(enable = "neon")]
25711#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25712#[rustc_legacy_const_generics(2)]
25713#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25714pub unsafe fn vst4q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x4_t) {
25715    static_assert_uimm_bits!(LANE, 4);
25716    unsafe extern "unadjusted" {
25717        #[cfg_attr(
25718            any(target_arch = "aarch64", target_arch = "arm64ec"),
25719            link_name = "llvm.aarch64.neon.st4lane.v16i8.p0"
25720        )]
25721        fn _vst4q_lane_s8(
25722            a: int8x16_t,
25723            b: int8x16_t,
25724            c: int8x16_t,
25725            d: int8x16_t,
25726            n: i64,
25727            ptr: *mut i8,
25728        );
25729    }
25730    _vst4q_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
25731}
25732#[doc = "Store multiple 4-element structures from four registers"]
25733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"]
25734#[doc = "## Safety"]
25735#[doc = "  * Neon intrinsic unsafe"]
25736#[inline]
25737#[target_feature(enable = "neon")]
25738#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25739#[rustc_legacy_const_generics(2)]
25740#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25741pub unsafe fn vst4q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x4_t) {
25742    static_assert_uimm_bits!(LANE, 1);
25743    unsafe extern "unadjusted" {
25744        #[cfg_attr(
25745            any(target_arch = "aarch64", target_arch = "arm64ec"),
25746            link_name = "llvm.aarch64.neon.st4lane.v2i64.p0"
25747        )]
25748        fn _vst4q_lane_s64(
25749            a: int64x2_t,
25750            b: int64x2_t,
25751            c: int64x2_t,
25752            d: int64x2_t,
25753            n: i64,
25754            ptr: *mut i8,
25755        );
25756    }
25757    _vst4q_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _)
25758}
25759#[doc = "Store multiple 4-element structures from four registers"]
25760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"]
25761#[doc = "## Safety"]
25762#[doc = "  * Neon intrinsic unsafe"]
25763#[inline]
25764#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25765#[target_feature(enable = "neon,aes")]
25766#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25767#[rustc_legacy_const_generics(2)]
25768pub unsafe fn vst4q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x4_t) {
25769    static_assert_uimm_bits!(LANE, 1);
25770    vst4q_lane_s64::<LANE>(transmute(a), transmute(b))
25771}
25772#[doc = "Store multiple 4-element structures from four registers"]
25773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"]
25774#[doc = "## Safety"]
25775#[doc = "  * Neon intrinsic unsafe"]
25776#[inline]
25777#[target_feature(enable = "neon")]
25778#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25779#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25780#[rustc_legacy_const_generics(2)]
25781pub unsafe fn vst4q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x4_t) {
25782    static_assert_uimm_bits!(LANE, 4);
25783    vst4q_lane_s8::<LANE>(transmute(a), transmute(b))
25784}
25785#[doc = "Store multiple 4-element structures from four registers"]
25786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"]
25787#[doc = "## Safety"]
25788#[doc = "  * Neon intrinsic unsafe"]
25789#[inline]
25790#[target_feature(enable = "neon")]
25791#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25792#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25793#[rustc_legacy_const_generics(2)]
25794pub unsafe fn vst4q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x4_t) {
25795    static_assert_uimm_bits!(LANE, 1);
25796    vst4q_lane_s64::<LANE>(transmute(a), transmute(b))
25797}
25798#[doc = "Store multiple 4-element structures from four registers"]
25799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"]
25800#[doc = "## Safety"]
25801#[doc = "  * Neon intrinsic unsafe"]
25802#[inline]
25803#[target_feature(enable = "neon")]
25804#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25805#[cfg_attr(test, assert_instr(st4, LANE = 0))]
25806#[rustc_legacy_const_generics(2)]
25807pub unsafe fn vst4q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x4_t) {
25808    static_assert_uimm_bits!(LANE, 4);
25809    vst4q_lane_s8::<LANE>(transmute(a), transmute(b))
25810}
25811#[doc = "Store multiple 4-element structures from four registers"]
25812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"]
25813#[doc = "## Safety"]
25814#[doc = "  * Neon intrinsic unsafe"]
25815#[inline]
25816#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25817#[target_feature(enable = "neon,aes")]
25818#[cfg_attr(test, assert_instr(st4))]
25819pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) {
25820    vst4q_s64(transmute(a), transmute(b))
25821}
25822#[doc = "Store multiple 4-element structures from four registers"]
25823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"]
25824#[doc = "## Safety"]
25825#[doc = "  * Neon intrinsic unsafe"]
25826#[inline]
25827#[target_feature(enable = "neon")]
25828#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25829#[cfg_attr(test, assert_instr(st4))]
25830pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
25831    vst4q_s64(transmute(a), transmute(b))
25832}
25833#[doc = "Store-Release a single-element structure from one lane of one register."]
25834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
25835#[doc = "## Safety"]
25836#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
25837#[inline]
25838#[target_feature(enable = "neon,rcpc3")]
25839#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
25840#[rustc_legacy_const_generics(2)]
25841#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
25842#[cfg(target_has_atomic = "64")]
25843pub unsafe fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
25844    static_assert!(LANE == 0);
25845    vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
25846}
25847#[doc = "Store-Release a single-element structure from one lane of one register."]
25848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
25849#[doc = "## Safety"]
25850#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
25851#[inline]
25852#[target_feature(enable = "neon,rcpc3")]
25853#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
25854#[rustc_legacy_const_generics(2)]
25855#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
25856#[cfg(target_has_atomic = "64")]
25857pub unsafe fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
25858    static_assert_uimm_bits!(LANE, 1);
25859    vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
25860}
25861#[doc = "Store-Release a single-element structure from one lane of one register."]
25862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
25863#[doc = "## Safety"]
25864#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
25865#[inline]
25866#[target_feature(enable = "neon,rcpc3")]
25867#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
25868#[rustc_legacy_const_generics(2)]
25869#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
25870#[cfg(target_has_atomic = "64")]
25871pub unsafe fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
25872    static_assert!(LANE == 0);
25873    vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
25874}
25875#[doc = "Store-Release a single-element structure from one lane of one register."]
25876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
25877#[doc = "## Safety"]
25878#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
25879#[inline]
25880#[target_feature(enable = "neon,rcpc3")]
25881#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
25882#[rustc_legacy_const_generics(2)]
25883#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
25884#[cfg(target_has_atomic = "64")]
25885pub unsafe fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
25886    static_assert_uimm_bits!(LANE, 1);
25887    vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
25888}
25889#[doc = "Store-Release a single-element structure from one lane of one register."]
25890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
25891#[doc = "## Safety"]
25892#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
25893#[inline]
25894#[target_feature(enable = "neon,rcpc3")]
25895#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
25896#[rustc_legacy_const_generics(2)]
25897#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
25898#[cfg(target_has_atomic = "64")]
25899pub unsafe fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
25900    static_assert!(LANE == 0);
25901    vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
25902}
25903#[doc = "Store-Release a single-element structure from one lane of one register."]
25904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
25905#[doc = "## Safety"]
25906#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
25907#[inline]
25908#[target_feature(enable = "neon,rcpc3")]
25909#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
25910#[rustc_legacy_const_generics(2)]
25911#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
25912#[cfg(target_has_atomic = "64")]
25913pub unsafe fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
25914    static_assert_uimm_bits!(LANE, 1);
25915    vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
25916}
25917#[doc = "Store-Release a single-element structure from one lane of one register."]
25918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
25919#[doc = "## Safety"]
25920#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
25921#[inline]
25922#[target_feature(enable = "neon,rcpc3")]
25923#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
25924#[rustc_legacy_const_generics(2)]
25925#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
25926#[cfg(target_has_atomic = "64")]
25927pub unsafe fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
25928    static_assert!(LANE == 0);
25929    let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
25930    let lane: i64 = vget_lane_s64::<LANE>(val);
25931    (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
25932}
25933#[doc = "Store-Release a single-element structure from one lane of one register."]
25934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
25935#[doc = "## Safety"]
25936#[doc = "  * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]."]
25937#[inline]
25938#[target_feature(enable = "neon,rcpc3")]
25939#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
25940#[rustc_legacy_const_generics(2)]
25941#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
25942#[cfg(target_has_atomic = "64")]
25943pub unsafe fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
25944    static_assert_uimm_bits!(LANE, 1);
25945    let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
25946    let lane: i64 = vgetq_lane_s64::<LANE>(val);
25947    (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
25948}
25949#[doc = "Subtract"]
25950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"]
25951#[inline]
25952#[target_feature(enable = "neon")]
25953#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25954#[cfg_attr(test, assert_instr(fsub))]
25955pub fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
25956    unsafe { simd_sub(a, b) }
25957}
25958#[doc = "Subtract"]
25959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)"]
25960#[inline]
25961#[target_feature(enable = "neon")]
25962#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25963#[cfg_attr(test, assert_instr(fsub))]
25964pub fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
25965    unsafe { simd_sub(a, b) }
25966}
25967#[doc = "Subtract"]
25968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64)"]
25969#[inline]
25970#[target_feature(enable = "neon")]
25971#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25972#[cfg_attr(test, assert_instr(sub))]
25973pub fn vsubd_s64(a: i64, b: i64) -> i64 {
25974    a.wrapping_sub(b)
25975}
25976#[doc = "Subtract"]
25977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64)"]
25978#[inline]
25979#[target_feature(enable = "neon")]
25980#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25981#[cfg_attr(test, assert_instr(sub))]
25982pub fn vsubd_u64(a: u64, b: u64) -> u64 {
25983    a.wrapping_sub(b)
25984}
25985#[doc = "Subtract"]
25986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubh_f16)"]
25987#[inline]
25988#[target_feature(enable = "neon,fp16")]
25989#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25990#[cfg(not(target_arch = "arm64ec"))]
25991#[cfg_attr(test, assert_instr(fsub))]
25992pub fn vsubh_f16(a: f16, b: f16) -> f16 {
25993    a - b
25994}
25995#[doc = "Signed Subtract Long"]
25996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)"]
25997#[inline]
25998#[target_feature(enable = "neon")]
25999#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26000#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
26001pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
26002    unsafe {
26003        let c: int16x8_t = simd_cast(vget_high_s8(a));
26004        let d: int16x8_t = simd_cast(vget_high_s8(b));
26005        simd_sub(c, d)
26006    }
26007}
26008#[doc = "Signed Subtract Long"]
26009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)"]
26010#[inline]
26011#[target_feature(enable = "neon")]
26012#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26013#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
26014pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
26015    unsafe {
26016        let c: int32x4_t = simd_cast(vget_high_s16(a));
26017        let d: int32x4_t = simd_cast(vget_high_s16(b));
26018        simd_sub(c, d)
26019    }
26020}
26021#[doc = "Signed Subtract Long"]
26022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)"]
26023#[inline]
26024#[target_feature(enable = "neon")]
26025#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26026#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
26027pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
26028    unsafe {
26029        let c: int64x2_t = simd_cast(vget_high_s32(a));
26030        let d: int64x2_t = simd_cast(vget_high_s32(b));
26031        simd_sub(c, d)
26032    }
26033}
26034#[doc = "Unsigned Subtract Long"]
26035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)"]
26036#[inline]
26037#[target_feature(enable = "neon")]
26038#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26039#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
26040pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
26041    unsafe {
26042        let c: uint16x8_t = simd_cast(vget_high_u8(a));
26043        let d: uint16x8_t = simd_cast(vget_high_u8(b));
26044        simd_sub(c, d)
26045    }
26046}
26047#[doc = "Unsigned Subtract Long"]
26048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)"]
26049#[inline]
26050#[target_feature(enable = "neon")]
26051#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26052#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
26053pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
26054    unsafe {
26055        let c: uint32x4_t = simd_cast(vget_high_u16(a));
26056        let d: uint32x4_t = simd_cast(vget_high_u16(b));
26057        simd_sub(c, d)
26058    }
26059}
26060#[doc = "Unsigned Subtract Long"]
26061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)"]
26062#[inline]
26063#[target_feature(enable = "neon")]
26064#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26065#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
26066pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
26067    unsafe {
26068        let c: uint64x2_t = simd_cast(vget_high_u32(a));
26069        let d: uint64x2_t = simd_cast(vget_high_u32(b));
26070        simd_sub(c, d)
26071    }
26072}
26073#[doc = "Signed Subtract Wide"]
26074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)"]
26075#[inline]
26076#[target_feature(enable = "neon")]
26077#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26078#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
26079pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
26080    let c = vget_high_s8(b);
26081    unsafe { simd_sub(a, simd_cast(c)) }
26082}
26083#[doc = "Signed Subtract Wide"]
26084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"]
26085#[inline]
26086#[target_feature(enable = "neon")]
26087#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26088#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
26089pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
26090    let c = vget_high_s16(b);
26091    unsafe { simd_sub(a, simd_cast(c)) }
26092}
26093#[doc = "Signed Subtract Wide"]
26094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"]
26095#[inline]
26096#[target_feature(enable = "neon")]
26097#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26098#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
26099pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
26100    let c = vget_high_s32(b);
26101    unsafe { simd_sub(a, simd_cast(c)) }
26102}
26103#[doc = "Unsigned Subtract Wide"]
26104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"]
26105#[inline]
26106#[target_feature(enable = "neon")]
26107#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26108#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
26109pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
26110    let c = vget_high_u8(b);
26111    unsafe { simd_sub(a, simd_cast(c)) }
26112}
26113#[doc = "Unsigned Subtract Wide"]
26114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"]
26115#[inline]
26116#[target_feature(enable = "neon")]
26117#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26118#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
26119pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
26120    let c = vget_high_u16(b);
26121    unsafe { simd_sub(a, simd_cast(c)) }
26122}
26123#[doc = "Unsigned Subtract Wide"]
26124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"]
26125#[inline]
26126#[target_feature(enable = "neon")]
26127#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26128#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
26129pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
26130    let c = vget_high_u32(b);
26131    unsafe { simd_sub(a, simd_cast(c)) }
26132}
26133#[doc = "Table look-up"]
26134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
26135#[inline]
26136#[target_feature(enable = "neon")]
26137#[cfg_attr(test, assert_instr(tbl))]
26138#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26139pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
26140    vqtbl1_s8(vcombine_s8(a, unsafe { crate::mem::zeroed() }), unsafe {
26141        {
26142            transmute(b)
26143        }
26144    })
26145}
26146#[doc = "Table look-up"]
26147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
26148#[inline]
26149#[target_feature(enable = "neon")]
26150#[cfg_attr(test, assert_instr(tbl))]
26151#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26152pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
26153    vqtbl1_u8(vcombine_u8(a, unsafe { crate::mem::zeroed() }), b)
26154}
26155#[doc = "Table look-up"]
26156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
26157#[inline]
26158#[target_feature(enable = "neon")]
26159#[cfg_attr(test, assert_instr(tbl))]
26160#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26161pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
26162    vqtbl1_p8(vcombine_p8(a, unsafe { crate::mem::zeroed() }), b)
26163}
26164#[doc = "Table look-up"]
26165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
26166#[inline]
26167#[target_feature(enable = "neon")]
26168#[cfg_attr(test, assert_instr(tbl))]
26169#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26170pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
26171    vqtbl1_s8(vcombine_s8(a.0, a.1), vreinterpret_u8_s8(b))
26172}
26173#[doc = "Table look-up"]
26174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
26175#[inline]
26176#[target_feature(enable = "neon")]
26177#[cfg_attr(test, assert_instr(tbl))]
26178#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26179pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
26180    vqtbl1_u8(vcombine_u8(a.0, a.1), b)
26181}
26182#[doc = "Table look-up"]
26183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
26184#[inline]
26185#[target_feature(enable = "neon")]
26186#[cfg_attr(test, assert_instr(tbl))]
26187#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26188pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
26189    vqtbl1_p8(vcombine_p8(a.0, a.1), b)
26190}
26191#[doc = "Table look-up"]
26192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
26193#[inline]
26194#[target_feature(enable = "neon")]
26195#[cfg_attr(test, assert_instr(tbl))]
26196#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26197pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
26198    let x = int8x16x2_t(
26199        vcombine_s8(a.0, a.1),
26200        vcombine_s8(a.2, unsafe { crate::mem::zeroed() }),
26201    );
26202    vqtbl2_s8(x, vreinterpret_u8_s8(b))
26203}
26204#[doc = "Table look-up"]
26205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
26206#[inline]
26207#[target_feature(enable = "neon")]
26208#[cfg_attr(test, assert_instr(tbl))]
26209#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26210pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
26211    let x = uint8x16x2_t(
26212        vcombine_u8(a.0, a.1),
26213        vcombine_u8(a.2, unsafe { crate::mem::zeroed() }),
26214    );
26215    vqtbl2_u8(x, b)
26216}
26217#[doc = "Table look-up"]
26218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
26219#[inline]
26220#[target_feature(enable = "neon")]
26221#[cfg_attr(test, assert_instr(tbl))]
26222#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26223pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
26224    let x = poly8x16x2_t(
26225        vcombine_p8(a.0, a.1),
26226        vcombine_p8(a.2, unsafe { crate::mem::zeroed() }),
26227    );
26228    vqtbl2_p8(x, b)
26229}
26230#[doc = "Table look-up"]
26231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
26232#[inline]
26233#[target_feature(enable = "neon")]
26234#[cfg_attr(test, assert_instr(tbl))]
26235#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26236pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
26237    let x = int8x16x2_t(vcombine_s8(a.0, a.1), vcombine_s8(a.2, a.3));
26238    vqtbl2_s8(x, vreinterpret_u8_s8(b))
26239}
26240#[doc = "Table look-up"]
26241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
26242#[inline]
26243#[target_feature(enable = "neon")]
26244#[cfg_attr(test, assert_instr(tbl))]
26245#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26246pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
26247    let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3));
26248    vqtbl2_u8(x, b)
26249}
26250#[doc = "Table look-up"]
26251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
26252#[inline]
26253#[target_feature(enable = "neon")]
26254#[cfg_attr(test, assert_instr(tbl))]
26255#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26256pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
26257    let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3));
26258    vqtbl2_p8(x, b)
26259}
26260#[doc = "Extended table look-up"]
26261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
26262#[inline]
26263#[target_feature(enable = "neon")]
26264#[cfg_attr(test, assert_instr(tbx))]
26265#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26266pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
26267    unsafe {
26268        simd_select(
26269            simd_lt::<int8x8_t, int8x8_t>(c, transmute(i8x8::splat(8))),
26270            vqtbx1_s8(
26271                a,
26272                vcombine_s8(b, crate::mem::zeroed()),
26273                vreinterpret_u8_s8(c),
26274            ),
26275            a,
26276        )
26277    }
26278}
26279#[doc = "Extended table look-up"]
26280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
26281#[inline]
26282#[target_feature(enable = "neon")]
26283#[cfg_attr(test, assert_instr(tbx))]
26284#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26285pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
26286    unsafe {
26287        simd_select(
26288            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(8))),
26289            vqtbx1_u8(a, vcombine_u8(b, crate::mem::zeroed()), c),
26290            a,
26291        )
26292    }
26293}
26294#[doc = "Extended table look-up"]
26295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
26296#[inline]
26297#[target_feature(enable = "neon")]
26298#[cfg_attr(test, assert_instr(tbx))]
26299#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26300pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
26301    unsafe {
26302        simd_select(
26303            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(8))),
26304            vqtbx1_p8(a, vcombine_p8(b, crate::mem::zeroed()), c),
26305            a,
26306        )
26307    }
26308}
26309#[doc = "Extended table look-up"]
26310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
26311#[inline]
26312#[target_feature(enable = "neon")]
26313#[cfg_attr(test, assert_instr(tbx))]
26314#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26315pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
26316    unsafe {
26317        simd_select(
26318            simd_lt::<int8x8_t, int8x8_t>(c, transmute(i8x8::splat(16))),
26319            vqtbx1_s8(a, vcombine_s8(b.0, b.1), vreinterpret_u8_s8(c)),
26320            a,
26321        )
26322    }
26323}
26324#[doc = "Extended table look-up"]
26325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
26326#[inline]
26327#[target_feature(enable = "neon")]
26328#[cfg_attr(test, assert_instr(tbx))]
26329#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26330pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
26331    unsafe {
26332        simd_select(
26333            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(16))),
26334            vqtbx1_u8(a, vcombine_u8(b.0, b.1), c),
26335            a,
26336        )
26337    }
26338}
26339#[doc = "Extended table look-up"]
26340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
26341#[inline]
26342#[target_feature(enable = "neon")]
26343#[cfg_attr(test, assert_instr(tbx))]
26344#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26345pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
26346    unsafe {
26347        simd_select(
26348            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(16))),
26349            vqtbx1_p8(a, vcombine_p8(b.0, b.1), c),
26350            a,
26351        )
26352    }
26353}
26354#[doc = "Extended table look-up"]
26355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
26356#[inline]
26357#[target_feature(enable = "neon")]
26358#[cfg_attr(test, assert_instr(tbx))]
26359#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26360pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
26361    let x = int8x16x2_t(
26362        vcombine_s8(b.0, b.1),
26363        vcombine_s8(b.2, unsafe { crate::mem::zeroed() }),
26364    );
26365    unsafe {
26366        simd_select(
26367            simd_lt::<int8x8_t, int8x8_t>(c, transmute(i8x8::splat(24))),
26368            vqtbx2_s8(a, x, vreinterpret_u8_s8(c)),
26369            a,
26370        )
26371    }
26372}
26373#[doc = "Extended table look-up"]
26374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
26375#[inline]
26376#[target_feature(enable = "neon")]
26377#[cfg_attr(test, assert_instr(tbx))]
26378#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26379pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
26380    let x = uint8x16x2_t(
26381        vcombine_u8(b.0, b.1),
26382        vcombine_u8(b.2, unsafe { crate::mem::zeroed() }),
26383    );
26384    unsafe {
26385        simd_select(
26386            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(24))),
26387            vqtbx2_u8(a, x, c),
26388            a,
26389        )
26390    }
26391}
26392#[doc = "Extended table look-up"]
26393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
26394#[inline]
26395#[target_feature(enable = "neon")]
26396#[cfg_attr(test, assert_instr(tbx))]
26397#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26398pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
26399    let x = poly8x16x2_t(
26400        vcombine_p8(b.0, b.1),
26401        vcombine_p8(b.2, unsafe { crate::mem::zeroed() }),
26402    );
26403    unsafe {
26404        simd_select(
26405            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(24))),
26406            vqtbx2_p8(a, x, c),
26407            a,
26408        )
26409    }
26410}
26411#[doc = "Extended table look-up"]
26412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
26413#[inline]
26414#[target_feature(enable = "neon")]
26415#[cfg_attr(test, assert_instr(tbx))]
26416#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26417pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
26418    let x = int8x16x2_t(vcombine_s8(b.0, b.1), vcombine_s8(b.2, b.3));
26419    unsafe {
26420        simd_select(
26421            simd_lt::<int8x8_t, int8x8_t>(c, transmute(i8x8::splat(32))),
26422            vqtbx2_s8(a, x, vreinterpret_u8_s8(c)),
26423            a,
26424        )
26425    }
26426}
26427#[doc = "Extended table look-up"]
26428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
26429#[inline]
26430#[target_feature(enable = "neon")]
26431#[cfg_attr(test, assert_instr(tbx))]
26432#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26433pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
26434    let x = uint8x16x2_t(vcombine_u8(b.0, b.1), vcombine_u8(b.2, b.3));
26435    unsafe {
26436        simd_select(
26437            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(32))),
26438            vqtbx2_u8(a, x, c),
26439            a,
26440        )
26441    }
26442}
26443#[doc = "Extended table look-up"]
26444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
26445#[inline]
26446#[target_feature(enable = "neon")]
26447#[cfg_attr(test, assert_instr(tbx))]
26448#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26449pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
26450    let x = poly8x16x2_t(vcombine_p8(b.0, b.1), vcombine_p8(b.2, b.3));
26451    unsafe {
26452        simd_select(
26453            simd_lt::<uint8x8_t, int8x8_t>(c, transmute(u8x8::splat(32))),
26454            vqtbx2_p8(a, x, c),
26455            a,
26456        )
26457    }
26458}
26459#[doc = "Transpose vectors"]
26460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"]
26461#[inline]
26462#[cfg(target_endian = "little")]
26463#[target_feature(enable = "neon,fp16")]
26464#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
26465#[cfg(not(target_arch = "arm64ec"))]
26466#[cfg_attr(
26467    all(test, not(target_env = "msvc"), target_endian = "little"),
26468    assert_instr(trn1)
26469)]
26470pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
26471    unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
26472}
26473#[doc = "Transpose vectors"]
26474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"]
26475#[inline]
26476#[cfg(target_endian = "big")]
26477#[target_feature(enable = "neon,fp16")]
26478#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
26479#[cfg(not(target_arch = "arm64ec"))]
26480#[cfg_attr(
26481    all(test, not(target_env = "msvc"), target_endian = "little"),
26482    assert_instr(trn1)
26483)]
26484pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
26485    unsafe {
26486        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
26487        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
26488        let ret_val: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
26489        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
26490    }
26491}
26492#[doc = "Transpose vectors"]
26493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"]
26494#[inline]
26495#[cfg(target_endian = "little")]
26496#[target_feature(enable = "neon,fp16")]
26497#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
26498#[cfg(not(target_arch = "arm64ec"))]
26499#[cfg_attr(
26500    all(test, not(target_env = "msvc"), target_endian = "little"),
26501    assert_instr(trn1)
26502)]
26503pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
26504    unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
26505}
26506#[doc = "Transpose vectors"]
26507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"]
26508#[inline]
26509#[cfg(target_endian = "big")]
26510#[target_feature(enable = "neon,fp16")]
26511#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
26512#[cfg(not(target_arch = "arm64ec"))]
26513#[cfg_attr(
26514    all(test, not(target_env = "msvc"), target_endian = "little"),
26515    assert_instr(trn1)
26516)]
26517pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
26518    unsafe {
26519        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
26520        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
26521        let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
26522        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
26523    }
26524}
26525#[doc = "Transpose vectors"]
26526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"]
26527#[inline]
26528#[cfg(target_endian = "little")]
26529#[target_feature(enable = "neon")]
26530#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26531#[cfg_attr(
26532    all(test, not(target_env = "msvc"), target_endian = "little"),
26533    assert_instr(zip1)
26534)]
26535pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
26536    unsafe { simd_shuffle!(a, b, [0, 2]) }
26537}
26538#[doc = "Transpose vectors"]
26539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"]
26540#[inline]
26541#[cfg(target_endian = "big")]
26542#[target_feature(enable = "neon")]
26543#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26544#[cfg_attr(
26545    all(test, not(target_env = "msvc"), target_endian = "little"),
26546    assert_instr(zip1)
26547)]
26548pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
26549    unsafe {
26550        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
26551        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
26552        let ret_val: float32x2_t = simd_shuffle!(a, b, [0, 2]);
26553        simd_shuffle!(ret_val, ret_val, [1, 0])
26554    }
26555}
26556#[doc = "Transpose vectors"]
26557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"]
26558#[inline]
26559#[cfg(target_endian = "little")]
26560#[target_feature(enable = "neon")]
26561#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26562#[cfg_attr(
26563    all(test, not(target_env = "msvc"), target_endian = "little"),
26564    assert_instr(zip1)
26565)]
26566pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
26567    unsafe { simd_shuffle!(a, b, [0, 2]) }
26568}
26569#[doc = "Transpose vectors"]
26570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"]
26571#[inline]
26572#[cfg(target_endian = "big")]
26573#[target_feature(enable = "neon")]
26574#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26575#[cfg_attr(
26576    all(test, not(target_env = "msvc"), target_endian = "little"),
26577    assert_instr(zip1)
26578)]
26579pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
26580    unsafe {
26581        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
26582        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
26583        let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 2]);
26584        simd_shuffle!(ret_val, ret_val, [1, 0])
26585    }
26586}
26587#[doc = "Transpose vectors"]
26588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"]
26589#[inline]
26590#[cfg(target_endian = "little")]
26591#[target_feature(enable = "neon")]
26592#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26593#[cfg_attr(
26594    all(test, not(target_env = "msvc"), target_endian = "little"),
26595    assert_instr(zip1)
26596)]
26597pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
26598    unsafe { simd_shuffle!(a, b, [0, 2]) }
26599}
26600#[doc = "Transpose vectors"]
26601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"]
26602#[inline]
26603#[cfg(target_endian = "big")]
26604#[target_feature(enable = "neon")]
26605#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26606#[cfg_attr(
26607    all(test, not(target_env = "msvc"), target_endian = "little"),
26608    assert_instr(zip1)
26609)]
26610pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
26611    unsafe {
26612        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
26613        let b: int32x2_t = simd_shuffle!(b, b, [1, 0]);
26614        let ret_val: int32x2_t = simd_shuffle!(a, b, [0, 2]);
26615        simd_shuffle!(ret_val, ret_val, [1, 0])
26616    }
26617}
26618#[doc = "Transpose vectors"]
26619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"]
26620#[inline]
26621#[cfg(target_endian = "little")]
26622#[target_feature(enable = "neon")]
26623#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26624#[cfg_attr(
26625    all(test, not(target_env = "msvc"), target_endian = "little"),
26626    assert_instr(zip1)
26627)]
26628pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
26629    unsafe { simd_shuffle!(a, b, [0, 2]) }
26630}
26631#[doc = "Transpose vectors"]
26632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"]
26633#[inline]
26634#[cfg(target_endian = "big")]
26635#[target_feature(enable = "neon")]
26636#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26637#[cfg_attr(
26638    all(test, not(target_env = "msvc"), target_endian = "little"),
26639    assert_instr(zip1)
26640)]
26641pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
26642    unsafe {
26643        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
26644        let b: int64x2_t = simd_shuffle!(b, b, [1, 0]);
26645        let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 2]);
26646        simd_shuffle!(ret_val, ret_val, [1, 0])
26647    }
26648}
26649#[doc = "Transpose vectors"]
26650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"]
26651#[inline]
26652#[cfg(target_endian = "little")]
26653#[target_feature(enable = "neon")]
26654#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26655#[cfg_attr(
26656    all(test, not(target_env = "msvc"), target_endian = "little"),
26657    assert_instr(zip1)
26658)]
26659pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
26660    unsafe { simd_shuffle!(a, b, [0, 2]) }
26661}
26662#[doc = "Transpose vectors"]
26663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"]
26664#[inline]
26665#[cfg(target_endian = "big")]
26666#[target_feature(enable = "neon")]
26667#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26668#[cfg_attr(
26669    all(test, not(target_env = "msvc"), target_endian = "little"),
26670    assert_instr(zip1)
26671)]
26672pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
26673    unsafe {
26674        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
26675        let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]);
26676        let ret_val: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
26677        simd_shuffle!(ret_val, ret_val, [1, 0])
26678    }
26679}
26680#[doc = "Transpose vectors"]
26681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"]
26682#[inline]
26683#[cfg(target_endian = "little")]
26684#[target_feature(enable = "neon")]
26685#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26686#[cfg_attr(
26687    all(test, not(target_env = "msvc"), target_endian = "little"),
26688    assert_instr(zip1)
26689)]
26690pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
26691    unsafe { simd_shuffle!(a, b, [0, 2]) }
26692}
26693#[doc = "Transpose vectors"]
26694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"]
26695#[inline]
26696#[cfg(target_endian = "big")]
26697#[target_feature(enable = "neon")]
26698#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26699#[cfg_attr(
26700    all(test, not(target_env = "msvc"), target_endian = "little"),
26701    assert_instr(zip1)
26702)]
26703pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
26704    unsafe {
26705        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
26706        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
26707        let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 2]);
26708        simd_shuffle!(ret_val, ret_val, [1, 0])
26709    }
26710}
26711#[doc = "Transpose vectors"]
26712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"]
26713#[inline]
26714#[cfg(target_endian = "little")]
26715#[target_feature(enable = "neon")]
26716#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26717#[cfg_attr(
26718    all(test, not(target_env = "msvc"), target_endian = "little"),
26719    assert_instr(zip1)
26720)]
26721pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
26722    unsafe { simd_shuffle!(a, b, [0, 2]) }
26723}
26724#[doc = "Transpose vectors"]
26725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"]
26726#[inline]
26727#[cfg(target_endian = "big")]
26728#[target_feature(enable = "neon")]
26729#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26730#[cfg_attr(
26731    all(test, not(target_env = "msvc"), target_endian = "little"),
26732    assert_instr(zip1)
26733)]
26734pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
26735    unsafe {
26736        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
26737        let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]);
26738        let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 2]);
26739        simd_shuffle!(ret_val, ret_val, [1, 0])
26740    }
26741}
26742#[doc = "Transpose vectors"]
26743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"]
26744#[inline]
26745#[cfg(target_endian = "little")]
26746#[target_feature(enable = "neon")]
26747#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26748#[cfg_attr(
26749    all(test, not(target_env = "msvc"), target_endian = "little"),
26750    assert_instr(trn1)
26751)]
26752pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
26753    unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
26754}
26755#[doc = "Transpose vectors"]
26756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"]
26757#[inline]
26758#[cfg(target_endian = "big")]
26759#[target_feature(enable = "neon")]
26760#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26761#[cfg_attr(
26762    all(test, not(target_env = "msvc"), target_endian = "little"),
26763    assert_instr(trn1)
26764)]
26765pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
26766    unsafe {
26767        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
26768        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
26769        let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
26770        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
26771    }
26772}
26773#[doc = "Transpose vectors"]
26774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"]
26775#[inline]
26776#[cfg(target_endian = "little")]
26777#[target_feature(enable = "neon")]
26778#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26779#[cfg_attr(
26780    all(test, not(target_env = "msvc"), target_endian = "little"),
26781    assert_instr(trn1)
26782)]
26783pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
26784    unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
26785}
26786#[doc = "Transpose vectors"]
26787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"]
26788#[inline]
26789#[cfg(target_endian = "big")]
26790#[target_feature(enable = "neon")]
26791#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26792#[cfg_attr(
26793    all(test, not(target_env = "msvc"), target_endian = "little"),
26794    assert_instr(trn1)
26795)]
26796pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
26797    unsafe {
26798        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
26799        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
26800        let ret_val: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
26801        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
26802    }
26803}
26804#[doc = "Transpose vectors"]
26805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"]
26806#[inline]
26807#[cfg(target_endian = "little")]
26808#[target_feature(enable = "neon")]
26809#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26810#[cfg_attr(
26811    all(test, not(target_env = "msvc"), target_endian = "little"),
26812    assert_instr(trn1)
26813)]
26814pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
26815    unsafe {
26816        simd_shuffle!(
26817            a,
26818            b,
26819            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
26820        )
26821    }
26822}
26823#[doc = "Transpose vectors"]
26824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"]
26825#[inline]
26826#[cfg(target_endian = "big")]
26827#[target_feature(enable = "neon")]
26828#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26829#[cfg_attr(
26830    all(test, not(target_env = "msvc"), target_endian = "little"),
26831    assert_instr(trn1)
26832)]
26833pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
26834    unsafe {
26835        let a: int8x16_t =
26836            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
26837        let b: int8x16_t =
26838            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
26839        let ret_val: int8x16_t = simd_shuffle!(
26840            a,
26841            b,
26842            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
26843        );
26844        simd_shuffle!(
26845            ret_val,
26846            ret_val,
26847            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
26848        )
26849    }
26850}
26851#[doc = "Transpose vectors"]
26852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"]
26853#[inline]
26854#[cfg(target_endian = "little")]
26855#[target_feature(enable = "neon")]
26856#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26857#[cfg_attr(
26858    all(test, not(target_env = "msvc"), target_endian = "little"),
26859    assert_instr(trn1)
26860)]
26861pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
26862    unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
26863}
26864#[doc = "Transpose vectors"]
26865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"]
26866#[inline]
26867#[cfg(target_endian = "big")]
26868#[target_feature(enable = "neon")]
26869#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26870#[cfg_attr(
26871    all(test, not(target_env = "msvc"), target_endian = "little"),
26872    assert_instr(trn1)
26873)]
26874pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
26875    unsafe {
26876        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
26877        let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
26878        let ret_val: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
26879        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
26880    }
26881}
26882#[doc = "Transpose vectors"]
26883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"]
26884#[inline]
26885#[cfg(target_endian = "little")]
26886#[target_feature(enable = "neon")]
26887#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26888#[cfg_attr(
26889    all(test, not(target_env = "msvc"), target_endian = "little"),
26890    assert_instr(trn1)
26891)]
26892pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
26893    unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
26894}
26895#[doc = "Transpose vectors"]
26896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"]
26897#[inline]
26898#[cfg(target_endian = "big")]
26899#[target_feature(enable = "neon")]
26900#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26901#[cfg_attr(
26902    all(test, not(target_env = "msvc"), target_endian = "little"),
26903    assert_instr(trn1)
26904)]
26905pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
26906    unsafe {
26907        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
26908        let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
26909        let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
26910        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
26911    }
26912}
26913#[doc = "Transpose vectors"]
26914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"]
26915#[inline]
26916#[cfg(target_endian = "little")]
26917#[target_feature(enable = "neon")]
26918#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26919#[cfg_attr(
26920    all(test, not(target_env = "msvc"), target_endian = "little"),
26921    assert_instr(trn1)
26922)]
26923pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
26924    unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
26925}
26926#[doc = "Transpose vectors"]
26927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"]
26928#[inline]
26929#[cfg(target_endian = "big")]
26930#[target_feature(enable = "neon")]
26931#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26932#[cfg_attr(
26933    all(test, not(target_env = "msvc"), target_endian = "little"),
26934    assert_instr(trn1)
26935)]
26936pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
26937    unsafe {
26938        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
26939        let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
26940        let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
26941        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
26942    }
26943}
26944#[doc = "Transpose vectors"]
26945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"]
26946#[inline]
26947#[cfg(target_endian = "little")]
26948#[target_feature(enable = "neon")]
26949#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26950#[cfg_attr(
26951    all(test, not(target_env = "msvc"), target_endian = "little"),
26952    assert_instr(trn1)
26953)]
26954pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
26955    unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
26956}
26957#[doc = "Transpose vectors"]
26958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"]
26959#[inline]
26960#[cfg(target_endian = "big")]
26961#[target_feature(enable = "neon")]
26962#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26963#[cfg_attr(
26964    all(test, not(target_env = "msvc"), target_endian = "little"),
26965    assert_instr(trn1)
26966)]
26967pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
26968    unsafe {
26969        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
26970        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
26971        let ret_val: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
26972        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
26973    }
26974}
26975#[doc = "Transpose vectors"]
26976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"]
26977#[inline]
26978#[cfg(target_endian = "little")]
26979#[target_feature(enable = "neon")]
26980#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26981#[cfg_attr(
26982    all(test, not(target_env = "msvc"), target_endian = "little"),
26983    assert_instr(trn1)
26984)]
26985pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
26986    unsafe {
26987        simd_shuffle!(
26988            a,
26989            b,
26990            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
26991        )
26992    }
26993}
26994#[doc = "Transpose vectors"]
26995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"]
26996#[inline]
26997#[cfg(target_endian = "big")]
26998#[target_feature(enable = "neon")]
26999#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27000#[cfg_attr(
27001    all(test, not(target_env = "msvc"), target_endian = "little"),
27002    assert_instr(trn1)
27003)]
27004pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
27005    unsafe {
27006        let a: uint8x16_t =
27007            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27008        let b: uint8x16_t =
27009            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27010        let ret_val: uint8x16_t = simd_shuffle!(
27011            a,
27012            b,
27013            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
27014        );
27015        simd_shuffle!(
27016            ret_val,
27017            ret_val,
27018            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27019        )
27020    }
27021}
27022#[doc = "Transpose vectors"]
27023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"]
27024#[inline]
27025#[cfg(target_endian = "little")]
27026#[target_feature(enable = "neon")]
27027#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27028#[cfg_attr(
27029    all(test, not(target_env = "msvc"), target_endian = "little"),
27030    assert_instr(trn1)
27031)]
27032pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
27033    unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
27034}
27035#[doc = "Transpose vectors"]
27036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"]
27037#[inline]
27038#[cfg(target_endian = "big")]
27039#[target_feature(enable = "neon")]
27040#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27041#[cfg_attr(
27042    all(test, not(target_env = "msvc"), target_endian = "little"),
27043    assert_instr(trn1)
27044)]
27045pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
27046    unsafe {
27047        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
27048        let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
27049        let ret_val: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
27050        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
27051    }
27052}
27053#[doc = "Transpose vectors"]
27054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"]
27055#[inline]
27056#[cfg(target_endian = "little")]
27057#[target_feature(enable = "neon")]
27058#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27059#[cfg_attr(
27060    all(test, not(target_env = "msvc"), target_endian = "little"),
27061    assert_instr(trn1)
27062)]
27063pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
27064    unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
27065}
27066#[doc = "Transpose vectors"]
27067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"]
27068#[inline]
27069#[cfg(target_endian = "big")]
27070#[target_feature(enable = "neon")]
27071#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27072#[cfg_attr(
27073    all(test, not(target_env = "msvc"), target_endian = "little"),
27074    assert_instr(trn1)
27075)]
27076pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
27077    unsafe {
27078        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
27079        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
27080        let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
27081        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
27082    }
27083}
27084#[doc = "Transpose vectors"]
27085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"]
27086#[inline]
27087#[cfg(target_endian = "little")]
27088#[target_feature(enable = "neon")]
27089#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27090#[cfg_attr(
27091    all(test, not(target_env = "msvc"), target_endian = "little"),
27092    assert_instr(trn1)
27093)]
27094pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
27095    unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
27096}
27097#[doc = "Transpose vectors"]
27098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"]
27099#[inline]
27100#[cfg(target_endian = "big")]
27101#[target_feature(enable = "neon")]
27102#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27103#[cfg_attr(
27104    all(test, not(target_env = "msvc"), target_endian = "little"),
27105    assert_instr(trn1)
27106)]
27107pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
27108    unsafe {
27109        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
27110        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
27111        let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
27112        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
27113    }
27114}
27115#[doc = "Transpose vectors"]
27116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"]
27117#[inline]
27118#[cfg(target_endian = "little")]
27119#[target_feature(enable = "neon")]
27120#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27121#[cfg_attr(
27122    all(test, not(target_env = "msvc"), target_endian = "little"),
27123    assert_instr(trn1)
27124)]
27125pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
27126    unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
27127}
27128#[doc = "Transpose vectors"]
27129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"]
27130#[inline]
27131#[cfg(target_endian = "big")]
27132#[target_feature(enable = "neon")]
27133#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27134#[cfg_attr(
27135    all(test, not(target_env = "msvc"), target_endian = "little"),
27136    assert_instr(trn1)
27137)]
27138pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
27139    unsafe {
27140        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
27141        let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
27142        let ret_val: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
27143        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
27144    }
27145}
27146#[doc = "Transpose vectors"]
27147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"]
27148#[inline]
27149#[cfg(target_endian = "little")]
27150#[target_feature(enable = "neon")]
27151#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27152#[cfg_attr(
27153    all(test, not(target_env = "msvc"), target_endian = "little"),
27154    assert_instr(trn1)
27155)]
27156pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
27157    unsafe {
27158        simd_shuffle!(
27159            a,
27160            b,
27161            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
27162        )
27163    }
27164}
27165#[doc = "Transpose vectors"]
27166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"]
27167#[inline]
27168#[cfg(target_endian = "big")]
27169#[target_feature(enable = "neon")]
27170#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27171#[cfg_attr(
27172    all(test, not(target_env = "msvc"), target_endian = "little"),
27173    assert_instr(trn1)
27174)]
27175pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
27176    unsafe {
27177        let a: poly8x16_t =
27178            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27179        let b: poly8x16_t =
27180            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27181        let ret_val: poly8x16_t = simd_shuffle!(
27182            a,
27183            b,
27184            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
27185        );
27186        simd_shuffle!(
27187            ret_val,
27188            ret_val,
27189            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27190        )
27191    }
27192}
27193#[doc = "Transpose vectors"]
27194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"]
27195#[inline]
27196#[cfg(target_endian = "little")]
27197#[target_feature(enable = "neon")]
27198#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27199#[cfg_attr(
27200    all(test, not(target_env = "msvc"), target_endian = "little"),
27201    assert_instr(trn1)
27202)]
27203pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
27204    unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
27205}
27206#[doc = "Transpose vectors"]
27207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"]
27208#[inline]
27209#[cfg(target_endian = "big")]
27210#[target_feature(enable = "neon")]
27211#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27212#[cfg_attr(
27213    all(test, not(target_env = "msvc"), target_endian = "little"),
27214    assert_instr(trn1)
27215)]
27216pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
27217    unsafe {
27218        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
27219        let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
27220        let ret_val: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
27221        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
27222    }
27223}
27224#[doc = "Transpose vectors"]
27225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"]
27226#[inline]
27227#[cfg(target_endian = "little")]
27228#[target_feature(enable = "neon")]
27229#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27230#[cfg_attr(
27231    all(test, not(target_env = "msvc"), target_endian = "little"),
27232    assert_instr(trn1)
27233)]
27234pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
27235    unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
27236}
27237#[doc = "Transpose vectors"]
27238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"]
27239#[inline]
27240#[cfg(target_endian = "big")]
27241#[target_feature(enable = "neon")]
27242#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27243#[cfg_attr(
27244    all(test, not(target_env = "msvc"), target_endian = "little"),
27245    assert_instr(trn1)
27246)]
27247pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
27248    unsafe {
27249        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
27250        let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
27251        let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
27252        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
27253    }
27254}
27255#[doc = "Transpose vectors"]
27256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"]
27257#[inline]
27258#[cfg(target_endian = "little")]
27259#[target_feature(enable = "neon,fp16")]
27260#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
27261#[cfg(not(target_arch = "arm64ec"))]
27262#[cfg_attr(
27263    all(test, not(target_env = "msvc"), target_endian = "little"),
27264    assert_instr(trn2)
27265)]
27266pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
27267    unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
27268}
27269#[doc = "Transpose vectors"]
27270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"]
27271#[inline]
27272#[cfg(target_endian = "big")]
27273#[target_feature(enable = "neon,fp16")]
27274#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
27275#[cfg(not(target_arch = "arm64ec"))]
27276#[cfg_attr(
27277    all(test, not(target_env = "msvc"), target_endian = "little"),
27278    assert_instr(trn2)
27279)]
27280pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
27281    unsafe {
27282        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
27283        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
27284        let ret_val: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
27285        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
27286    }
27287}
27288#[doc = "Transpose vectors"]
27289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"]
27290#[inline]
27291#[cfg(target_endian = "little")]
27292#[target_feature(enable = "neon,fp16")]
27293#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
27294#[cfg(not(target_arch = "arm64ec"))]
27295#[cfg_attr(
27296    all(test, not(target_env = "msvc"), target_endian = "little"),
27297    assert_instr(trn2)
27298)]
27299pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
27300    unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
27301}
27302#[doc = "Transpose vectors"]
27303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"]
27304#[inline]
27305#[cfg(target_endian = "big")]
27306#[target_feature(enable = "neon,fp16")]
27307#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
27308#[cfg(not(target_arch = "arm64ec"))]
27309#[cfg_attr(
27310    all(test, not(target_env = "msvc"), target_endian = "little"),
27311    assert_instr(trn2)
27312)]
27313pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
27314    unsafe {
27315        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
27316        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
27317        let ret_val: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
27318        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
27319    }
27320}
27321#[doc = "Transpose vectors"]
27322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"]
27323#[inline]
27324#[cfg(target_endian = "little")]
27325#[target_feature(enable = "neon")]
27326#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27327#[cfg_attr(
27328    all(test, not(target_env = "msvc"), target_endian = "little"),
27329    assert_instr(zip2)
27330)]
27331pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
27332    unsafe { simd_shuffle!(a, b, [1, 3]) }
27333}
27334#[doc = "Transpose vectors"]
27335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"]
27336#[inline]
27337#[cfg(target_endian = "big")]
27338#[target_feature(enable = "neon")]
27339#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27340#[cfg_attr(
27341    all(test, not(target_env = "msvc"), target_endian = "little"),
27342    assert_instr(zip2)
27343)]
27344pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
27345    unsafe {
27346        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
27347        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
27348        let ret_val: float32x2_t = simd_shuffle!(a, b, [1, 3]);
27349        simd_shuffle!(ret_val, ret_val, [1, 0])
27350    }
27351}
27352#[doc = "Transpose vectors"]
27353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"]
27354#[inline]
27355#[cfg(target_endian = "little")]
27356#[target_feature(enable = "neon")]
27357#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27358#[cfg_attr(
27359    all(test, not(target_env = "msvc"), target_endian = "little"),
27360    assert_instr(zip2)
27361)]
27362pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
27363    unsafe { simd_shuffle!(a, b, [1, 3]) }
27364}
27365#[doc = "Transpose vectors"]
27366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"]
27367#[inline]
27368#[cfg(target_endian = "big")]
27369#[target_feature(enable = "neon")]
27370#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27371#[cfg_attr(
27372    all(test, not(target_env = "msvc"), target_endian = "little"),
27373    assert_instr(zip2)
27374)]
27375pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
27376    unsafe {
27377        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
27378        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
27379        let ret_val: float64x2_t = simd_shuffle!(a, b, [1, 3]);
27380        simd_shuffle!(ret_val, ret_val, [1, 0])
27381    }
27382}
27383#[doc = "Transpose vectors"]
27384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"]
27385#[inline]
27386#[cfg(target_endian = "little")]
27387#[target_feature(enable = "neon")]
27388#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27389#[cfg_attr(
27390    all(test, not(target_env = "msvc"), target_endian = "little"),
27391    assert_instr(zip2)
27392)]
27393pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
27394    unsafe { simd_shuffle!(a, b, [1, 3]) }
27395}
27396#[doc = "Transpose vectors"]
27397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"]
27398#[inline]
27399#[cfg(target_endian = "big")]
27400#[target_feature(enable = "neon")]
27401#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27402#[cfg_attr(
27403    all(test, not(target_env = "msvc"), target_endian = "little"),
27404    assert_instr(zip2)
27405)]
27406pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
27407    unsafe {
27408        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
27409        let b: int32x2_t = simd_shuffle!(b, b, [1, 0]);
27410        let ret_val: int32x2_t = simd_shuffle!(a, b, [1, 3]);
27411        simd_shuffle!(ret_val, ret_val, [1, 0])
27412    }
27413}
27414#[doc = "Transpose vectors"]
27415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"]
27416#[inline]
27417#[cfg(target_endian = "little")]
27418#[target_feature(enable = "neon")]
27419#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27420#[cfg_attr(
27421    all(test, not(target_env = "msvc"), target_endian = "little"),
27422    assert_instr(zip2)
27423)]
27424pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
27425    unsafe { simd_shuffle!(a, b, [1, 3]) }
27426}
27427#[doc = "Transpose vectors"]
27428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"]
27429#[inline]
27430#[cfg(target_endian = "big")]
27431#[target_feature(enable = "neon")]
27432#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27433#[cfg_attr(
27434    all(test, not(target_env = "msvc"), target_endian = "little"),
27435    assert_instr(zip2)
27436)]
27437pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
27438    unsafe {
27439        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
27440        let b: int64x2_t = simd_shuffle!(b, b, [1, 0]);
27441        let ret_val: int64x2_t = simd_shuffle!(a, b, [1, 3]);
27442        simd_shuffle!(ret_val, ret_val, [1, 0])
27443    }
27444}
27445#[doc = "Transpose vectors"]
27446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"]
27447#[inline]
27448#[cfg(target_endian = "little")]
27449#[target_feature(enable = "neon")]
27450#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27451#[cfg_attr(
27452    all(test, not(target_env = "msvc"), target_endian = "little"),
27453    assert_instr(zip2)
27454)]
27455pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
27456    unsafe { simd_shuffle!(a, b, [1, 3]) }
27457}
27458#[doc = "Transpose vectors"]
27459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"]
27460#[inline]
27461#[cfg(target_endian = "big")]
27462#[target_feature(enable = "neon")]
27463#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27464#[cfg_attr(
27465    all(test, not(target_env = "msvc"), target_endian = "little"),
27466    assert_instr(zip2)
27467)]
27468pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
27469    unsafe {
27470        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
27471        let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]);
27472        let ret_val: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
27473        simd_shuffle!(ret_val, ret_val, [1, 0])
27474    }
27475}
27476#[doc = "Transpose vectors"]
27477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"]
27478#[inline]
27479#[cfg(target_endian = "little")]
27480#[target_feature(enable = "neon")]
27481#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27482#[cfg_attr(
27483    all(test, not(target_env = "msvc"), target_endian = "little"),
27484    assert_instr(zip2)
27485)]
27486pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
27487    unsafe { simd_shuffle!(a, b, [1, 3]) }
27488}
27489#[doc = "Transpose vectors"]
27490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"]
27491#[inline]
27492#[cfg(target_endian = "big")]
27493#[target_feature(enable = "neon")]
27494#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27495#[cfg_attr(
27496    all(test, not(target_env = "msvc"), target_endian = "little"),
27497    assert_instr(zip2)
27498)]
27499pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
27500    unsafe {
27501        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
27502        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
27503        let ret_val: uint64x2_t = simd_shuffle!(a, b, [1, 3]);
27504        simd_shuffle!(ret_val, ret_val, [1, 0])
27505    }
27506}
27507#[doc = "Transpose vectors"]
27508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"]
27509#[inline]
27510#[cfg(target_endian = "little")]
27511#[target_feature(enable = "neon")]
27512#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27513#[cfg_attr(
27514    all(test, not(target_env = "msvc"), target_endian = "little"),
27515    assert_instr(zip2)
27516)]
27517pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
27518    unsafe { simd_shuffle!(a, b, [1, 3]) }
27519}
27520#[doc = "Transpose vectors"]
27521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"]
27522#[inline]
27523#[cfg(target_endian = "big")]
27524#[target_feature(enable = "neon")]
27525#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27526#[cfg_attr(
27527    all(test, not(target_env = "msvc"), target_endian = "little"),
27528    assert_instr(zip2)
27529)]
27530pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
27531    unsafe {
27532        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
27533        let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]);
27534        let ret_val: poly64x2_t = simd_shuffle!(a, b, [1, 3]);
27535        simd_shuffle!(ret_val, ret_val, [1, 0])
27536    }
27537}
27538#[doc = "Transpose vectors"]
27539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"]
27540#[inline]
27541#[cfg(target_endian = "little")]
27542#[target_feature(enable = "neon")]
27543#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27544#[cfg_attr(
27545    all(test, not(target_env = "msvc"), target_endian = "little"),
27546    assert_instr(trn2)
27547)]
27548pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
27549    unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
27550}
27551#[doc = "Transpose vectors"]
27552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"]
27553#[inline]
27554#[cfg(target_endian = "big")]
27555#[target_feature(enable = "neon")]
27556#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27557#[cfg_attr(
27558    all(test, not(target_env = "msvc"), target_endian = "little"),
27559    assert_instr(trn2)
27560)]
27561pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
27562    unsafe {
27563        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
27564        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
27565        let ret_val: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
27566        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
27567    }
27568}
27569#[doc = "Transpose vectors"]
27570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"]
27571#[inline]
27572#[cfg(target_endian = "little")]
27573#[target_feature(enable = "neon")]
27574#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27575#[cfg_attr(
27576    all(test, not(target_env = "msvc"), target_endian = "little"),
27577    assert_instr(trn2)
27578)]
27579pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
27580    unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
27581}
27582#[doc = "Transpose vectors"]
27583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"]
27584#[inline]
27585#[cfg(target_endian = "big")]
27586#[target_feature(enable = "neon")]
27587#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27588#[cfg_attr(
27589    all(test, not(target_env = "msvc"), target_endian = "little"),
27590    assert_instr(trn2)
27591)]
27592pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
27593    unsafe {
27594        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
27595        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
27596        let ret_val: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
27597        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
27598    }
27599}
27600#[doc = "Transpose vectors"]
27601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"]
27602#[inline]
27603#[cfg(target_endian = "little")]
27604#[target_feature(enable = "neon")]
27605#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27606#[cfg_attr(
27607    all(test, not(target_env = "msvc"), target_endian = "little"),
27608    assert_instr(trn2)
27609)]
27610pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
27611    unsafe {
27612        simd_shuffle!(
27613            a,
27614            b,
27615            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
27616        )
27617    }
27618}
27619#[doc = "Transpose vectors"]
27620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"]
27621#[inline]
27622#[cfg(target_endian = "big")]
27623#[target_feature(enable = "neon")]
27624#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27625#[cfg_attr(
27626    all(test, not(target_env = "msvc"), target_endian = "little"),
27627    assert_instr(trn2)
27628)]
27629pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
27630    unsafe {
27631        let a: int8x16_t =
27632            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27633        let b: int8x16_t =
27634            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27635        let ret_val: int8x16_t = simd_shuffle!(
27636            a,
27637            b,
27638            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
27639        );
27640        simd_shuffle!(
27641            ret_val,
27642            ret_val,
27643            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27644        )
27645    }
27646}
27647#[doc = "Transpose vectors"]
27648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"]
27649#[inline]
27650#[cfg(target_endian = "little")]
27651#[target_feature(enable = "neon")]
27652#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27653#[cfg_attr(
27654    all(test, not(target_env = "msvc"), target_endian = "little"),
27655    assert_instr(trn2)
27656)]
27657pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
27658    unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
27659}
27660#[doc = "Transpose vectors"]
27661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"]
27662#[inline]
27663#[cfg(target_endian = "big")]
27664#[target_feature(enable = "neon")]
27665#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27666#[cfg_attr(
27667    all(test, not(target_env = "msvc"), target_endian = "little"),
27668    assert_instr(trn2)
27669)]
27670pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
27671    unsafe {
27672        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
27673        let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
27674        let ret_val: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
27675        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
27676    }
27677}
27678#[doc = "Transpose vectors"]
27679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"]
27680#[inline]
27681#[cfg(target_endian = "little")]
27682#[target_feature(enable = "neon")]
27683#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27684#[cfg_attr(
27685    all(test, not(target_env = "msvc"), target_endian = "little"),
27686    assert_instr(trn2)
27687)]
27688pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
27689    unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
27690}
27691#[doc = "Transpose vectors"]
27692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"]
27693#[inline]
27694#[cfg(target_endian = "big")]
27695#[target_feature(enable = "neon")]
27696#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27697#[cfg_attr(
27698    all(test, not(target_env = "msvc"), target_endian = "little"),
27699    assert_instr(trn2)
27700)]
27701pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
27702    unsafe {
27703        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
27704        let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
27705        let ret_val: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
27706        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
27707    }
27708}
27709#[doc = "Transpose vectors"]
27710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"]
27711#[inline]
27712#[cfg(target_endian = "little")]
27713#[target_feature(enable = "neon")]
27714#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27715#[cfg_attr(
27716    all(test, not(target_env = "msvc"), target_endian = "little"),
27717    assert_instr(trn2)
27718)]
27719pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
27720    unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
27721}
27722#[doc = "Transpose vectors"]
27723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"]
27724#[inline]
27725#[cfg(target_endian = "big")]
27726#[target_feature(enable = "neon")]
27727#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27728#[cfg_attr(
27729    all(test, not(target_env = "msvc"), target_endian = "little"),
27730    assert_instr(trn2)
27731)]
27732pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
27733    unsafe {
27734        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
27735        let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
27736        let ret_val: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
27737        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
27738    }
27739}
27740#[doc = "Transpose vectors"]
27741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"]
27742#[inline]
27743#[cfg(target_endian = "little")]
27744#[target_feature(enable = "neon")]
27745#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27746#[cfg_attr(
27747    all(test, not(target_env = "msvc"), target_endian = "little"),
27748    assert_instr(trn2)
27749)]
27750pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
27751    unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
27752}
27753#[doc = "Transpose vectors"]
27754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"]
27755#[inline]
27756#[cfg(target_endian = "big")]
27757#[target_feature(enable = "neon")]
27758#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27759#[cfg_attr(
27760    all(test, not(target_env = "msvc"), target_endian = "little"),
27761    assert_instr(trn2)
27762)]
27763pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
27764    unsafe {
27765        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
27766        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
27767        let ret_val: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
27768        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
27769    }
27770}
27771#[doc = "Transpose vectors"]
27772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"]
27773#[inline]
27774#[cfg(target_endian = "little")]
27775#[target_feature(enable = "neon")]
27776#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27777#[cfg_attr(
27778    all(test, not(target_env = "msvc"), target_endian = "little"),
27779    assert_instr(trn2)
27780)]
27781pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
27782    unsafe {
27783        simd_shuffle!(
27784            a,
27785            b,
27786            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
27787        )
27788    }
27789}
27790#[doc = "Transpose vectors"]
27791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"]
27792#[inline]
27793#[cfg(target_endian = "big")]
27794#[target_feature(enable = "neon")]
27795#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27796#[cfg_attr(
27797    all(test, not(target_env = "msvc"), target_endian = "little"),
27798    assert_instr(trn2)
27799)]
27800pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
27801    unsafe {
27802        let a: uint8x16_t =
27803            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27804        let b: uint8x16_t =
27805            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27806        let ret_val: uint8x16_t = simd_shuffle!(
27807            a,
27808            b,
27809            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
27810        );
27811        simd_shuffle!(
27812            ret_val,
27813            ret_val,
27814            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27815        )
27816    }
27817}
27818#[doc = "Transpose vectors"]
27819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"]
27820#[inline]
27821#[cfg(target_endian = "little")]
27822#[target_feature(enable = "neon")]
27823#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27824#[cfg_attr(
27825    all(test, not(target_env = "msvc"), target_endian = "little"),
27826    assert_instr(trn2)
27827)]
27828pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
27829    unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
27830}
27831#[doc = "Transpose vectors"]
27832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"]
27833#[inline]
27834#[cfg(target_endian = "big")]
27835#[target_feature(enable = "neon")]
27836#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27837#[cfg_attr(
27838    all(test, not(target_env = "msvc"), target_endian = "little"),
27839    assert_instr(trn2)
27840)]
27841pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
27842    unsafe {
27843        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
27844        let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
27845        let ret_val: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
27846        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
27847    }
27848}
27849#[doc = "Transpose vectors"]
27850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"]
27851#[inline]
27852#[cfg(target_endian = "little")]
27853#[target_feature(enable = "neon")]
27854#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27855#[cfg_attr(
27856    all(test, not(target_env = "msvc"), target_endian = "little"),
27857    assert_instr(trn2)
27858)]
27859pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
27860    unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
27861}
27862#[doc = "Transpose vectors"]
27863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"]
27864#[inline]
27865#[cfg(target_endian = "big")]
27866#[target_feature(enable = "neon")]
27867#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27868#[cfg_attr(
27869    all(test, not(target_env = "msvc"), target_endian = "little"),
27870    assert_instr(trn2)
27871)]
27872pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
27873    unsafe {
27874        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
27875        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
27876        let ret_val: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
27877        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
27878    }
27879}
27880#[doc = "Transpose vectors"]
27881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"]
27882#[inline]
27883#[cfg(target_endian = "little")]
27884#[target_feature(enable = "neon")]
27885#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27886#[cfg_attr(
27887    all(test, not(target_env = "msvc"), target_endian = "little"),
27888    assert_instr(trn2)
27889)]
27890pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
27891    unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
27892}
27893#[doc = "Transpose vectors"]
27894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"]
27895#[inline]
27896#[cfg(target_endian = "big")]
27897#[target_feature(enable = "neon")]
27898#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27899#[cfg_attr(
27900    all(test, not(target_env = "msvc"), target_endian = "little"),
27901    assert_instr(trn2)
27902)]
27903pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
27904    unsafe {
27905        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
27906        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
27907        let ret_val: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
27908        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
27909    }
27910}
27911#[doc = "Transpose vectors"]
27912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"]
27913#[inline]
27914#[cfg(target_endian = "little")]
27915#[target_feature(enable = "neon")]
27916#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27917#[cfg_attr(
27918    all(test, not(target_env = "msvc"), target_endian = "little"),
27919    assert_instr(trn2)
27920)]
27921pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
27922    unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
27923}
27924#[doc = "Transpose vectors"]
27925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"]
27926#[inline]
27927#[cfg(target_endian = "big")]
27928#[target_feature(enable = "neon")]
27929#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27930#[cfg_attr(
27931    all(test, not(target_env = "msvc"), target_endian = "little"),
27932    assert_instr(trn2)
27933)]
27934pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
27935    unsafe {
27936        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
27937        let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
27938        let ret_val: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
27939        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
27940    }
27941}
27942#[doc = "Transpose vectors"]
27943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"]
27944#[inline]
27945#[cfg(target_endian = "little")]
27946#[target_feature(enable = "neon")]
27947#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27948#[cfg_attr(
27949    all(test, not(target_env = "msvc"), target_endian = "little"),
27950    assert_instr(trn2)
27951)]
27952pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
27953    unsafe {
27954        simd_shuffle!(
27955            a,
27956            b,
27957            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
27958        )
27959    }
27960}
27961#[doc = "Transpose vectors"]
27962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"]
27963#[inline]
27964#[cfg(target_endian = "big")]
27965#[target_feature(enable = "neon")]
27966#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27967#[cfg_attr(
27968    all(test, not(target_env = "msvc"), target_endian = "little"),
27969    assert_instr(trn2)
27970)]
27971pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
27972    unsafe {
27973        let a: poly8x16_t =
27974            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27975        let b: poly8x16_t =
27976            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
27977        let ret_val: poly8x16_t = simd_shuffle!(
27978            a,
27979            b,
27980            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
27981        );
27982        simd_shuffle!(
27983            ret_val,
27984            ret_val,
27985            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27986        )
27987    }
27988}
27989#[doc = "Transpose vectors"]
27990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"]
27991#[inline]
27992#[cfg(target_endian = "little")]
27993#[target_feature(enable = "neon")]
27994#[stable(feature = "neon_intrinsics", since = "1.59.0")]
27995#[cfg_attr(
27996    all(test, not(target_env = "msvc"), target_endian = "little"),
27997    assert_instr(trn2)
27998)]
27999pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
28000    unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
28001}
28002#[doc = "Transpose vectors"]
28003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"]
28004#[inline]
28005#[cfg(target_endian = "big")]
28006#[target_feature(enable = "neon")]
28007#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28008#[cfg_attr(
28009    all(test, not(target_env = "msvc"), target_endian = "little"),
28010    assert_instr(trn2)
28011)]
28012pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
28013    unsafe {
28014        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
28015        let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
28016        let ret_val: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
28017        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
28018    }
28019}
28020#[doc = "Transpose vectors"]
28021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"]
28022#[inline]
28023#[cfg(target_endian = "little")]
28024#[target_feature(enable = "neon")]
28025#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28026#[cfg_attr(
28027    all(test, not(target_env = "msvc"), target_endian = "little"),
28028    assert_instr(trn2)
28029)]
28030pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
28031    unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
28032}
28033#[doc = "Transpose vectors"]
28034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"]
28035#[inline]
28036#[cfg(target_endian = "big")]
28037#[target_feature(enable = "neon")]
28038#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28039#[cfg_attr(
28040    all(test, not(target_env = "msvc"), target_endian = "little"),
28041    assert_instr(trn2)
28042)]
28043pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
28044    unsafe {
28045        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
28046        let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
28047        let ret_val: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
28048        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
28049    }
28050}
28051#[doc = "Signed compare bitwise Test bits nonzero"]
28052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)"]
28053#[inline]
28054#[target_feature(enable = "neon")]
28055#[cfg_attr(test, assert_instr(cmtst))]
28056#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28057pub fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
28058    unsafe {
28059        let c: int64x1_t = simd_and(a, b);
28060        let d: i64x1 = i64x1::new(0);
28061        simd_ne(c, transmute(d))
28062    }
28063}
28064#[doc = "Signed compare bitwise Test bits nonzero"]
28065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)"]
28066#[inline]
28067#[target_feature(enable = "neon")]
28068#[cfg_attr(test, assert_instr(cmtst))]
28069#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28070pub fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
28071    unsafe {
28072        let c: int64x2_t = simd_and(a, b);
28073        let d: i64x2 = i64x2::new(0, 0);
28074        simd_ne(c, transmute(d))
28075    }
28076}
28077#[doc = "Signed compare bitwise Test bits nonzero"]
28078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64)"]
28079#[inline]
28080#[target_feature(enable = "neon")]
28081#[cfg_attr(test, assert_instr(cmtst))]
28082#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28083pub fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t {
28084    unsafe {
28085        let c: poly64x1_t = simd_and(a, b);
28086        let d: i64x1 = i64x1::new(0);
28087        simd_ne(c, transmute(d))
28088    }
28089}
28090#[doc = "Signed compare bitwise Test bits nonzero"]
28091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64)"]
28092#[inline]
28093#[target_feature(enable = "neon")]
28094#[cfg_attr(test, assert_instr(cmtst))]
28095#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28096pub fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
28097    unsafe {
28098        let c: poly64x2_t = simd_and(a, b);
28099        let d: i64x2 = i64x2::new(0, 0);
28100        simd_ne(c, transmute(d))
28101    }
28102}
28103#[doc = "Unsigned compare bitwise Test bits nonzero"]
28104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)"]
28105#[inline]
28106#[target_feature(enable = "neon")]
28107#[cfg_attr(test, assert_instr(cmtst))]
28108#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28109pub fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
28110    unsafe {
28111        let c: uint64x1_t = simd_and(a, b);
28112        let d: u64x1 = u64x1::new(0);
28113        simd_ne(c, transmute(d))
28114    }
28115}
28116#[doc = "Unsigned compare bitwise Test bits nonzero"]
28117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)"]
28118#[inline]
28119#[target_feature(enable = "neon")]
28120#[cfg_attr(test, assert_instr(cmtst))]
28121#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28122pub fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
28123    unsafe {
28124        let c: uint64x2_t = simd_and(a, b);
28125        let d: u64x2 = u64x2::new(0, 0);
28126        simd_ne(c, transmute(d))
28127    }
28128}
28129#[doc = "Compare bitwise test bits nonzero"]
28130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64)"]
28131#[inline]
28132#[target_feature(enable = "neon")]
28133#[cfg_attr(test, assert_instr(tst))]
28134#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28135pub fn vtstd_s64(a: i64, b: i64) -> u64 {
28136    unsafe { transmute(vtst_s64(transmute(a), transmute(b))) }
28137}
28138#[doc = "Compare bitwise test bits nonzero"]
28139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64)"]
28140#[inline]
28141#[target_feature(enable = "neon")]
28142#[cfg_attr(test, assert_instr(tst))]
28143#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28144pub fn vtstd_u64(a: u64, b: u64) -> u64 {
28145    unsafe { transmute(vtst_u64(transmute(a), transmute(b))) }
28146}
28147#[doc = "Signed saturating Accumulate of Unsigned value."]
28148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s8)"]
28149#[inline]
28150#[target_feature(enable = "neon")]
28151#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28152#[cfg_attr(test, assert_instr(suqadd))]
28153pub fn vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t {
28154    unsafe extern "unadjusted" {
28155        #[cfg_attr(
28156            any(target_arch = "aarch64", target_arch = "arm64ec"),
28157            link_name = "llvm.aarch64.neon.suqadd.v8i8"
28158        )]
28159        fn _vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t;
28160    }
28161    unsafe { _vuqadd_s8(a, b) }
28162}
28163#[doc = "Signed saturating Accumulate of Unsigned value."]
28164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s8)"]
28165#[inline]
28166#[target_feature(enable = "neon")]
28167#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28168#[cfg_attr(test, assert_instr(suqadd))]
28169pub fn vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
28170    unsafe extern "unadjusted" {
28171        #[cfg_attr(
28172            any(target_arch = "aarch64", target_arch = "arm64ec"),
28173            link_name = "llvm.aarch64.neon.suqadd.v16i8"
28174        )]
28175        fn _vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t;
28176    }
28177    unsafe { _vuqaddq_s8(a, b) }
28178}
28179#[doc = "Signed saturating Accumulate of Unsigned value."]
28180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s16)"]
28181#[inline]
28182#[target_feature(enable = "neon")]
28183#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28184#[cfg_attr(test, assert_instr(suqadd))]
28185pub fn vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t {
28186    unsafe extern "unadjusted" {
28187        #[cfg_attr(
28188            any(target_arch = "aarch64", target_arch = "arm64ec"),
28189            link_name = "llvm.aarch64.neon.suqadd.v4i16"
28190        )]
28191        fn _vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t;
28192    }
28193    unsafe { _vuqadd_s16(a, b) }
28194}
28195#[doc = "Signed saturating Accumulate of Unsigned value."]
28196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s16)"]
28197#[inline]
28198#[target_feature(enable = "neon")]
28199#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28200#[cfg_attr(test, assert_instr(suqadd))]
28201pub fn vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t {
28202    unsafe extern "unadjusted" {
28203        #[cfg_attr(
28204            any(target_arch = "aarch64", target_arch = "arm64ec"),
28205            link_name = "llvm.aarch64.neon.suqadd.v8i16"
28206        )]
28207        fn _vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t;
28208    }
28209    unsafe { _vuqaddq_s16(a, b) }
28210}
28211#[doc = "Signed saturating Accumulate of Unsigned value."]
28212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s32)"]
28213#[inline]
28214#[target_feature(enable = "neon")]
28215#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28216#[cfg_attr(test, assert_instr(suqadd))]
28217pub fn vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t {
28218    unsafe extern "unadjusted" {
28219        #[cfg_attr(
28220            any(target_arch = "aarch64", target_arch = "arm64ec"),
28221            link_name = "llvm.aarch64.neon.suqadd.v2i32"
28222        )]
28223        fn _vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t;
28224    }
28225    unsafe { _vuqadd_s32(a, b) }
28226}
28227#[doc = "Signed saturating Accumulate of Unsigned value."]
28228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s32)"]
28229#[inline]
28230#[target_feature(enable = "neon")]
28231#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28232#[cfg_attr(test, assert_instr(suqadd))]
28233pub fn vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t {
28234    unsafe extern "unadjusted" {
28235        #[cfg_attr(
28236            any(target_arch = "aarch64", target_arch = "arm64ec"),
28237            link_name = "llvm.aarch64.neon.suqadd.v4i32"
28238        )]
28239        fn _vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t;
28240    }
28241    unsafe { _vuqaddq_s32(a, b) }
28242}
28243#[doc = "Signed saturating Accumulate of Unsigned value."]
28244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s64)"]
28245#[inline]
28246#[target_feature(enable = "neon")]
28247#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28248#[cfg_attr(test, assert_instr(suqadd))]
28249pub fn vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t {
28250    unsafe extern "unadjusted" {
28251        #[cfg_attr(
28252            any(target_arch = "aarch64", target_arch = "arm64ec"),
28253            link_name = "llvm.aarch64.neon.suqadd.v1i64"
28254        )]
28255        fn _vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t;
28256    }
28257    unsafe { _vuqadd_s64(a, b) }
28258}
28259#[doc = "Signed saturating Accumulate of Unsigned value."]
28260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s64)"]
28261#[inline]
28262#[target_feature(enable = "neon")]
28263#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28264#[cfg_attr(test, assert_instr(suqadd))]
28265pub fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t {
28266    unsafe extern "unadjusted" {
28267        #[cfg_attr(
28268            any(target_arch = "aarch64", target_arch = "arm64ec"),
28269            link_name = "llvm.aarch64.neon.suqadd.v2i64"
28270        )]
28271        fn _vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t;
28272    }
28273    unsafe { _vuqaddq_s64(a, b) }
28274}
28275#[doc = "Signed saturating accumulate of unsigned value"]
28276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)"]
28277#[inline]
28278#[target_feature(enable = "neon")]
28279#[cfg_attr(test, assert_instr(suqadd))]
28280#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28281pub fn vuqaddb_s8(a: i8, b: u8) -> i8 {
28282    vget_lane_s8::<0>(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)))
28283}
28284#[doc = "Signed saturating accumulate of unsigned value"]
28285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"]
28286#[inline]
28287#[target_feature(enable = "neon")]
28288#[cfg_attr(test, assert_instr(suqadd))]
28289#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28290pub fn vuqaddh_s16(a: i16, b: u16) -> i16 {
28291    vget_lane_s16::<0>(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)))
28292}
28293#[doc = "Signed saturating accumulate of unsigned value"]
28294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"]
28295#[inline]
28296#[target_feature(enable = "neon")]
28297#[cfg_attr(test, assert_instr(suqadd))]
28298#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28299pub fn vuqaddd_s64(a: i64, b: u64) -> i64 {
28300    unsafe extern "unadjusted" {
28301        #[cfg_attr(
28302            any(target_arch = "aarch64", target_arch = "arm64ec"),
28303            link_name = "llvm.aarch64.neon.suqadd.i64"
28304        )]
28305        fn _vuqaddd_s64(a: i64, b: u64) -> i64;
28306    }
28307    unsafe { _vuqaddd_s64(a, b) }
28308}
28309#[doc = "Signed saturating accumulate of unsigned value"]
28310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)"]
28311#[inline]
28312#[target_feature(enable = "neon")]
28313#[cfg_attr(test, assert_instr(suqadd))]
28314#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28315pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
28316    unsafe extern "unadjusted" {
28317        #[cfg_attr(
28318            any(target_arch = "aarch64", target_arch = "arm64ec"),
28319            link_name = "llvm.aarch64.neon.suqadd.i32"
28320        )]
28321        fn _vuqadds_s32(a: i32, b: u32) -> i32;
28322    }
28323    unsafe { _vuqadds_s32(a, b) }
28324}
28325#[doc = "Unzip vectors"]
28326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"]
28327#[inline]
28328#[cfg(target_endian = "little")]
28329#[target_feature(enable = "neon,fp16")]
28330#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
28331#[cfg(not(target_arch = "arm64ec"))]
28332#[cfg_attr(
28333    all(test, not(target_env = "msvc"), target_endian = "little"),
28334    assert_instr(uzp1)
28335)]
28336pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28337    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
28338}
28339#[doc = "Unzip vectors"]
28340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"]
28341#[inline]
28342#[cfg(target_endian = "big")]
28343#[target_feature(enable = "neon,fp16")]
28344#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
28345#[cfg(not(target_arch = "arm64ec"))]
28346#[cfg_attr(
28347    all(test, not(target_env = "msvc"), target_endian = "little"),
28348    assert_instr(uzp1)
28349)]
28350pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28351    unsafe {
28352        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
28353        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
28354        let ret_val: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
28355        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
28356    }
28357}
28358#[doc = "Unzip vectors"]
28359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"]
28360#[inline]
28361#[cfg(target_endian = "little")]
28362#[target_feature(enable = "neon,fp16")]
28363#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
28364#[cfg(not(target_arch = "arm64ec"))]
28365#[cfg_attr(
28366    all(test, not(target_env = "msvc"), target_endian = "little"),
28367    assert_instr(uzp1)
28368)]
28369pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28370    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
28371}
28372#[doc = "Unzip vectors"]
28373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"]
28374#[inline]
28375#[cfg(target_endian = "big")]
28376#[target_feature(enable = "neon,fp16")]
28377#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
28378#[cfg(not(target_arch = "arm64ec"))]
28379#[cfg_attr(
28380    all(test, not(target_env = "msvc"), target_endian = "little"),
28381    assert_instr(uzp1)
28382)]
28383pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28384    unsafe {
28385        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
28386        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
28387        let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
28388        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
28389    }
28390}
28391#[doc = "Unzip vectors"]
28392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"]
28393#[inline]
28394#[cfg(target_endian = "little")]
28395#[target_feature(enable = "neon")]
28396#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28397#[cfg_attr(
28398    all(test, not(target_env = "msvc"), target_endian = "little"),
28399    assert_instr(zip1)
28400)]
28401pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28402    unsafe { simd_shuffle!(a, b, [0, 2]) }
28403}
28404#[doc = "Unzip vectors"]
28405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"]
28406#[inline]
28407#[cfg(target_endian = "big")]
28408#[target_feature(enable = "neon")]
28409#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28410#[cfg_attr(
28411    all(test, not(target_env = "msvc"), target_endian = "little"),
28412    assert_instr(zip1)
28413)]
28414pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28415    unsafe {
28416        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
28417        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
28418        let ret_val: float32x2_t = simd_shuffle!(a, b, [0, 2]);
28419        simd_shuffle!(ret_val, ret_val, [1, 0])
28420    }
28421}
28422#[doc = "Unzip vectors"]
28423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"]
28424#[inline]
28425#[cfg(target_endian = "little")]
28426#[target_feature(enable = "neon")]
28427#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28428#[cfg_attr(
28429    all(test, not(target_env = "msvc"), target_endian = "little"),
28430    assert_instr(zip1)
28431)]
28432pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
28433    unsafe { simd_shuffle!(a, b, [0, 2]) }
28434}
28435#[doc = "Unzip vectors"]
28436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"]
28437#[inline]
28438#[cfg(target_endian = "big")]
28439#[target_feature(enable = "neon")]
28440#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28441#[cfg_attr(
28442    all(test, not(target_env = "msvc"), target_endian = "little"),
28443    assert_instr(zip1)
28444)]
28445pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
28446    unsafe {
28447        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
28448        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
28449        let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 2]);
28450        simd_shuffle!(ret_val, ret_val, [1, 0])
28451    }
28452}
28453#[doc = "Unzip vectors"]
28454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"]
28455#[inline]
28456#[cfg(target_endian = "little")]
28457#[target_feature(enable = "neon")]
28458#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28459#[cfg_attr(
28460    all(test, not(target_env = "msvc"), target_endian = "little"),
28461    assert_instr(zip1)
28462)]
28463pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
28464    unsafe { simd_shuffle!(a, b, [0, 2]) }
28465}
28466#[doc = "Unzip vectors"]
28467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"]
28468#[inline]
28469#[cfg(target_endian = "big")]
28470#[target_feature(enable = "neon")]
28471#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28472#[cfg_attr(
28473    all(test, not(target_env = "msvc"), target_endian = "little"),
28474    assert_instr(zip1)
28475)]
28476pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
28477    unsafe {
28478        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
28479        let b: int32x2_t = simd_shuffle!(b, b, [1, 0]);
28480        let ret_val: int32x2_t = simd_shuffle!(a, b, [0, 2]);
28481        simd_shuffle!(ret_val, ret_val, [1, 0])
28482    }
28483}
28484#[doc = "Unzip vectors"]
28485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"]
28486#[inline]
28487#[cfg(target_endian = "little")]
28488#[target_feature(enable = "neon")]
28489#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28490#[cfg_attr(
28491    all(test, not(target_env = "msvc"), target_endian = "little"),
28492    assert_instr(zip1)
28493)]
28494pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
28495    unsafe { simd_shuffle!(a, b, [0, 2]) }
28496}
28497#[doc = "Unzip vectors"]
28498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"]
28499#[inline]
28500#[cfg(target_endian = "big")]
28501#[target_feature(enable = "neon")]
28502#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28503#[cfg_attr(
28504    all(test, not(target_env = "msvc"), target_endian = "little"),
28505    assert_instr(zip1)
28506)]
28507pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
28508    unsafe {
28509        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
28510        let b: int64x2_t = simd_shuffle!(b, b, [1, 0]);
28511        let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 2]);
28512        simd_shuffle!(ret_val, ret_val, [1, 0])
28513    }
28514}
28515#[doc = "Unzip vectors"]
28516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"]
28517#[inline]
28518#[cfg(target_endian = "little")]
28519#[target_feature(enable = "neon")]
28520#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28521#[cfg_attr(
28522    all(test, not(target_env = "msvc"), target_endian = "little"),
28523    assert_instr(zip1)
28524)]
28525pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
28526    unsafe { simd_shuffle!(a, b, [0, 2]) }
28527}
28528#[doc = "Unzip vectors"]
28529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"]
28530#[inline]
28531#[cfg(target_endian = "big")]
28532#[target_feature(enable = "neon")]
28533#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28534#[cfg_attr(
28535    all(test, not(target_env = "msvc"), target_endian = "little"),
28536    assert_instr(zip1)
28537)]
28538pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
28539    unsafe {
28540        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
28541        let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]);
28542        let ret_val: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
28543        simd_shuffle!(ret_val, ret_val, [1, 0])
28544    }
28545}
28546#[doc = "Unzip vectors"]
28547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"]
28548#[inline]
28549#[cfg(target_endian = "little")]
28550#[target_feature(enable = "neon")]
28551#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28552#[cfg_attr(
28553    all(test, not(target_env = "msvc"), target_endian = "little"),
28554    assert_instr(zip1)
28555)]
28556pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
28557    unsafe { simd_shuffle!(a, b, [0, 2]) }
28558}
28559#[doc = "Unzip vectors"]
28560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"]
28561#[inline]
28562#[cfg(target_endian = "big")]
28563#[target_feature(enable = "neon")]
28564#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28565#[cfg_attr(
28566    all(test, not(target_env = "msvc"), target_endian = "little"),
28567    assert_instr(zip1)
28568)]
28569pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
28570    unsafe {
28571        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
28572        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
28573        let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 2]);
28574        simd_shuffle!(ret_val, ret_val, [1, 0])
28575    }
28576}
28577#[doc = "Unzip vectors"]
28578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"]
28579#[inline]
28580#[cfg(target_endian = "little")]
28581#[target_feature(enable = "neon")]
28582#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28583#[cfg_attr(
28584    all(test, not(target_env = "msvc"), target_endian = "little"),
28585    assert_instr(zip1)
28586)]
28587pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
28588    unsafe { simd_shuffle!(a, b, [0, 2]) }
28589}
28590#[doc = "Unzip vectors"]
28591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"]
28592#[inline]
28593#[cfg(target_endian = "big")]
28594#[target_feature(enable = "neon")]
28595#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28596#[cfg_attr(
28597    all(test, not(target_env = "msvc"), target_endian = "little"),
28598    assert_instr(zip1)
28599)]
28600pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
28601    unsafe {
28602        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
28603        let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]);
28604        let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 2]);
28605        simd_shuffle!(ret_val, ret_val, [1, 0])
28606    }
28607}
28608#[doc = "Unzip vectors"]
28609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"]
28610#[inline]
28611#[cfg(target_endian = "little")]
28612#[target_feature(enable = "neon")]
28613#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28614#[cfg_attr(
28615    all(test, not(target_env = "msvc"), target_endian = "little"),
28616    assert_instr(uzp1)
28617)]
28618pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28619    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
28620}
28621#[doc = "Unzip vectors"]
28622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"]
28623#[inline]
28624#[cfg(target_endian = "big")]
28625#[target_feature(enable = "neon")]
28626#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28627#[cfg_attr(
28628    all(test, not(target_env = "msvc"), target_endian = "little"),
28629    assert_instr(uzp1)
28630)]
28631pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28632    unsafe {
28633        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
28634        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
28635        let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
28636        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
28637    }
28638}
28639#[doc = "Unzip vectors"]
28640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"]
28641#[inline]
28642#[cfg(target_endian = "little")]
28643#[target_feature(enable = "neon")]
28644#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28645#[cfg_attr(
28646    all(test, not(target_env = "msvc"), target_endian = "little"),
28647    assert_instr(uzp1)
28648)]
28649pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
28650    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
28651}
28652#[doc = "Unzip vectors"]
28653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"]
28654#[inline]
28655#[cfg(target_endian = "big")]
28656#[target_feature(enable = "neon")]
28657#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28658#[cfg_attr(
28659    all(test, not(target_env = "msvc"), target_endian = "little"),
28660    assert_instr(uzp1)
28661)]
28662pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
28663    unsafe {
28664        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
28665        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
28666        let ret_val: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
28667        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
28668    }
28669}
28670#[doc = "Unzip vectors"]
28671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"]
28672#[inline]
28673#[cfg(target_endian = "little")]
28674#[target_feature(enable = "neon")]
28675#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28676#[cfg_attr(
28677    all(test, not(target_env = "msvc"), target_endian = "little"),
28678    assert_instr(uzp1)
28679)]
28680pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
28681    unsafe {
28682        simd_shuffle!(
28683            a,
28684            b,
28685            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
28686        )
28687    }
28688}
28689#[doc = "Unzip vectors"]
28690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"]
28691#[inline]
28692#[cfg(target_endian = "big")]
28693#[target_feature(enable = "neon")]
28694#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28695#[cfg_attr(
28696    all(test, not(target_env = "msvc"), target_endian = "little"),
28697    assert_instr(uzp1)
28698)]
28699pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
28700    unsafe {
28701        let a: int8x16_t =
28702            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
28703        let b: int8x16_t =
28704            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
28705        let ret_val: int8x16_t = simd_shuffle!(
28706            a,
28707            b,
28708            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
28709        );
28710        simd_shuffle!(
28711            ret_val,
28712            ret_val,
28713            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
28714        )
28715    }
28716}
28717#[doc = "Unzip vectors"]
28718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"]
28719#[inline]
28720#[cfg(target_endian = "little")]
28721#[target_feature(enable = "neon")]
28722#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28723#[cfg_attr(
28724    all(test, not(target_env = "msvc"), target_endian = "little"),
28725    assert_instr(uzp1)
28726)]
28727pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
28728    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
28729}
28730#[doc = "Unzip vectors"]
28731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"]
28732#[inline]
28733#[cfg(target_endian = "big")]
28734#[target_feature(enable = "neon")]
28735#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28736#[cfg_attr(
28737    all(test, not(target_env = "msvc"), target_endian = "little"),
28738    assert_instr(uzp1)
28739)]
28740pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
28741    unsafe {
28742        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
28743        let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
28744        let ret_val: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
28745        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
28746    }
28747}
28748#[doc = "Unzip vectors"]
28749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"]
28750#[inline]
28751#[cfg(target_endian = "little")]
28752#[target_feature(enable = "neon")]
28753#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28754#[cfg_attr(
28755    all(test, not(target_env = "msvc"), target_endian = "little"),
28756    assert_instr(uzp1)
28757)]
28758pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
28759    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
28760}
28761#[doc = "Unzip vectors"]
28762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"]
28763#[inline]
28764#[cfg(target_endian = "big")]
28765#[target_feature(enable = "neon")]
28766#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28767#[cfg_attr(
28768    all(test, not(target_env = "msvc"), target_endian = "little"),
28769    assert_instr(uzp1)
28770)]
28771pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
28772    unsafe {
28773        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
28774        let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
28775        let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
28776        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
28777    }
28778}
28779#[doc = "Unzip vectors"]
28780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"]
28781#[inline]
28782#[cfg(target_endian = "little")]
28783#[target_feature(enable = "neon")]
28784#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28785#[cfg_attr(
28786    all(test, not(target_env = "msvc"), target_endian = "little"),
28787    assert_instr(uzp1)
28788)]
28789pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
28790    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
28791}
28792#[doc = "Unzip vectors"]
28793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"]
28794#[inline]
28795#[cfg(target_endian = "big")]
28796#[target_feature(enable = "neon")]
28797#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28798#[cfg_attr(
28799    all(test, not(target_env = "msvc"), target_endian = "little"),
28800    assert_instr(uzp1)
28801)]
28802pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
28803    unsafe {
28804        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
28805        let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
28806        let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
28807        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
28808    }
28809}
28810#[doc = "Unzip vectors"]
28811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"]
28812#[inline]
28813#[cfg(target_endian = "little")]
28814#[target_feature(enable = "neon")]
28815#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28816#[cfg_attr(
28817    all(test, not(target_env = "msvc"), target_endian = "little"),
28818    assert_instr(uzp1)
28819)]
28820pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
28821    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
28822}
28823#[doc = "Unzip vectors"]
28824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"]
28825#[inline]
28826#[cfg(target_endian = "big")]
28827#[target_feature(enable = "neon")]
28828#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28829#[cfg_attr(
28830    all(test, not(target_env = "msvc"), target_endian = "little"),
28831    assert_instr(uzp1)
28832)]
28833pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
28834    unsafe {
28835        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
28836        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
28837        let ret_val: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
28838        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
28839    }
28840}
28841#[doc = "Unzip vectors"]
28842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"]
28843#[inline]
28844#[cfg(target_endian = "little")]
28845#[target_feature(enable = "neon")]
28846#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28847#[cfg_attr(
28848    all(test, not(target_env = "msvc"), target_endian = "little"),
28849    assert_instr(uzp1)
28850)]
28851pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
28852    unsafe {
28853        simd_shuffle!(
28854            a,
28855            b,
28856            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
28857        )
28858    }
28859}
28860#[doc = "Unzip vectors"]
28861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"]
28862#[inline]
28863#[cfg(target_endian = "big")]
28864#[target_feature(enable = "neon")]
28865#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28866#[cfg_attr(
28867    all(test, not(target_env = "msvc"), target_endian = "little"),
28868    assert_instr(uzp1)
28869)]
28870pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
28871    unsafe {
28872        let a: uint8x16_t =
28873            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
28874        let b: uint8x16_t =
28875            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
28876        let ret_val: uint8x16_t = simd_shuffle!(
28877            a,
28878            b,
28879            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
28880        );
28881        simd_shuffle!(
28882            ret_val,
28883            ret_val,
28884            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
28885        )
28886    }
28887}
28888#[doc = "Unzip vectors"]
28889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"]
28890#[inline]
28891#[cfg(target_endian = "little")]
28892#[target_feature(enable = "neon")]
28893#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28894#[cfg_attr(
28895    all(test, not(target_env = "msvc"), target_endian = "little"),
28896    assert_instr(uzp1)
28897)]
28898pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
28899    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
28900}
28901#[doc = "Unzip vectors"]
28902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"]
28903#[inline]
28904#[cfg(target_endian = "big")]
28905#[target_feature(enable = "neon")]
28906#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28907#[cfg_attr(
28908    all(test, not(target_env = "msvc"), target_endian = "little"),
28909    assert_instr(uzp1)
28910)]
28911pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
28912    unsafe {
28913        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
28914        let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
28915        let ret_val: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
28916        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
28917    }
28918}
28919#[doc = "Unzip vectors"]
28920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"]
28921#[inline]
28922#[cfg(target_endian = "little")]
28923#[target_feature(enable = "neon")]
28924#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28925#[cfg_attr(
28926    all(test, not(target_env = "msvc"), target_endian = "little"),
28927    assert_instr(uzp1)
28928)]
28929pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
28930    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
28931}
28932#[doc = "Unzip vectors"]
28933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"]
28934#[inline]
28935#[cfg(target_endian = "big")]
28936#[target_feature(enable = "neon")]
28937#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28938#[cfg_attr(
28939    all(test, not(target_env = "msvc"), target_endian = "little"),
28940    assert_instr(uzp1)
28941)]
28942pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
28943    unsafe {
28944        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
28945        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
28946        let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
28947        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
28948    }
28949}
28950#[doc = "Unzip vectors"]
28951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"]
28952#[inline]
28953#[cfg(target_endian = "little")]
28954#[target_feature(enable = "neon")]
28955#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28956#[cfg_attr(
28957    all(test, not(target_env = "msvc"), target_endian = "little"),
28958    assert_instr(uzp1)
28959)]
28960pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
28961    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
28962}
28963#[doc = "Unzip vectors"]
28964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"]
28965#[inline]
28966#[cfg(target_endian = "big")]
28967#[target_feature(enable = "neon")]
28968#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28969#[cfg_attr(
28970    all(test, not(target_env = "msvc"), target_endian = "little"),
28971    assert_instr(uzp1)
28972)]
28973pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
28974    unsafe {
28975        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
28976        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
28977        let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
28978        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
28979    }
28980}
28981#[doc = "Unzip vectors"]
28982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"]
28983#[inline]
28984#[cfg(target_endian = "little")]
28985#[target_feature(enable = "neon")]
28986#[stable(feature = "neon_intrinsics", since = "1.59.0")]
28987#[cfg_attr(
28988    all(test, not(target_env = "msvc"), target_endian = "little"),
28989    assert_instr(uzp1)
28990)]
28991pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
28992    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
28993}
28994#[doc = "Unzip vectors"]
28995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"]
28996#[inline]
28997#[cfg(target_endian = "big")]
28998#[target_feature(enable = "neon")]
28999#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29000#[cfg_attr(
29001    all(test, not(target_env = "msvc"), target_endian = "little"),
29002    assert_instr(uzp1)
29003)]
29004pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
29005    unsafe {
29006        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29007        let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29008        let ret_val: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
29009        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29010    }
29011}
29012#[doc = "Unzip vectors"]
29013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"]
29014#[inline]
29015#[cfg(target_endian = "little")]
29016#[target_feature(enable = "neon")]
29017#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29018#[cfg_attr(
29019    all(test, not(target_env = "msvc"), target_endian = "little"),
29020    assert_instr(uzp1)
29021)]
29022pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
29023    unsafe {
29024        simd_shuffle!(
29025            a,
29026            b,
29027            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
29028        )
29029    }
29030}
29031#[doc = "Unzip vectors"]
29032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"]
29033#[inline]
29034#[cfg(target_endian = "big")]
29035#[target_feature(enable = "neon")]
29036#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29037#[cfg_attr(
29038    all(test, not(target_env = "msvc"), target_endian = "little"),
29039    assert_instr(uzp1)
29040)]
29041pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
29042    unsafe {
29043        let a: poly8x16_t =
29044            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
29045        let b: poly8x16_t =
29046            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
29047        let ret_val: poly8x16_t = simd_shuffle!(
29048            a,
29049            b,
29050            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
29051        );
29052        simd_shuffle!(
29053            ret_val,
29054            ret_val,
29055            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
29056        )
29057    }
29058}
29059#[doc = "Unzip vectors"]
29060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"]
29061#[inline]
29062#[cfg(target_endian = "little")]
29063#[target_feature(enable = "neon")]
29064#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29065#[cfg_attr(
29066    all(test, not(target_env = "msvc"), target_endian = "little"),
29067    assert_instr(uzp1)
29068)]
29069pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
29070    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
29071}
29072#[doc = "Unzip vectors"]
29073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"]
29074#[inline]
29075#[cfg(target_endian = "big")]
29076#[target_feature(enable = "neon")]
29077#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29078#[cfg_attr(
29079    all(test, not(target_env = "msvc"), target_endian = "little"),
29080    assert_instr(uzp1)
29081)]
29082pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
29083    unsafe {
29084        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
29085        let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
29086        let ret_val: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
29087        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29088    }
29089}
29090#[doc = "Unzip vectors"]
29091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"]
29092#[inline]
29093#[cfg(target_endian = "little")]
29094#[target_feature(enable = "neon")]
29095#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29096#[cfg_attr(
29097    all(test, not(target_env = "msvc"), target_endian = "little"),
29098    assert_instr(uzp1)
29099)]
29100pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
29101    unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
29102}
29103#[doc = "Unzip vectors"]
29104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"]
29105#[inline]
29106#[cfg(target_endian = "big")]
29107#[target_feature(enable = "neon")]
29108#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29109#[cfg_attr(
29110    all(test, not(target_env = "msvc"), target_endian = "little"),
29111    assert_instr(uzp1)
29112)]
29113pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
29114    unsafe {
29115        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29116        let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29117        let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
29118        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29119    }
29120}
29121#[doc = "Unzip vectors"]
29122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"]
29123#[inline]
29124#[cfg(target_endian = "little")]
29125#[target_feature(enable = "neon,fp16")]
29126#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
29127#[cfg(not(target_arch = "arm64ec"))]
29128#[cfg_attr(
29129    all(test, not(target_env = "msvc"), target_endian = "little"),
29130    assert_instr(uzp2)
29131)]
29132pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
29133    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
29134}
29135#[doc = "Unzip vectors"]
29136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"]
29137#[inline]
29138#[cfg(target_endian = "big")]
29139#[target_feature(enable = "neon,fp16")]
29140#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
29141#[cfg(not(target_arch = "arm64ec"))]
29142#[cfg_attr(
29143    all(test, not(target_env = "msvc"), target_endian = "little"),
29144    assert_instr(uzp2)
29145)]
29146pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
29147    unsafe {
29148        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
29149        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
29150        let ret_val: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
29151        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29152    }
29153}
29154#[doc = "Unzip vectors"]
29155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"]
29156#[inline]
29157#[cfg(target_endian = "little")]
29158#[target_feature(enable = "neon,fp16")]
29159#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
29160#[cfg(not(target_arch = "arm64ec"))]
29161#[cfg_attr(
29162    all(test, not(target_env = "msvc"), target_endian = "little"),
29163    assert_instr(uzp2)
29164)]
29165pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
29166    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
29167}
29168#[doc = "Unzip vectors"]
29169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"]
29170#[inline]
29171#[cfg(target_endian = "big")]
29172#[target_feature(enable = "neon,fp16")]
29173#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
29174#[cfg(not(target_arch = "arm64ec"))]
29175#[cfg_attr(
29176    all(test, not(target_env = "msvc"), target_endian = "little"),
29177    assert_instr(uzp2)
29178)]
29179pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
29180    unsafe {
29181        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29182        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29183        let ret_val: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
29184        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29185    }
29186}
29187#[doc = "Unzip vectors"]
29188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"]
29189#[inline]
29190#[cfg(target_endian = "little")]
29191#[target_feature(enable = "neon")]
29192#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29193#[cfg_attr(
29194    all(test, not(target_env = "msvc"), target_endian = "little"),
29195    assert_instr(zip2)
29196)]
29197pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
29198    unsafe { simd_shuffle!(a, b, [1, 3]) }
29199}
29200#[doc = "Unzip vectors"]
29201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"]
29202#[inline]
29203#[cfg(target_endian = "big")]
29204#[target_feature(enable = "neon")]
29205#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29206#[cfg_attr(
29207    all(test, not(target_env = "msvc"), target_endian = "little"),
29208    assert_instr(zip2)
29209)]
29210pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
29211    unsafe {
29212        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
29213        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
29214        let ret_val: float32x2_t = simd_shuffle!(a, b, [1, 3]);
29215        simd_shuffle!(ret_val, ret_val, [1, 0])
29216    }
29217}
29218#[doc = "Unzip vectors"]
29219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"]
29220#[inline]
29221#[cfg(target_endian = "little")]
29222#[target_feature(enable = "neon")]
29223#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29224#[cfg_attr(
29225    all(test, not(target_env = "msvc"), target_endian = "little"),
29226    assert_instr(zip2)
29227)]
29228pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
29229    unsafe { simd_shuffle!(a, b, [1, 3]) }
29230}
29231#[doc = "Unzip vectors"]
29232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"]
29233#[inline]
29234#[cfg(target_endian = "big")]
29235#[target_feature(enable = "neon")]
29236#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29237#[cfg_attr(
29238    all(test, not(target_env = "msvc"), target_endian = "little"),
29239    assert_instr(zip2)
29240)]
29241pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
29242    unsafe {
29243        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
29244        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
29245        let ret_val: float64x2_t = simd_shuffle!(a, b, [1, 3]);
29246        simd_shuffle!(ret_val, ret_val, [1, 0])
29247    }
29248}
29249#[doc = "Unzip vectors"]
29250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"]
29251#[inline]
29252#[cfg(target_endian = "little")]
29253#[target_feature(enable = "neon")]
29254#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29255#[cfg_attr(
29256    all(test, not(target_env = "msvc"), target_endian = "little"),
29257    assert_instr(zip2)
29258)]
29259pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
29260    unsafe { simd_shuffle!(a, b, [1, 3]) }
29261}
29262#[doc = "Unzip vectors"]
29263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"]
29264#[inline]
29265#[cfg(target_endian = "big")]
29266#[target_feature(enable = "neon")]
29267#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29268#[cfg_attr(
29269    all(test, not(target_env = "msvc"), target_endian = "little"),
29270    assert_instr(zip2)
29271)]
29272pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
29273    unsafe {
29274        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
29275        let b: int32x2_t = simd_shuffle!(b, b, [1, 0]);
29276        let ret_val: int32x2_t = simd_shuffle!(a, b, [1, 3]);
29277        simd_shuffle!(ret_val, ret_val, [1, 0])
29278    }
29279}
29280#[doc = "Unzip vectors"]
29281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"]
29282#[inline]
29283#[cfg(target_endian = "little")]
29284#[target_feature(enable = "neon")]
29285#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29286#[cfg_attr(
29287    all(test, not(target_env = "msvc"), target_endian = "little"),
29288    assert_instr(zip2)
29289)]
29290pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
29291    unsafe { simd_shuffle!(a, b, [1, 3]) }
29292}
29293#[doc = "Unzip vectors"]
29294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"]
29295#[inline]
29296#[cfg(target_endian = "big")]
29297#[target_feature(enable = "neon")]
29298#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29299#[cfg_attr(
29300    all(test, not(target_env = "msvc"), target_endian = "little"),
29301    assert_instr(zip2)
29302)]
29303pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
29304    unsafe {
29305        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
29306        let b: int64x2_t = simd_shuffle!(b, b, [1, 0]);
29307        let ret_val: int64x2_t = simd_shuffle!(a, b, [1, 3]);
29308        simd_shuffle!(ret_val, ret_val, [1, 0])
29309    }
29310}
29311#[doc = "Unzip vectors"]
29312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"]
29313#[inline]
29314#[cfg(target_endian = "little")]
29315#[target_feature(enable = "neon")]
29316#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29317#[cfg_attr(
29318    all(test, not(target_env = "msvc"), target_endian = "little"),
29319    assert_instr(zip2)
29320)]
29321pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
29322    unsafe { simd_shuffle!(a, b, [1, 3]) }
29323}
29324#[doc = "Unzip vectors"]
29325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"]
29326#[inline]
29327#[cfg(target_endian = "big")]
29328#[target_feature(enable = "neon")]
29329#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29330#[cfg_attr(
29331    all(test, not(target_env = "msvc"), target_endian = "little"),
29332    assert_instr(zip2)
29333)]
29334pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
29335    unsafe {
29336        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
29337        let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]);
29338        let ret_val: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
29339        simd_shuffle!(ret_val, ret_val, [1, 0])
29340    }
29341}
29342#[doc = "Unzip vectors"]
29343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"]
29344#[inline]
29345#[cfg(target_endian = "little")]
29346#[target_feature(enable = "neon")]
29347#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29348#[cfg_attr(
29349    all(test, not(target_env = "msvc"), target_endian = "little"),
29350    assert_instr(zip2)
29351)]
29352pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
29353    unsafe { simd_shuffle!(a, b, [1, 3]) }
29354}
29355#[doc = "Unzip vectors"]
29356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"]
29357#[inline]
29358#[cfg(target_endian = "big")]
29359#[target_feature(enable = "neon")]
29360#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29361#[cfg_attr(
29362    all(test, not(target_env = "msvc"), target_endian = "little"),
29363    assert_instr(zip2)
29364)]
29365pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
29366    unsafe {
29367        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
29368        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
29369        let ret_val: uint64x2_t = simd_shuffle!(a, b, [1, 3]);
29370        simd_shuffle!(ret_val, ret_val, [1, 0])
29371    }
29372}
29373#[doc = "Unzip vectors"]
29374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"]
29375#[inline]
29376#[cfg(target_endian = "little")]
29377#[target_feature(enable = "neon")]
29378#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29379#[cfg_attr(
29380    all(test, not(target_env = "msvc"), target_endian = "little"),
29381    assert_instr(zip2)
29382)]
29383pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
29384    unsafe { simd_shuffle!(a, b, [1, 3]) }
29385}
29386#[doc = "Unzip vectors"]
29387#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"]
29388#[inline]
29389#[cfg(target_endian = "big")]
29390#[target_feature(enable = "neon")]
29391#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29392#[cfg_attr(
29393    all(test, not(target_env = "msvc"), target_endian = "little"),
29394    assert_instr(zip2)
29395)]
29396pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
29397    unsafe {
29398        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
29399        let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]);
29400        let ret_val: poly64x2_t = simd_shuffle!(a, b, [1, 3]);
29401        simd_shuffle!(ret_val, ret_val, [1, 0])
29402    }
29403}
29404#[doc = "Unzip vectors"]
29405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"]
29406#[inline]
29407#[cfg(target_endian = "little")]
29408#[target_feature(enable = "neon")]
29409#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29410#[cfg_attr(
29411    all(test, not(target_env = "msvc"), target_endian = "little"),
29412    assert_instr(uzp2)
29413)]
29414pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
29415    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
29416}
29417#[doc = "Unzip vectors"]
29418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"]
29419#[inline]
29420#[cfg(target_endian = "big")]
29421#[target_feature(enable = "neon")]
29422#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29423#[cfg_attr(
29424    all(test, not(target_env = "msvc"), target_endian = "little"),
29425    assert_instr(uzp2)
29426)]
29427pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
29428    unsafe {
29429        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
29430        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
29431        let ret_val: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
29432        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29433    }
29434}
29435#[doc = "Unzip vectors"]
29436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"]
29437#[inline]
29438#[cfg(target_endian = "little")]
29439#[target_feature(enable = "neon")]
29440#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29441#[cfg_attr(
29442    all(test, not(target_env = "msvc"), target_endian = "little"),
29443    assert_instr(uzp2)
29444)]
29445pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
29446    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
29447}
29448#[doc = "Unzip vectors"]
29449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"]
29450#[inline]
29451#[cfg(target_endian = "big")]
29452#[target_feature(enable = "neon")]
29453#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29454#[cfg_attr(
29455    all(test, not(target_env = "msvc"), target_endian = "little"),
29456    assert_instr(uzp2)
29457)]
29458pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
29459    unsafe {
29460        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29461        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29462        let ret_val: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
29463        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29464    }
29465}
29466#[doc = "Unzip vectors"]
29467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"]
29468#[inline]
29469#[cfg(target_endian = "little")]
29470#[target_feature(enable = "neon")]
29471#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29472#[cfg_attr(
29473    all(test, not(target_env = "msvc"), target_endian = "little"),
29474    assert_instr(uzp2)
29475)]
29476pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
29477    unsafe {
29478        simd_shuffle!(
29479            a,
29480            b,
29481            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
29482        )
29483    }
29484}
29485#[doc = "Unzip vectors"]
29486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"]
29487#[inline]
29488#[cfg(target_endian = "big")]
29489#[target_feature(enable = "neon")]
29490#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29491#[cfg_attr(
29492    all(test, not(target_env = "msvc"), target_endian = "little"),
29493    assert_instr(uzp2)
29494)]
29495pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
29496    unsafe {
29497        let a: int8x16_t =
29498            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
29499        let b: int8x16_t =
29500            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
29501        let ret_val: int8x16_t = simd_shuffle!(
29502            a,
29503            b,
29504            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
29505        );
29506        simd_shuffle!(
29507            ret_val,
29508            ret_val,
29509            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
29510        )
29511    }
29512}
29513#[doc = "Unzip vectors"]
29514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"]
29515#[inline]
29516#[cfg(target_endian = "little")]
29517#[target_feature(enable = "neon")]
29518#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29519#[cfg_attr(
29520    all(test, not(target_env = "msvc"), target_endian = "little"),
29521    assert_instr(uzp2)
29522)]
29523pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
29524    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
29525}
29526#[doc = "Unzip vectors"]
29527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"]
29528#[inline]
29529#[cfg(target_endian = "big")]
29530#[target_feature(enable = "neon")]
29531#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29532#[cfg_attr(
29533    all(test, not(target_env = "msvc"), target_endian = "little"),
29534    assert_instr(uzp2)
29535)]
29536pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
29537    unsafe {
29538        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
29539        let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
29540        let ret_val: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
29541        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29542    }
29543}
29544#[doc = "Unzip vectors"]
29545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"]
29546#[inline]
29547#[cfg(target_endian = "little")]
29548#[target_feature(enable = "neon")]
29549#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29550#[cfg_attr(
29551    all(test, not(target_env = "msvc"), target_endian = "little"),
29552    assert_instr(uzp2)
29553)]
29554pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
29555    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
29556}
29557#[doc = "Unzip vectors"]
29558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"]
29559#[inline]
29560#[cfg(target_endian = "big")]
29561#[target_feature(enable = "neon")]
29562#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29563#[cfg_attr(
29564    all(test, not(target_env = "msvc"), target_endian = "little"),
29565    assert_instr(uzp2)
29566)]
29567pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
29568    unsafe {
29569        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29570        let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29571        let ret_val: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
29572        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29573    }
29574}
29575#[doc = "Unzip vectors"]
29576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"]
29577#[inline]
29578#[cfg(target_endian = "little")]
29579#[target_feature(enable = "neon")]
29580#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29581#[cfg_attr(
29582    all(test, not(target_env = "msvc"), target_endian = "little"),
29583    assert_instr(uzp2)
29584)]
29585pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
29586    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
29587}
29588#[doc = "Unzip vectors"]
29589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"]
29590#[inline]
29591#[cfg(target_endian = "big")]
29592#[target_feature(enable = "neon")]
29593#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29594#[cfg_attr(
29595    all(test, not(target_env = "msvc"), target_endian = "little"),
29596    assert_instr(uzp2)
29597)]
29598pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
29599    unsafe {
29600        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
29601        let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
29602        let ret_val: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
29603        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29604    }
29605}
29606#[doc = "Unzip vectors"]
29607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"]
29608#[inline]
29609#[cfg(target_endian = "little")]
29610#[target_feature(enable = "neon")]
29611#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29612#[cfg_attr(
29613    all(test, not(target_env = "msvc"), target_endian = "little"),
29614    assert_instr(uzp2)
29615)]
29616pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
29617    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
29618}
29619#[doc = "Unzip vectors"]
29620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"]
29621#[inline]
29622#[cfg(target_endian = "big")]
29623#[target_feature(enable = "neon")]
29624#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29625#[cfg_attr(
29626    all(test, not(target_env = "msvc"), target_endian = "little"),
29627    assert_instr(uzp2)
29628)]
29629pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
29630    unsafe {
29631        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29632        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29633        let ret_val: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
29634        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29635    }
29636}
29637#[doc = "Unzip vectors"]
29638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"]
29639#[inline]
29640#[cfg(target_endian = "little")]
29641#[target_feature(enable = "neon")]
29642#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29643#[cfg_attr(
29644    all(test, not(target_env = "msvc"), target_endian = "little"),
29645    assert_instr(uzp2)
29646)]
29647pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
29648    unsafe {
29649        simd_shuffle!(
29650            a,
29651            b,
29652            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
29653        )
29654    }
29655}
29656#[doc = "Unzip vectors"]
29657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"]
29658#[inline]
29659#[cfg(target_endian = "big")]
29660#[target_feature(enable = "neon")]
29661#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29662#[cfg_attr(
29663    all(test, not(target_env = "msvc"), target_endian = "little"),
29664    assert_instr(uzp2)
29665)]
29666pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
29667    unsafe {
29668        let a: uint8x16_t =
29669            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
29670        let b: uint8x16_t =
29671            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
29672        let ret_val: uint8x16_t = simd_shuffle!(
29673            a,
29674            b,
29675            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
29676        );
29677        simd_shuffle!(
29678            ret_val,
29679            ret_val,
29680            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
29681        )
29682    }
29683}
29684#[doc = "Unzip vectors"]
29685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"]
29686#[inline]
29687#[cfg(target_endian = "little")]
29688#[target_feature(enable = "neon")]
29689#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29690#[cfg_attr(
29691    all(test, not(target_env = "msvc"), target_endian = "little"),
29692    assert_instr(uzp2)
29693)]
29694pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
29695    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
29696}
29697#[doc = "Unzip vectors"]
29698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"]
29699#[inline]
29700#[cfg(target_endian = "big")]
29701#[target_feature(enable = "neon")]
29702#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29703#[cfg_attr(
29704    all(test, not(target_env = "msvc"), target_endian = "little"),
29705    assert_instr(uzp2)
29706)]
29707pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
29708    unsafe {
29709        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
29710        let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
29711        let ret_val: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
29712        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29713    }
29714}
29715#[doc = "Unzip vectors"]
29716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"]
29717#[inline]
29718#[cfg(target_endian = "little")]
29719#[target_feature(enable = "neon")]
29720#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29721#[cfg_attr(
29722    all(test, not(target_env = "msvc"), target_endian = "little"),
29723    assert_instr(uzp2)
29724)]
29725pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
29726    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
29727}
29728#[doc = "Unzip vectors"]
29729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"]
29730#[inline]
29731#[cfg(target_endian = "big")]
29732#[target_feature(enable = "neon")]
29733#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29734#[cfg_attr(
29735    all(test, not(target_env = "msvc"), target_endian = "little"),
29736    assert_instr(uzp2)
29737)]
29738pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
29739    unsafe {
29740        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29741        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29742        let ret_val: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
29743        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29744    }
29745}
29746#[doc = "Unzip vectors"]
29747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"]
29748#[inline]
29749#[cfg(target_endian = "little")]
29750#[target_feature(enable = "neon")]
29751#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29752#[cfg_attr(
29753    all(test, not(target_env = "msvc"), target_endian = "little"),
29754    assert_instr(uzp2)
29755)]
29756pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
29757    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
29758}
29759#[doc = "Unzip vectors"]
29760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"]
29761#[inline]
29762#[cfg(target_endian = "big")]
29763#[target_feature(enable = "neon")]
29764#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29765#[cfg_attr(
29766    all(test, not(target_env = "msvc"), target_endian = "little"),
29767    assert_instr(uzp2)
29768)]
29769pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
29770    unsafe {
29771        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
29772        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
29773        let ret_val: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
29774        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29775    }
29776}
29777#[doc = "Unzip vectors"]
29778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"]
29779#[inline]
29780#[cfg(target_endian = "little")]
29781#[target_feature(enable = "neon")]
29782#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29783#[cfg_attr(
29784    all(test, not(target_env = "msvc"), target_endian = "little"),
29785    assert_instr(uzp2)
29786)]
29787pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
29788    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
29789}
29790#[doc = "Unzip vectors"]
29791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"]
29792#[inline]
29793#[cfg(target_endian = "big")]
29794#[target_feature(enable = "neon")]
29795#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29796#[cfg_attr(
29797    all(test, not(target_env = "msvc"), target_endian = "little"),
29798    assert_instr(uzp2)
29799)]
29800pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
29801    unsafe {
29802        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29803        let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29804        let ret_val: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
29805        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29806    }
29807}
29808#[doc = "Unzip vectors"]
29809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"]
29810#[inline]
29811#[cfg(target_endian = "little")]
29812#[target_feature(enable = "neon")]
29813#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29814#[cfg_attr(
29815    all(test, not(target_env = "msvc"), target_endian = "little"),
29816    assert_instr(uzp2)
29817)]
29818pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
29819    unsafe {
29820        simd_shuffle!(
29821            a,
29822            b,
29823            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
29824        )
29825    }
29826}
29827#[doc = "Unzip vectors"]
29828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"]
29829#[inline]
29830#[cfg(target_endian = "big")]
29831#[target_feature(enable = "neon")]
29832#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29833#[cfg_attr(
29834    all(test, not(target_env = "msvc"), target_endian = "little"),
29835    assert_instr(uzp2)
29836)]
29837pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
29838    unsafe {
29839        let a: poly8x16_t =
29840            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
29841        let b: poly8x16_t =
29842            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
29843        let ret_val: poly8x16_t = simd_shuffle!(
29844            a,
29845            b,
29846            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
29847        );
29848        simd_shuffle!(
29849            ret_val,
29850            ret_val,
29851            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
29852        )
29853    }
29854}
29855#[doc = "Unzip vectors"]
29856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"]
29857#[inline]
29858#[cfg(target_endian = "little")]
29859#[target_feature(enable = "neon")]
29860#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29861#[cfg_attr(
29862    all(test, not(target_env = "msvc"), target_endian = "little"),
29863    assert_instr(uzp2)
29864)]
29865pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
29866    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
29867}
29868#[doc = "Unzip vectors"]
29869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"]
29870#[inline]
29871#[cfg(target_endian = "big")]
29872#[target_feature(enable = "neon")]
29873#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29874#[cfg_attr(
29875    all(test, not(target_env = "msvc"), target_endian = "little"),
29876    assert_instr(uzp2)
29877)]
29878pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
29879    unsafe {
29880        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
29881        let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
29882        let ret_val: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
29883        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29884    }
29885}
29886#[doc = "Unzip vectors"]
29887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"]
29888#[inline]
29889#[cfg(target_endian = "little")]
29890#[target_feature(enable = "neon")]
29891#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29892#[cfg_attr(
29893    all(test, not(target_env = "msvc"), target_endian = "little"),
29894    assert_instr(uzp2)
29895)]
29896pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
29897    unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
29898}
29899#[doc = "Unzip vectors"]
29900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"]
29901#[inline]
29902#[cfg(target_endian = "big")]
29903#[target_feature(enable = "neon")]
29904#[stable(feature = "neon_intrinsics", since = "1.59.0")]
29905#[cfg_attr(
29906    all(test, not(target_env = "msvc"), target_endian = "little"),
29907    assert_instr(uzp2)
29908)]
29909pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
29910    unsafe {
29911        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29912        let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29913        let ret_val: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
29914        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29915    }
29916}
29917#[doc = "Exclusive OR and rotate"]
29918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vxarq_u64)"]
29919#[inline]
29920#[target_feature(enable = "neon,sha3")]
29921#[cfg_attr(test, assert_instr(xar, IMM6 = 0))]
29922#[rustc_legacy_const_generics(2)]
29923#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
29924pub fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
29925    static_assert_uimm_bits!(IMM6, 6);
29926    unsafe extern "unadjusted" {
29927        #[cfg_attr(
29928            any(target_arch = "aarch64", target_arch = "arm64ec"),
29929            link_name = "llvm.aarch64.crypto.xar"
29930        )]
29931        fn _vxarq_u64(a: uint64x2_t, b: uint64x2_t, n: i64) -> uint64x2_t;
29932    }
29933    unsafe { _vxarq_u64(a, b, IMM6 as i64) }
29934}
29935#[doc = "Zip vectors"]
29936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"]
29937#[inline]
29938#[cfg(target_endian = "little")]
29939#[target_feature(enable = "neon,fp16")]
29940#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
29941#[cfg(not(target_arch = "arm64ec"))]
29942#[cfg_attr(
29943    all(test, not(target_env = "msvc"), target_endian = "little"),
29944    assert_instr(zip1)
29945)]
29946pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
29947    unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
29948}
29949#[doc = "Zip vectors"]
29950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"]
29951#[inline]
29952#[cfg(target_endian = "big")]
29953#[target_feature(enable = "neon,fp16")]
29954#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
29955#[cfg(not(target_arch = "arm64ec"))]
29956#[cfg_attr(
29957    all(test, not(target_env = "msvc"), target_endian = "little"),
29958    assert_instr(zip1)
29959)]
29960pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
29961    unsafe {
29962        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
29963        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
29964        let ret_val: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
29965        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
29966    }
29967}
29968#[doc = "Zip vectors"]
29969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"]
29970#[inline]
29971#[cfg(target_endian = "little")]
29972#[target_feature(enable = "neon,fp16")]
29973#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
29974#[cfg(not(target_arch = "arm64ec"))]
29975#[cfg_attr(
29976    all(test, not(target_env = "msvc"), target_endian = "little"),
29977    assert_instr(zip1)
29978)]
29979pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
29980    unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
29981}
29982#[doc = "Zip vectors"]
29983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"]
29984#[inline]
29985#[cfg(target_endian = "big")]
29986#[target_feature(enable = "neon,fp16")]
29987#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
29988#[cfg(not(target_arch = "arm64ec"))]
29989#[cfg_attr(
29990    all(test, not(target_env = "msvc"), target_endian = "little"),
29991    assert_instr(zip1)
29992)]
29993pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
29994    unsafe {
29995        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
29996        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
29997        let ret_val: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
29998        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
29999    }
30000}
30001#[doc = "Zip vectors"]
30002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"]
30003#[inline]
30004#[cfg(target_endian = "little")]
30005#[target_feature(enable = "neon")]
30006#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30007#[cfg_attr(
30008    all(test, not(target_env = "msvc"), target_endian = "little"),
30009    assert_instr(zip1)
30010)]
30011pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
30012    unsafe { simd_shuffle!(a, b, [0, 2]) }
30013}
30014#[doc = "Zip vectors"]
30015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"]
30016#[inline]
30017#[cfg(target_endian = "big")]
30018#[target_feature(enable = "neon")]
30019#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30020#[cfg_attr(
30021    all(test, not(target_env = "msvc"), target_endian = "little"),
30022    assert_instr(zip1)
30023)]
30024pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
30025    unsafe {
30026        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
30027        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
30028        let ret_val: float32x2_t = simd_shuffle!(a, b, [0, 2]);
30029        simd_shuffle!(ret_val, ret_val, [1, 0])
30030    }
30031}
30032#[doc = "Zip vectors"]
30033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"]
30034#[inline]
30035#[cfg(target_endian = "little")]
30036#[target_feature(enable = "neon")]
30037#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30038#[cfg_attr(
30039    all(test, not(target_env = "msvc"), target_endian = "little"),
30040    assert_instr(zip1)
30041)]
30042pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
30043    unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
30044}
30045#[doc = "Zip vectors"]
30046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"]
30047#[inline]
30048#[cfg(target_endian = "big")]
30049#[target_feature(enable = "neon")]
30050#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30051#[cfg_attr(
30052    all(test, not(target_env = "msvc"), target_endian = "little"),
30053    assert_instr(zip1)
30054)]
30055pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
30056    unsafe {
30057        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
30058        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
30059        let ret_val: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
30060        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
30061    }
30062}
30063#[doc = "Zip vectors"]
30064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"]
30065#[inline]
30066#[cfg(target_endian = "little")]
30067#[target_feature(enable = "neon")]
30068#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30069#[cfg_attr(
30070    all(test, not(target_env = "msvc"), target_endian = "little"),
30071    assert_instr(zip1)
30072)]
30073pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
30074    unsafe { simd_shuffle!(a, b, [0, 2]) }
30075}
30076#[doc = "Zip vectors"]
30077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"]
30078#[inline]
30079#[cfg(target_endian = "big")]
30080#[target_feature(enable = "neon")]
30081#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30082#[cfg_attr(
30083    all(test, not(target_env = "msvc"), target_endian = "little"),
30084    assert_instr(zip1)
30085)]
30086pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
30087    unsafe {
30088        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
30089        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
30090        let ret_val: float64x2_t = simd_shuffle!(a, b, [0, 2]);
30091        simd_shuffle!(ret_val, ret_val, [1, 0])
30092    }
30093}
30094#[doc = "Zip vectors"]
30095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"]
30096#[inline]
30097#[cfg(target_endian = "little")]
30098#[target_feature(enable = "neon")]
30099#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30100#[cfg_attr(
30101    all(test, not(target_env = "msvc"), target_endian = "little"),
30102    assert_instr(zip1)
30103)]
30104pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
30105    unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
30106}
30107#[doc = "Zip vectors"]
30108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"]
30109#[inline]
30110#[cfg(target_endian = "big")]
30111#[target_feature(enable = "neon")]
30112#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30113#[cfg_attr(
30114    all(test, not(target_env = "msvc"), target_endian = "little"),
30115    assert_instr(zip1)
30116)]
30117pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
30118    unsafe {
30119        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
30120        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
30121        let ret_val: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
30122        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
30123    }
30124}
30125#[doc = "Zip vectors"]
30126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"]
30127#[inline]
30128#[cfg(target_endian = "little")]
30129#[target_feature(enable = "neon")]
30130#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30131#[cfg_attr(
30132    all(test, not(target_env = "msvc"), target_endian = "little"),
30133    assert_instr(zip1)
30134)]
30135pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
30136    unsafe {
30137        simd_shuffle!(
30138            a,
30139            b,
30140            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
30141        )
30142    }
30143}
30144#[doc = "Zip vectors"]
30145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"]
30146#[inline]
30147#[cfg(target_endian = "big")]
30148#[target_feature(enable = "neon")]
30149#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30150#[cfg_attr(
30151    all(test, not(target_env = "msvc"), target_endian = "little"),
30152    assert_instr(zip1)
30153)]
30154pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
30155    unsafe {
30156        let a: int8x16_t =
30157            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
30158        let b: int8x16_t =
30159            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
30160        let ret_val: int8x16_t = simd_shuffle!(
30161            a,
30162            b,
30163            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
30164        );
30165        simd_shuffle!(
30166            ret_val,
30167            ret_val,
30168            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
30169        )
30170    }
30171}
30172#[doc = "Zip vectors"]
30173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"]
30174#[inline]
30175#[cfg(target_endian = "little")]
30176#[target_feature(enable = "neon")]
30177#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30178#[cfg_attr(
30179    all(test, not(target_env = "msvc"), target_endian = "little"),
30180    assert_instr(zip1)
30181)]
30182pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
30183    unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
30184}
30185#[doc = "Zip vectors"]
30186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"]
30187#[inline]
30188#[cfg(target_endian = "big")]
30189#[target_feature(enable = "neon")]
30190#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30191#[cfg_attr(
30192    all(test, not(target_env = "msvc"), target_endian = "little"),
30193    assert_instr(zip1)
30194)]
30195pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
30196    unsafe {
30197        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
30198        let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
30199        let ret_val: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
30200        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
30201    }
30202}
30203#[doc = "Zip vectors"]
30204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"]
30205#[inline]
30206#[cfg(target_endian = "little")]
30207#[target_feature(enable = "neon")]
30208#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30209#[cfg_attr(
30210    all(test, not(target_env = "msvc"), target_endian = "little"),
30211    assert_instr(zip1)
30212)]
30213pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
30214    unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
30215}
30216#[doc = "Zip vectors"]
30217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"]
30218#[inline]
30219#[cfg(target_endian = "big")]
30220#[target_feature(enable = "neon")]
30221#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30222#[cfg_attr(
30223    all(test, not(target_env = "msvc"), target_endian = "little"),
30224    assert_instr(zip1)
30225)]
30226pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
30227    unsafe {
30228        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
30229        let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
30230        let ret_val: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
30231        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
30232    }
30233}
30234#[doc = "Zip vectors"]
30235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"]
30236#[inline]
30237#[cfg(target_endian = "little")]
30238#[target_feature(enable = "neon")]
30239#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30240#[cfg_attr(
30241    all(test, not(target_env = "msvc"), target_endian = "little"),
30242    assert_instr(zip1)
30243)]
30244pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
30245    unsafe { simd_shuffle!(a, b, [0, 2]) }
30246}
30247#[doc = "Zip vectors"]
30248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"]
30249#[inline]
30250#[cfg(target_endian = "big")]
30251#[target_feature(enable = "neon")]
30252#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30253#[cfg_attr(
30254    all(test, not(target_env = "msvc"), target_endian = "little"),
30255    assert_instr(zip1)
30256)]
30257pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
30258    unsafe {
30259        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
30260        let b: int32x2_t = simd_shuffle!(b, b, [1, 0]);
30261        let ret_val: int32x2_t = simd_shuffle!(a, b, [0, 2]);
30262        simd_shuffle!(ret_val, ret_val, [1, 0])
30263    }
30264}
30265#[doc = "Zip vectors"]
30266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"]
30267#[inline]
30268#[cfg(target_endian = "little")]
30269#[target_feature(enable = "neon")]
30270#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30271#[cfg_attr(
30272    all(test, not(target_env = "msvc"), target_endian = "little"),
30273    assert_instr(zip1)
30274)]
30275pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
30276    unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
30277}
30278#[doc = "Zip vectors"]
30279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"]
30280#[inline]
30281#[cfg(target_endian = "big")]
30282#[target_feature(enable = "neon")]
30283#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30284#[cfg_attr(
30285    all(test, not(target_env = "msvc"), target_endian = "little"),
30286    assert_instr(zip1)
30287)]
30288pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
30289    unsafe {
30290        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
30291        let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
30292        let ret_val: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
30293        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
30294    }
30295}
30296#[doc = "Zip vectors"]
30297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"]
30298#[inline]
30299#[cfg(target_endian = "little")]
30300#[target_feature(enable = "neon")]
30301#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30302#[cfg_attr(
30303    all(test, not(target_env = "msvc"), target_endian = "little"),
30304    assert_instr(zip1)
30305)]
30306pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
30307    unsafe { simd_shuffle!(a, b, [0, 2]) }
30308}
30309#[doc = "Zip vectors"]
30310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"]
30311#[inline]
30312#[cfg(target_endian = "big")]
30313#[target_feature(enable = "neon")]
30314#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30315#[cfg_attr(
30316    all(test, not(target_env = "msvc"), target_endian = "little"),
30317    assert_instr(zip1)
30318)]
30319pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
30320    unsafe {
30321        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
30322        let b: int64x2_t = simd_shuffle!(b, b, [1, 0]);
30323        let ret_val: int64x2_t = simd_shuffle!(a, b, [0, 2]);
30324        simd_shuffle!(ret_val, ret_val, [1, 0])
30325    }
30326}
30327#[doc = "Zip vectors"]
30328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"]
30329#[inline]
30330#[cfg(target_endian = "little")]
30331#[target_feature(enable = "neon")]
30332#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30333#[cfg_attr(
30334    all(test, not(target_env = "msvc"), target_endian = "little"),
30335    assert_instr(zip1)
30336)]
30337pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
30338    unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
30339}
30340#[doc = "Zip vectors"]
30341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"]
30342#[inline]
30343#[cfg(target_endian = "big")]
30344#[target_feature(enable = "neon")]
30345#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30346#[cfg_attr(
30347    all(test, not(target_env = "msvc"), target_endian = "little"),
30348    assert_instr(zip1)
30349)]
30350pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
30351    unsafe {
30352        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
30353        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
30354        let ret_val: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
30355        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
30356    }
30357}
30358#[doc = "Zip vectors"]
30359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"]
30360#[inline]
30361#[cfg(target_endian = "little")]
30362#[target_feature(enable = "neon")]
30363#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30364#[cfg_attr(
30365    all(test, not(target_env = "msvc"), target_endian = "little"),
30366    assert_instr(zip1)
30367)]
30368pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
30369    unsafe {
30370        simd_shuffle!(
30371            a,
30372            b,
30373            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
30374        )
30375    }
30376}
30377#[doc = "Zip vectors"]
30378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"]
30379#[inline]
30380#[cfg(target_endian = "big")]
30381#[target_feature(enable = "neon")]
30382#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30383#[cfg_attr(
30384    all(test, not(target_env = "msvc"), target_endian = "little"),
30385    assert_instr(zip1)
30386)]
30387pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
30388    unsafe {
30389        let a: uint8x16_t =
30390            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
30391        let b: uint8x16_t =
30392            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
30393        let ret_val: uint8x16_t = simd_shuffle!(
30394            a,
30395            b,
30396            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
30397        );
30398        simd_shuffle!(
30399            ret_val,
30400            ret_val,
30401            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
30402        )
30403    }
30404}
30405#[doc = "Zip vectors"]
30406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"]
30407#[inline]
30408#[cfg(target_endian = "little")]
30409#[target_feature(enable = "neon")]
30410#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30411#[cfg_attr(
30412    all(test, not(target_env = "msvc"), target_endian = "little"),
30413    assert_instr(zip1)
30414)]
30415pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
30416    unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
30417}
30418#[doc = "Zip vectors"]
30419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"]
30420#[inline]
30421#[cfg(target_endian = "big")]
30422#[target_feature(enable = "neon")]
30423#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30424#[cfg_attr(
30425    all(test, not(target_env = "msvc"), target_endian = "little"),
30426    assert_instr(zip1)
30427)]
30428pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
30429    unsafe {
30430        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
30431        let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
30432        let ret_val: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
30433        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
30434    }
30435}
30436#[doc = "Zip vectors"]
30437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"]
30438#[inline]
30439#[cfg(target_endian = "little")]
30440#[target_feature(enable = "neon")]
30441#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30442#[cfg_attr(
30443    all(test, not(target_env = "msvc"), target_endian = "little"),
30444    assert_instr(zip1)
30445)]
30446pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
30447    unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
30448}
30449#[doc = "Zip vectors"]
30450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"]
30451#[inline]
30452#[cfg(target_endian = "big")]
30453#[target_feature(enable = "neon")]
30454#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30455#[cfg_attr(
30456    all(test, not(target_env = "msvc"), target_endian = "little"),
30457    assert_instr(zip1)
30458)]
30459pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
30460    unsafe {
30461        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
30462        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
30463        let ret_val: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
30464        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
30465    }
30466}
30467#[doc = "Zip vectors"]
30468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"]
30469#[inline]
30470#[cfg(target_endian = "little")]
30471#[target_feature(enable = "neon")]
30472#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30473#[cfg_attr(
30474    all(test, not(target_env = "msvc"), target_endian = "little"),
30475    assert_instr(zip1)
30476)]
30477pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
30478    unsafe { simd_shuffle!(a, b, [0, 2]) }
30479}
30480#[doc = "Zip vectors"]
30481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"]
30482#[inline]
30483#[cfg(target_endian = "big")]
30484#[target_feature(enable = "neon")]
30485#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30486#[cfg_attr(
30487    all(test, not(target_env = "msvc"), target_endian = "little"),
30488    assert_instr(zip1)
30489)]
30490pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
30491    unsafe {
30492        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
30493        let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]);
30494        let ret_val: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
30495        simd_shuffle!(ret_val, ret_val, [1, 0])
30496    }
30497}
30498#[doc = "Zip vectors"]
30499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"]
30500#[inline]
30501#[cfg(target_endian = "little")]
30502#[target_feature(enable = "neon")]
30503#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30504#[cfg_attr(
30505    all(test, not(target_env = "msvc"), target_endian = "little"),
30506    assert_instr(zip1)
30507)]
30508pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
30509    unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
30510}
30511#[doc = "Zip vectors"]
30512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"]
30513#[inline]
30514#[cfg(target_endian = "big")]
30515#[target_feature(enable = "neon")]
30516#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30517#[cfg_attr(
30518    all(test, not(target_env = "msvc"), target_endian = "little"),
30519    assert_instr(zip1)
30520)]
30521pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
30522    unsafe {
30523        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
30524        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
30525        let ret_val: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
30526        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
30527    }
30528}
30529#[doc = "Zip vectors"]
30530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"]
30531#[inline]
30532#[cfg(target_endian = "little")]
30533#[target_feature(enable = "neon")]
30534#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30535#[cfg_attr(
30536    all(test, not(target_env = "msvc"), target_endian = "little"),
30537    assert_instr(zip1)
30538)]
30539pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
30540    unsafe { simd_shuffle!(a, b, [0, 2]) }
30541}
30542#[doc = "Zip vectors"]
30543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"]
30544#[inline]
30545#[cfg(target_endian = "big")]
30546#[target_feature(enable = "neon")]
30547#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30548#[cfg_attr(
30549    all(test, not(target_env = "msvc"), target_endian = "little"),
30550    assert_instr(zip1)
30551)]
30552pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
30553    unsafe {
30554        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
30555        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
30556        let ret_val: uint64x2_t = simd_shuffle!(a, b, [0, 2]);
30557        simd_shuffle!(ret_val, ret_val, [1, 0])
30558    }
30559}
30560#[doc = "Zip vectors"]
30561#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"]
30562#[inline]
30563#[cfg(target_endian = "little")]
30564#[target_feature(enable = "neon")]
30565#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30566#[cfg_attr(
30567    all(test, not(target_env = "msvc"), target_endian = "little"),
30568    assert_instr(zip1)
30569)]
30570pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
30571    unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
30572}
30573#[doc = "Zip vectors"]
30574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"]
30575#[inline]
30576#[cfg(target_endian = "big")]
30577#[target_feature(enable = "neon")]
30578#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30579#[cfg_attr(
30580    all(test, not(target_env = "msvc"), target_endian = "little"),
30581    assert_instr(zip1)
30582)]
30583pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
30584    unsafe {
30585        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
30586        let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
30587        let ret_val: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
30588        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
30589    }
30590}
30591#[doc = "Zip vectors"]
30592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"]
30593#[inline]
30594#[cfg(target_endian = "little")]
30595#[target_feature(enable = "neon")]
30596#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30597#[cfg_attr(
30598    all(test, not(target_env = "msvc"), target_endian = "little"),
30599    assert_instr(zip1)
30600)]
30601pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
30602    unsafe {
30603        simd_shuffle!(
30604            a,
30605            b,
30606            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
30607        )
30608    }
30609}
30610#[doc = "Zip vectors"]
30611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"]
30612#[inline]
30613#[cfg(target_endian = "big")]
30614#[target_feature(enable = "neon")]
30615#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30616#[cfg_attr(
30617    all(test, not(target_env = "msvc"), target_endian = "little"),
30618    assert_instr(zip1)
30619)]
30620pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
30621    unsafe {
30622        let a: poly8x16_t =
30623            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
30624        let b: poly8x16_t =
30625            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
30626        let ret_val: poly8x16_t = simd_shuffle!(
30627            a,
30628            b,
30629            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
30630        );
30631        simd_shuffle!(
30632            ret_val,
30633            ret_val,
30634            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
30635        )
30636    }
30637}
30638#[doc = "Zip vectors"]
30639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"]
30640#[inline]
30641#[cfg(target_endian = "little")]
30642#[target_feature(enable = "neon")]
30643#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30644#[cfg_attr(
30645    all(test, not(target_env = "msvc"), target_endian = "little"),
30646    assert_instr(zip1)
30647)]
30648pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
30649    unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
30650}
30651#[doc = "Zip vectors"]
30652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"]
30653#[inline]
30654#[cfg(target_endian = "big")]
30655#[target_feature(enable = "neon")]
30656#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30657#[cfg_attr(
30658    all(test, not(target_env = "msvc"), target_endian = "little"),
30659    assert_instr(zip1)
30660)]
30661pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
30662    unsafe {
30663        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
30664        let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
30665        let ret_val: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
30666        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
30667    }
30668}
30669#[doc = "Zip vectors"]
30670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"]
30671#[inline]
30672#[cfg(target_endian = "little")]
30673#[target_feature(enable = "neon")]
30674#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30675#[cfg_attr(
30676    all(test, not(target_env = "msvc"), target_endian = "little"),
30677    assert_instr(zip1)
30678)]
30679pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
30680    unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
30681}
30682#[doc = "Zip vectors"]
30683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"]
30684#[inline]
30685#[cfg(target_endian = "big")]
30686#[target_feature(enable = "neon")]
30687#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30688#[cfg_attr(
30689    all(test, not(target_env = "msvc"), target_endian = "little"),
30690    assert_instr(zip1)
30691)]
30692pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
30693    unsafe {
30694        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
30695        let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
30696        let ret_val: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
30697        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
30698    }
30699}
30700#[doc = "Zip vectors"]
30701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"]
30702#[inline]
30703#[cfg(target_endian = "little")]
30704#[target_feature(enable = "neon")]
30705#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30706#[cfg_attr(
30707    all(test, not(target_env = "msvc"), target_endian = "little"),
30708    assert_instr(zip1)
30709)]
30710pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
30711    unsafe { simd_shuffle!(a, b, [0, 2]) }
30712}
30713#[doc = "Zip vectors"]
30714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"]
30715#[inline]
30716#[cfg(target_endian = "big")]
30717#[target_feature(enable = "neon")]
30718#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30719#[cfg_attr(
30720    all(test, not(target_env = "msvc"), target_endian = "little"),
30721    assert_instr(zip1)
30722)]
30723pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
30724    unsafe {
30725        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
30726        let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]);
30727        let ret_val: poly64x2_t = simd_shuffle!(a, b, [0, 2]);
30728        simd_shuffle!(ret_val, ret_val, [1, 0])
30729    }
30730}
30731#[doc = "Zip vectors"]
30732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"]
30733#[inline]
30734#[cfg(target_endian = "little")]
30735#[target_feature(enable = "neon,fp16")]
30736#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
30737#[cfg(not(target_arch = "arm64ec"))]
30738#[cfg_attr(
30739    all(test, not(target_env = "msvc"), target_endian = "little"),
30740    assert_instr(zip2)
30741)]
30742pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
30743    unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
30744}
30745#[doc = "Zip vectors"]
30746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"]
30747#[inline]
30748#[cfg(target_endian = "big")]
30749#[target_feature(enable = "neon,fp16")]
30750#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
30751#[cfg(not(target_arch = "arm64ec"))]
30752#[cfg_attr(
30753    all(test, not(target_env = "msvc"), target_endian = "little"),
30754    assert_instr(zip2)
30755)]
30756pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
30757    unsafe {
30758        let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
30759        let b: float16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
30760        let ret_val: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
30761        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
30762    }
30763}
30764#[doc = "Zip vectors"]
30765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"]
30766#[inline]
30767#[cfg(target_endian = "little")]
30768#[target_feature(enable = "neon,fp16")]
30769#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
30770#[cfg(not(target_arch = "arm64ec"))]
30771#[cfg_attr(
30772    all(test, not(target_env = "msvc"), target_endian = "little"),
30773    assert_instr(zip2)
30774)]
30775pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
30776    unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
30777}
30778#[doc = "Zip vectors"]
30779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"]
30780#[inline]
30781#[cfg(target_endian = "big")]
30782#[target_feature(enable = "neon,fp16")]
30783#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
30784#[cfg(not(target_arch = "arm64ec"))]
30785#[cfg_attr(
30786    all(test, not(target_env = "msvc"), target_endian = "little"),
30787    assert_instr(zip2)
30788)]
30789pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
30790    unsafe {
30791        let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
30792        let b: float16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
30793        let ret_val: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
30794        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
30795    }
30796}
30797#[doc = "Zip vectors"]
30798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"]
30799#[inline]
30800#[cfg(target_endian = "little")]
30801#[target_feature(enable = "neon")]
30802#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30803#[cfg_attr(
30804    all(test, not(target_env = "msvc"), target_endian = "little"),
30805    assert_instr(zip2)
30806)]
30807pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
30808    unsafe { simd_shuffle!(a, b, [1, 3]) }
30809}
30810#[doc = "Zip vectors"]
30811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"]
30812#[inline]
30813#[cfg(target_endian = "big")]
30814#[target_feature(enable = "neon")]
30815#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30816#[cfg_attr(
30817    all(test, not(target_env = "msvc"), target_endian = "little"),
30818    assert_instr(zip2)
30819)]
30820pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
30821    unsafe {
30822        let a: float32x2_t = simd_shuffle!(a, a, [1, 0]);
30823        let b: float32x2_t = simd_shuffle!(b, b, [1, 0]);
30824        let ret_val: float32x2_t = simd_shuffle!(a, b, [1, 3]);
30825        simd_shuffle!(ret_val, ret_val, [1, 0])
30826    }
30827}
30828#[doc = "Zip vectors"]
30829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"]
30830#[inline]
30831#[cfg(target_endian = "little")]
30832#[target_feature(enable = "neon")]
30833#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30834#[cfg_attr(
30835    all(test, not(target_env = "msvc"), target_endian = "little"),
30836    assert_instr(zip2)
30837)]
30838pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
30839    unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
30840}
30841#[doc = "Zip vectors"]
30842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"]
30843#[inline]
30844#[cfg(target_endian = "big")]
30845#[target_feature(enable = "neon")]
30846#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30847#[cfg_attr(
30848    all(test, not(target_env = "msvc"), target_endian = "little"),
30849    assert_instr(zip2)
30850)]
30851pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
30852    unsafe {
30853        let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
30854        let b: float32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
30855        let ret_val: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
30856        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
30857    }
30858}
30859#[doc = "Zip vectors"]
30860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"]
30861#[inline]
30862#[cfg(target_endian = "little")]
30863#[target_feature(enable = "neon")]
30864#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30865#[cfg_attr(
30866    all(test, not(target_env = "msvc"), target_endian = "little"),
30867    assert_instr(zip2)
30868)]
30869pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
30870    unsafe { simd_shuffle!(a, b, [1, 3]) }
30871}
30872#[doc = "Zip vectors"]
30873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"]
30874#[inline]
30875#[cfg(target_endian = "big")]
30876#[target_feature(enable = "neon")]
30877#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30878#[cfg_attr(
30879    all(test, not(target_env = "msvc"), target_endian = "little"),
30880    assert_instr(zip2)
30881)]
30882pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
30883    unsafe {
30884        let a: float64x2_t = simd_shuffle!(a, a, [1, 0]);
30885        let b: float64x2_t = simd_shuffle!(b, b, [1, 0]);
30886        let ret_val: float64x2_t = simd_shuffle!(a, b, [1, 3]);
30887        simd_shuffle!(ret_val, ret_val, [1, 0])
30888    }
30889}
30890#[doc = "Zip vectors"]
30891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"]
30892#[inline]
30893#[cfg(target_endian = "little")]
30894#[target_feature(enable = "neon")]
30895#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30896#[cfg_attr(
30897    all(test, not(target_env = "msvc"), target_endian = "little"),
30898    assert_instr(zip2)
30899)]
30900pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
30901    unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
30902}
30903#[doc = "Zip vectors"]
30904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"]
30905#[inline]
30906#[cfg(target_endian = "big")]
30907#[target_feature(enable = "neon")]
30908#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30909#[cfg_attr(
30910    all(test, not(target_env = "msvc"), target_endian = "little"),
30911    assert_instr(zip2)
30912)]
30913pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
30914    unsafe {
30915        let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
30916        let b: int8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
30917        let ret_val: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
30918        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
30919    }
30920}
30921#[doc = "Zip vectors"]
30922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"]
30923#[inline]
30924#[cfg(target_endian = "little")]
30925#[target_feature(enable = "neon")]
30926#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30927#[cfg_attr(
30928    all(test, not(target_env = "msvc"), target_endian = "little"),
30929    assert_instr(zip2)
30930)]
30931pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
30932    unsafe {
30933        simd_shuffle!(
30934            a,
30935            b,
30936            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
30937        )
30938    }
30939}
30940#[doc = "Zip vectors"]
30941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"]
30942#[inline]
30943#[cfg(target_endian = "big")]
30944#[target_feature(enable = "neon")]
30945#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30946#[cfg_attr(
30947    all(test, not(target_env = "msvc"), target_endian = "little"),
30948    assert_instr(zip2)
30949)]
30950pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
30951    unsafe {
30952        let a: int8x16_t =
30953            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
30954        let b: int8x16_t =
30955            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
30956        let ret_val: int8x16_t = simd_shuffle!(
30957            a,
30958            b,
30959            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
30960        );
30961        simd_shuffle!(
30962            ret_val,
30963            ret_val,
30964            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
30965        )
30966    }
30967}
30968#[doc = "Zip vectors"]
30969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"]
30970#[inline]
30971#[cfg(target_endian = "little")]
30972#[target_feature(enable = "neon")]
30973#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30974#[cfg_attr(
30975    all(test, not(target_env = "msvc"), target_endian = "little"),
30976    assert_instr(zip2)
30977)]
30978pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
30979    unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
30980}
30981#[doc = "Zip vectors"]
30982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"]
30983#[inline]
30984#[cfg(target_endian = "big")]
30985#[target_feature(enable = "neon")]
30986#[stable(feature = "neon_intrinsics", since = "1.59.0")]
30987#[cfg_attr(
30988    all(test, not(target_env = "msvc"), target_endian = "little"),
30989    assert_instr(zip2)
30990)]
30991pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
30992    unsafe {
30993        let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
30994        let b: int16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
30995        let ret_val: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
30996        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
30997    }
30998}
30999#[doc = "Zip vectors"]
31000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"]
31001#[inline]
31002#[cfg(target_endian = "little")]
31003#[target_feature(enable = "neon")]
31004#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31005#[cfg_attr(
31006    all(test, not(target_env = "msvc"), target_endian = "little"),
31007    assert_instr(zip2)
31008)]
31009pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
31010    unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
31011}
31012#[doc = "Zip vectors"]
31013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"]
31014#[inline]
31015#[cfg(target_endian = "big")]
31016#[target_feature(enable = "neon")]
31017#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31018#[cfg_attr(
31019    all(test, not(target_env = "msvc"), target_endian = "little"),
31020    assert_instr(zip2)
31021)]
31022pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
31023    unsafe {
31024        let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
31025        let b: int16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
31026        let ret_val: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
31027        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
31028    }
31029}
31030#[doc = "Zip vectors"]
31031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"]
31032#[inline]
31033#[cfg(target_endian = "little")]
31034#[target_feature(enable = "neon")]
31035#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31036#[cfg_attr(
31037    all(test, not(target_env = "msvc"), target_endian = "little"),
31038    assert_instr(zip2)
31039)]
31040pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
31041    unsafe { simd_shuffle!(a, b, [1, 3]) }
31042}
31043#[doc = "Zip vectors"]
31044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"]
31045#[inline]
31046#[cfg(target_endian = "big")]
31047#[target_feature(enable = "neon")]
31048#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31049#[cfg_attr(
31050    all(test, not(target_env = "msvc"), target_endian = "little"),
31051    assert_instr(zip2)
31052)]
31053pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
31054    unsafe {
31055        let a: int32x2_t = simd_shuffle!(a, a, [1, 0]);
31056        let b: int32x2_t = simd_shuffle!(b, b, [1, 0]);
31057        let ret_val: int32x2_t = simd_shuffle!(a, b, [1, 3]);
31058        simd_shuffle!(ret_val, ret_val, [1, 0])
31059    }
31060}
31061#[doc = "Zip vectors"]
31062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"]
31063#[inline]
31064#[cfg(target_endian = "little")]
31065#[target_feature(enable = "neon")]
31066#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31067#[cfg_attr(
31068    all(test, not(target_env = "msvc"), target_endian = "little"),
31069    assert_instr(zip2)
31070)]
31071pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
31072    unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
31073}
31074#[doc = "Zip vectors"]
31075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"]
31076#[inline]
31077#[cfg(target_endian = "big")]
31078#[target_feature(enable = "neon")]
31079#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31080#[cfg_attr(
31081    all(test, not(target_env = "msvc"), target_endian = "little"),
31082    assert_instr(zip2)
31083)]
31084pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
31085    unsafe {
31086        let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
31087        let b: int32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
31088        let ret_val: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
31089        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
31090    }
31091}
31092#[doc = "Zip vectors"]
31093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"]
31094#[inline]
31095#[cfg(target_endian = "little")]
31096#[target_feature(enable = "neon")]
31097#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31098#[cfg_attr(
31099    all(test, not(target_env = "msvc"), target_endian = "little"),
31100    assert_instr(zip2)
31101)]
31102pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
31103    unsafe { simd_shuffle!(a, b, [1, 3]) }
31104}
31105#[doc = "Zip vectors"]
31106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"]
31107#[inline]
31108#[cfg(target_endian = "big")]
31109#[target_feature(enable = "neon")]
31110#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31111#[cfg_attr(
31112    all(test, not(target_env = "msvc"), target_endian = "little"),
31113    assert_instr(zip2)
31114)]
31115pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
31116    unsafe {
31117        let a: int64x2_t = simd_shuffle!(a, a, [1, 0]);
31118        let b: int64x2_t = simd_shuffle!(b, b, [1, 0]);
31119        let ret_val: int64x2_t = simd_shuffle!(a, b, [1, 3]);
31120        simd_shuffle!(ret_val, ret_val, [1, 0])
31121    }
31122}
31123#[doc = "Zip vectors"]
31124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"]
31125#[inline]
31126#[cfg(target_endian = "little")]
31127#[target_feature(enable = "neon")]
31128#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31129#[cfg_attr(
31130    all(test, not(target_env = "msvc"), target_endian = "little"),
31131    assert_instr(zip2)
31132)]
31133pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
31134    unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
31135}
31136#[doc = "Zip vectors"]
31137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"]
31138#[inline]
31139#[cfg(target_endian = "big")]
31140#[target_feature(enable = "neon")]
31141#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31142#[cfg_attr(
31143    all(test, not(target_env = "msvc"), target_endian = "little"),
31144    assert_instr(zip2)
31145)]
31146pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
31147    unsafe {
31148        let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
31149        let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
31150        let ret_val: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
31151        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
31152    }
31153}
31154#[doc = "Zip vectors"]
31155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"]
31156#[inline]
31157#[cfg(target_endian = "little")]
31158#[target_feature(enable = "neon")]
31159#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31160#[cfg_attr(
31161    all(test, not(target_env = "msvc"), target_endian = "little"),
31162    assert_instr(zip2)
31163)]
31164pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
31165    unsafe {
31166        simd_shuffle!(
31167            a,
31168            b,
31169            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
31170        )
31171    }
31172}
31173#[doc = "Zip vectors"]
31174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"]
31175#[inline]
31176#[cfg(target_endian = "big")]
31177#[target_feature(enable = "neon")]
31178#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31179#[cfg_attr(
31180    all(test, not(target_env = "msvc"), target_endian = "little"),
31181    assert_instr(zip2)
31182)]
31183pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
31184    unsafe {
31185        let a: uint8x16_t =
31186            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
31187        let b: uint8x16_t =
31188            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
31189        let ret_val: uint8x16_t = simd_shuffle!(
31190            a,
31191            b,
31192            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
31193        );
31194        simd_shuffle!(
31195            ret_val,
31196            ret_val,
31197            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
31198        )
31199    }
31200}
31201#[doc = "Zip vectors"]
31202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"]
31203#[inline]
31204#[cfg(target_endian = "little")]
31205#[target_feature(enable = "neon")]
31206#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31207#[cfg_attr(
31208    all(test, not(target_env = "msvc"), target_endian = "little"),
31209    assert_instr(zip2)
31210)]
31211pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
31212    unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
31213}
31214#[doc = "Zip vectors"]
31215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"]
31216#[inline]
31217#[cfg(target_endian = "big")]
31218#[target_feature(enable = "neon")]
31219#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31220#[cfg_attr(
31221    all(test, not(target_env = "msvc"), target_endian = "little"),
31222    assert_instr(zip2)
31223)]
31224pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
31225    unsafe {
31226        let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
31227        let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
31228        let ret_val: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
31229        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
31230    }
31231}
31232#[doc = "Zip vectors"]
31233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"]
31234#[inline]
31235#[cfg(target_endian = "little")]
31236#[target_feature(enable = "neon")]
31237#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31238#[cfg_attr(
31239    all(test, not(target_env = "msvc"), target_endian = "little"),
31240    assert_instr(zip2)
31241)]
31242pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
31243    unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
31244}
31245#[doc = "Zip vectors"]
31246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"]
31247#[inline]
31248#[cfg(target_endian = "big")]
31249#[target_feature(enable = "neon")]
31250#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31251#[cfg_attr(
31252    all(test, not(target_env = "msvc"), target_endian = "little"),
31253    assert_instr(zip2)
31254)]
31255pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
31256    unsafe {
31257        let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
31258        let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
31259        let ret_val: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
31260        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
31261    }
31262}
31263#[doc = "Zip vectors"]
31264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"]
31265#[inline]
31266#[cfg(target_endian = "little")]
31267#[target_feature(enable = "neon")]
31268#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31269#[cfg_attr(
31270    all(test, not(target_env = "msvc"), target_endian = "little"),
31271    assert_instr(zip2)
31272)]
31273pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
31274    unsafe { simd_shuffle!(a, b, [1, 3]) }
31275}
31276#[doc = "Zip vectors"]
31277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"]
31278#[inline]
31279#[cfg(target_endian = "big")]
31280#[target_feature(enable = "neon")]
31281#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31282#[cfg_attr(
31283    all(test, not(target_env = "msvc"), target_endian = "little"),
31284    assert_instr(zip2)
31285)]
31286pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
31287    unsafe {
31288        let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]);
31289        let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]);
31290        let ret_val: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
31291        simd_shuffle!(ret_val, ret_val, [1, 0])
31292    }
31293}
31294#[doc = "Zip vectors"]
31295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"]
31296#[inline]
31297#[cfg(target_endian = "little")]
31298#[target_feature(enable = "neon")]
31299#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31300#[cfg_attr(
31301    all(test, not(target_env = "msvc"), target_endian = "little"),
31302    assert_instr(zip2)
31303)]
31304pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
31305    unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
31306}
31307#[doc = "Zip vectors"]
31308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"]
31309#[inline]
31310#[cfg(target_endian = "big")]
31311#[target_feature(enable = "neon")]
31312#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31313#[cfg_attr(
31314    all(test, not(target_env = "msvc"), target_endian = "little"),
31315    assert_instr(zip2)
31316)]
31317pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
31318    unsafe {
31319        let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
31320        let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
31321        let ret_val: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
31322        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
31323    }
31324}
31325#[doc = "Zip vectors"]
31326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"]
31327#[inline]
31328#[cfg(target_endian = "little")]
31329#[target_feature(enable = "neon")]
31330#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31331#[cfg_attr(
31332    all(test, not(target_env = "msvc"), target_endian = "little"),
31333    assert_instr(zip2)
31334)]
31335pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
31336    unsafe { simd_shuffle!(a, b, [1, 3]) }
31337}
31338#[doc = "Zip vectors"]
31339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"]
31340#[inline]
31341#[cfg(target_endian = "big")]
31342#[target_feature(enable = "neon")]
31343#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31344#[cfg_attr(
31345    all(test, not(target_env = "msvc"), target_endian = "little"),
31346    assert_instr(zip2)
31347)]
31348pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
31349    unsafe {
31350        let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]);
31351        let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]);
31352        let ret_val: uint64x2_t = simd_shuffle!(a, b, [1, 3]);
31353        simd_shuffle!(ret_val, ret_val, [1, 0])
31354    }
31355}
31356#[doc = "Zip vectors"]
31357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"]
31358#[inline]
31359#[cfg(target_endian = "little")]
31360#[target_feature(enable = "neon")]
31361#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31362#[cfg_attr(
31363    all(test, not(target_env = "msvc"), target_endian = "little"),
31364    assert_instr(zip2)
31365)]
31366pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
31367    unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
31368}
31369#[doc = "Zip vectors"]
31370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"]
31371#[inline]
31372#[cfg(target_endian = "big")]
31373#[target_feature(enable = "neon")]
31374#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31375#[cfg_attr(
31376    all(test, not(target_env = "msvc"), target_endian = "little"),
31377    assert_instr(zip2)
31378)]
31379pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
31380    unsafe {
31381        let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
31382        let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
31383        let ret_val: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
31384        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
31385    }
31386}
31387#[doc = "Zip vectors"]
31388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"]
31389#[inline]
31390#[cfg(target_endian = "little")]
31391#[target_feature(enable = "neon")]
31392#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31393#[cfg_attr(
31394    all(test, not(target_env = "msvc"), target_endian = "little"),
31395    assert_instr(zip2)
31396)]
31397pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
31398    unsafe {
31399        simd_shuffle!(
31400            a,
31401            b,
31402            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
31403        )
31404    }
31405}
31406#[doc = "Zip vectors"]
31407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"]
31408#[inline]
31409#[cfg(target_endian = "big")]
31410#[target_feature(enable = "neon")]
31411#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31412#[cfg_attr(
31413    all(test, not(target_env = "msvc"), target_endian = "little"),
31414    assert_instr(zip2)
31415)]
31416pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
31417    unsafe {
31418        let a: poly8x16_t =
31419            simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
31420        let b: poly8x16_t =
31421            simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]);
31422        let ret_val: poly8x16_t = simd_shuffle!(
31423            a,
31424            b,
31425            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
31426        );
31427        simd_shuffle!(
31428            ret_val,
31429            ret_val,
31430            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
31431        )
31432    }
31433}
31434#[doc = "Zip vectors"]
31435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"]
31436#[inline]
31437#[cfg(target_endian = "little")]
31438#[target_feature(enable = "neon")]
31439#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31440#[cfg_attr(
31441    all(test, not(target_env = "msvc"), target_endian = "little"),
31442    assert_instr(zip2)
31443)]
31444pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
31445    unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
31446}
31447#[doc = "Zip vectors"]
31448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"]
31449#[inline]
31450#[cfg(target_endian = "big")]
31451#[target_feature(enable = "neon")]
31452#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31453#[cfg_attr(
31454    all(test, not(target_env = "msvc"), target_endian = "little"),
31455    assert_instr(zip2)
31456)]
31457pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
31458    unsafe {
31459        let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]);
31460        let b: poly16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]);
31461        let ret_val: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
31462        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
31463    }
31464}
31465#[doc = "Zip vectors"]
31466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"]
31467#[inline]
31468#[cfg(target_endian = "little")]
31469#[target_feature(enable = "neon")]
31470#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31471#[cfg_attr(
31472    all(test, not(target_env = "msvc"), target_endian = "little"),
31473    assert_instr(zip2)
31474)]
31475pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
31476    unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
31477}
31478#[doc = "Zip vectors"]
31479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"]
31480#[inline]
31481#[cfg(target_endian = "big")]
31482#[target_feature(enable = "neon")]
31483#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31484#[cfg_attr(
31485    all(test, not(target_env = "msvc"), target_endian = "little"),
31486    assert_instr(zip2)
31487)]
31488pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
31489    unsafe {
31490        let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]);
31491        let b: poly16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]);
31492        let ret_val: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
31493        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
31494    }
31495}
31496#[doc = "Zip vectors"]
31497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"]
31498#[inline]
31499#[cfg(target_endian = "little")]
31500#[target_feature(enable = "neon")]
31501#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31502#[cfg_attr(
31503    all(test, not(target_env = "msvc"), target_endian = "little"),
31504    assert_instr(zip2)
31505)]
31506pub fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
31507    unsafe { simd_shuffle!(a, b, [1, 3]) }
31508}
31509#[doc = "Zip vectors"]
31510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"]
31511#[inline]
31512#[cfg(target_endian = "big")]
31513#[target_feature(enable = "neon")]
31514#[stable(feature = "neon_intrinsics", since = "1.59.0")]
31515#[cfg_attr(
31516    all(test, not(target_env = "msvc"), target_endian = "little"),
31517    assert_instr(zip2)
31518)]
31519pub fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
31520    unsafe {
31521        let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]);
31522        let b: poly64x2_t = simd_shuffle!(b, b, [1, 0]);
31523        let ret_val: poly64x2_t = simd_shuffle!(a, b, [1, 3]);
31524        simd_shuffle!(ret_val, ret_val, [1, 0])
31525    }
31526}