bin: ["c_emulator/riscv_sim_RV64" "c_emulator/riscv_sim_RV32"]
share: [ "model/riscv_insts_mext.sail" {"model/riscv_insts_mext.sail"} "model/riscv_insts_cext.sail" {"model/riscv_insts_cext.sail"} "model/riscv_csr_map.sail" {"model/riscv_csr_map.sail"} "model/riscv_addr_checks.sail" {"model/riscv_addr_checks.sail"} "model/riscv_sys_exceptions.sail" {"model/riscv_sys_exceptions.sail"} "model/riscv_vmem_sv32.sail" {"model/riscv_vmem_sv32.sail"} "model/riscv_types.sail" {"model/riscv_types.sail"} "model/riscv_addr_checks_common.sail" {"model/riscv_addr_checks_common.sail"} "model/riscv_step.sail" {"model/riscv_step.sail"} "model/riscv_step_rvfi.sail" {"model/riscv_step_rvfi.sail"} "model/riscv_step_common.sail" {"model/riscv_step_common.sail"} "model/riscv_platform.sail" {"model/riscv_platform.sail"} "model/riscv_insts_next.sail" {"model/riscv_insts_next.sail"} "model/riscv_sys_control.sail" {"model/riscv_sys_control.sail"} "model/riscv_insts_begin.sail" {"model/riscv_insts_begin.sail"} "model/riscv_vmem_sv48.sail" {"model/riscv_vmem_sv48.sail"} "model/riscv_csr_ext.sail" {"model/riscv_csr_ext.sail"} "model/riscv_regs.sail" {"model/riscv_regs.sail"} "model/riscv_fetch.sail" {"model/riscv_fetch.sail"} "model/riscv_step_ext.sail" {"model/riscv_step_ext.sail"} "model/riscv_fetch_rvfi.sail" {"model/riscv_fetch_rvfi.sail"} "model/riscv_termination_rv32.sail" {"model/riscv_termination_rv32.sail"} "model/riscv_jalr_rmem.sail" {"model/riscv_jalr_rmem.sail"} "model/riscv_vmem_common.sail" {"model/riscv_vmem_common.sail"} "model/riscv_decode_ext.sail" {"model/riscv_decode_ext.sail"} "model/riscv_next_regs.sail" {"model/riscv_next_regs.sail"} "model/riscv_xlen64.sail" {"model/riscv_xlen64.sail"} "model/riscv_insts_zicsr.sail" {"model/riscv_insts_zicsr.sail"} "model/riscv_pc_access.sail" {"model/riscv_pc_access.sail"} "model/riscv_insts_rmem.sail" {"model/riscv_insts_rmem.sail"} "model/prelude_mapping.sail" {"model/prelude_mapping.sail"} "model/riscv_vmem_rv32.sail" {"model/riscv_vmem_rv32.sail"} "model/riscv_insts_end.sail" {"model/riscv_insts_end.sail"} "model/riscv_ext_regs.sail" {"model/riscv_ext_regs.sail"} "model/rvfi_dii.sail" {"model/rvfi_dii.sail"} "model/prelude_mem.sail" {"model/prelude_mem.sail"} "model/riscv_duopod.sail" {"model/riscv_duopod.sail"} "model/riscv_sync_exception.sail" {"model/riscv_sync_exception.sail"} "model/riscv_vmem_sv39.sail" {"model/riscv_vmem_sv39.sail"} "model/riscv_next_control.sail" {"model/riscv_next_control.sail"} "model/riscv_vmem_rv64.sail" {"model/riscv_vmem_rv64.sail"} "model/riscv_analysis.sail" {"model/riscv_analysis.sail"} "model/main.sail" {"model/main.sail"} "model/riscv_vmem_tlb.sail" {"model/riscv_vmem_tlb.sail"} "model/riscv_sys_regs.sail" {"model/riscv_sys_regs.sail"} "model/riscv_termination_rv64.sail" {"model/riscv_termination_rv64.sail"} "model/prelude_mem_metadata.sail" {"model/prelude_mem_metadata.sail"} "model/prelude.sail" {"model/prelude.sail"} "model/riscv_xlen32.sail" {"model/riscv_xlen32.sail"} "model/riscv_termination_common.sail" {"model/riscv_termination_common.sail"} "model/riscv_insts_base.sail" {"model/riscv_insts_base.sail"} "model/riscv_jalr_seq.sail" {"model/riscv_jalr_seq.sail"} "model/riscv_reg_type.sail" {"model/riscv_reg_type.sail"} "model/riscv_mem.sail" {"model/riscv_mem.sail"} "model/riscv_insts_aext.sail" {"model/riscv_insts_aext.sail"} "c_emulator/riscv_platform.c" {"c_emulator/riscv_platform.c"} "c_emulator/riscv_sim.c" {"c_emulator/riscv_sim.c"} "c_emulator/riscv_platform_impl.c" {"c_emulator/riscv_platform_impl.c"} "c_emulator/riscv_prelude.c" {"c_emulator/riscv_prelude.c"} "c_emulator/riscv_platform_impl.h" {"c_emulator/riscv_platform_impl.h"} "c_emulator/riscv_prelude.h" {"c_emulator/riscv_prelude.h"} "c_emulator/riscv_sail.h" {"c_emulator/riscv_sail.h"} "c_emulator/riscv_platform.h" {"c_emulator/riscv_platform.h"} "c_emulator/riscv_config.h" {"c_emulator/riscv_config.h"} ]