From ad348876ca17529c4d7fe2f3d2ec227f9f3026e1 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Fri, 19 Jul 2019 11:21:40 +0100 Subject: Add a new pc access function to get the architectural PC: on CHERI this is not what is in the PC register because the architectural PC is the offset of PCC and the PC register stores the absolute PC (at present -- may review this decision in future). This allows fix for AUIPC and RVFI reported PC. --- model/riscv_insts_base.sail | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'model/riscv_insts_base.sail') diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail index 14a626e..9327948 100644 --- a/model/riscv_insts_base.sail +++ b/model/riscv_insts_base.sail @@ -17,7 +17,7 @@ function clause execute UTYPE(imm, rd, op) = { let off : xlenbits = EXTS(imm @ 0x000); let ret : xlenbits = match op { RISCV_LUI => off, - RISCV_AUIPC => PC + off + RISCV_AUIPC => get_arch_pc() + off }; X(rd) = ret; RETIRE_SUCCESS -- cgit v1.1