From a381a832bb39bb7571725f75c27dc257762cd693 Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk>
Date: Mon, 19 Aug 2019 18:49:23 +0100
Subject: RISC-V spec, without implicit casts

---
 model/riscv_fetch.sail | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'model/riscv_fetch.sail')

diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail
index ae8748c..c52a70d 100644
--- a/model/riscv_fetch.sail
+++ b/model/riscv_fetch.sail
@@ -12,7 +12,7 @@ function fetch() -> FetchResult =
   match ext_fetch_check_pc(PC, PC) {
     Ext_FetchAddr_Error(e)   => F_Ext_Error(e),
     Ext_FetchAddr_OK(use_pc) => {
-      if   (use_pc[0] != 0b0 | (use_pc[1] != 0b0 & (~ (haveRVC()))))
+      if   (use_pc[0] != bitzero | (use_pc[1] != bitzero & (~ (haveRVC()))))
       then F_Error(E_Fetch_Addr_Align, PC)
       else match translateAddr(use_pc, Execute) {
         TR_Failure(e)     => F_Error(e, PC),
-- 
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