From c90cf2e6eff5fa4ef7b93cc2020166dea7453fc6 Mon Sep 17 00:00:00 2001 From: Xinlai Wan Date: Tue, 27 Dec 2022 20:23:10 +0800 Subject: RISC-V Vector Extension Support This PR adds the following: General Framework and Configurations: * Introduced the V extension's general framework and configuration setting instructions. * Updated model/riscv_insts_vext_vset.sail and effect matching functions in riscv_vlen.sail. * Addressed code formatting issues and made revisions post the Nov 22 meeting. * Co-authored by Nicolas Brunie and Jessica Clarke. Vector Load/Store Instructions: * Integrated vector load and store instructions. * Enhanced the implementation of SEW, LMUL, VLEN and removed real numbers from the code. * Updated vstart settings and removed unnecessary assert statements. * Rectified bugs in vleff instructions and overhauled coding styles. * Incorporated guards for vector encdec clauses and optimized memory access post vector load/store failures. Vector Integer/Fixed-Point Instructions: * Added vector integer/fixed-point arithmetic and mask instructions. * Improved vector EEW and EMUL checking functions and introduced illegal instruction check functions. * Fine-tuned code formatting for vector instruction checks. Vector Floating-Point Instructions: * Rolled out vector floating-point instructions and updated their conversion counterparts. * Refreshed copyright headers specific to the vector extension code. Vector Reduction and Mask Instructions: * Integrated vector mask and reduction instructions. * Addressed register overlap checks for vector mask instructions. Miscellaneous Enhancements and Fixes: * Updated vector CSR vtype.vill settings and judgements. * Systematized patterns for vector illegal instruction checks. * Rectified issues in vector load/store and reduction operations. * Purged redundant elements from the V extension code and vector floating-point functions. * Cleaned up softfloat makefiles and renamed EXTZ and EXTS within the V extension code. * Addressed a clang-format check issue and NaN boxing anomalies. Provided annotations for pending RVV configurations. * Initialized default VLEN value and set vlenb CSR. * Set constraints for vector variable initialization and added mstatus.VS settings specific to the vector extension. --- c_emulator/riscv_sim.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'c_emulator/riscv_sim.c') diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index 276be0c..9194518 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -246,6 +246,7 @@ static int process_args(int argc, char **argv) "N" "I" "F" + "W" "i" "s" "p" @@ -300,6 +301,10 @@ static int process_args(int argc, char **argv) fprintf(stderr, "disabling floating point (F and D extensions).\n"); rv_enable_fdext = false; break; + case 'W': + fprintf(stderr, "disabling RVV vector instructions.\n"); + rv_enable_vext = false; + break; case 'i': fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n"); rv_mtval_has_illegal_inst_bits = true; -- cgit v1.1