From f14e8ebac39bf6771f0d1775d5145f7f6549c5ea Mon Sep 17 00:00:00 2001
From: Robert Norton <rmn30@cam.ac.uk>
Date: Mon, 29 Apr 2019 14:31:18 +0100
Subject: Add a post decode hook aimed at implementing CHERI capability mode.

---
 Makefile                     | 4 ++--
 model/riscv_decode_ext.sail  | 2 ++
 model/riscv_step.sail        | 4 ++--
 model/riscv_step_common.sail | 5 +++++
 4 files changed, 11 insertions(+), 4 deletions(-)
 create mode 100644 model/riscv_decode_ext.sail

diff --git a/Makefile b/Makefile
index fe6f722..7683b1e 100644
--- a/Makefile
+++ b/Makefile
@@ -47,8 +47,8 @@ SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_sys_regs.sail riscv_e
 SAIL_ARCH_SRCS = $(PRELUDE) riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
 SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS)
 SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS)
-SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_fetch.sail riscv_step.sail
-RVFI_STEP_SRCS = riscv_step_common.sail riscv_step_rvfi.sail riscv_fetch_rvfi.sail riscv_step.sail
+SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail
+RVFI_STEP_SRCS = riscv_step_common.sail riscv_step_rvfi.sail riscv_decode_ext.sail riscv_fetch_rvfi.sail riscv_step.sail
 
 # Control inclusion of 64-bit only riscv_analysis
 ifeq ($(ARCH),RV32)
diff --git a/model/riscv_decode_ext.sail b/model/riscv_decode_ext.sail
new file mode 100644
index 0000000..2f4c5af
--- /dev/null
+++ b/model/riscv_decode_ext.sail
@@ -0,0 +1,2 @@
+/* Default (identity) implementation of post decode hook. */
+function ext_post_decode_hook(x) = x
\ No newline at end of file
diff --git a/model/riscv_step.sail b/model/riscv_step.sail
index 0b6e531..fda2777 100644
--- a/model/riscv_step.sail
+++ b/model/riscv_step.sail
@@ -35,7 +35,7 @@ function step(step_no) = {
             /* check for RVC once here instead of every RVC execute clause. */
             if haveRVC() then {
               nextPC = PC + 2;
-              (execute(ast), true)
+              (execute(ext_post_decode_hook(ast)), true)
              } else {
               handle_illegal();
               (false, true)
@@ -45,7 +45,7 @@ function step(step_no) = {
             let ast = decode(w);
             print_instr("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") " ^ ast);
             nextPC = PC + 4;
-            (execute(ast), true)
+            (execute(ext_post_decode_hook(ast)), true)
           }
         }
       }
diff --git a/model/riscv_step_common.sail b/model/riscv_step_common.sail
index 145b5bd..2cbc32c 100644
--- a/model/riscv_step_common.sail
+++ b/model/riscv_step_common.sail
@@ -8,3 +8,8 @@ union FetchResult = {
   F_RVC       : half,                      /* Compressed ISA */
   F_Error     : (ExceptionType, xlenbits)  /* standard exception and PC */
 }
+
+/*!
+A hook for extensions that want to interpose on decoded instructions.
+ */
+val ext_post_decode_hook : ast -> ast effect {rreg}
-- 
cgit v1.1