From af5c2f2647f1d4f6985f3590fb3f881de6b348cd Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 18 May 2024 00:37:30 -0700
Subject: Update bitfield syntax

---
 model/riscv_pmp_regs.sail | 6 +++---
 model/riscv_vmem.sail     | 4 ++--
 model/riscv_vmem_pte.sail | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/model/riscv_pmp_regs.sail b/model/riscv_pmp_regs.sail
index a9e4676..65afd2b 100644
--- a/model/riscv_pmp_regs.sail
+++ b/model/riscv_pmp_regs.sail
@@ -68,7 +68,7 @@ function pmpReadCfgReg(n : range(0, 15)) -> xlenbits = {
 
 function pmpReadAddrReg(n : range(0, 63)) -> xlenbits = {
   let G = sys_pmp_grain();
-  let match_type = pmpcfg_n[n].A();
+  let match_type = pmpcfg_n[n][A];
   let addr = pmpaddr_n[n];
 
   match match_type[1] {
@@ -104,12 +104,12 @@ function pmpWriteCfg(n: range(0, 63), cfg: Pmpcfg_ent, v: bits(8)) -> Pmpcfg_ent
     // "The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved."
     // In this implementation if R=0 and W=1 then R, W and X are all set to 0.
     // This is the least risky option from a security perspective.
-    let cfg = if cfg.W() == 0b1 & cfg.R() == 0b0 then [cfg with X = 0b0, W = 0b0, R = 0b0] else cfg;
+    let cfg = if cfg[W] == 0b1 & cfg[R] == 0b0 then [cfg with X = 0b0, W = 0b0, R = 0b0] else cfg;
 
     // "When G >= 1, the NA4 mode is not selectable."
     // In this implementation we set it to OFF if NA4 is selected.
     // This is the least risky option from a security perspective.
-    let cfg = if sys_pmp_grain() >= 1 & pmpAddrMatchType_of_bits(cfg.A()) == NA4
+    let cfg = if sys_pmp_grain() >= 1 & pmpAddrMatchType_of_bits(cfg[A]) == NA4
               then [cfg with A = pmpAddrMatchType_to_bits(OFF)]
               else cfg;
 
diff --git a/model/riscv_vmem.sail b/model/riscv_vmem.sail
index 6e29007..2bb96fe 100644
--- a/model/riscv_vmem.sail
+++ b/model/riscv_vmem.sail
@@ -426,8 +426,8 @@ function translateAddr(vAddr   : xlenbits,
   if not(valid_va) then
     TR_Failure(translationException(ac, PTW_Invalid_Addr()), init_ext_ptw)
   else {
-    let mxr               = mstatus.MXR() == 0b1;
-    let do_sum            = mstatus.SUM() == 0b1;
+    let mxr               = mstatus[MXR] == 0b1;
+    let do_sum            = mstatus[SUM] == 0b1;
     let asid   : asidbits = satp_to_asid(satp);
     let ptb    : bits(64) = satp_to_PT_base(satp);
     let tr_result1 = translate(sv_params,
diff --git a/model/riscv_vmem_pte.sail b/model/riscv_vmem_pte.sail
index dfe032c..07a94a3 100644
--- a/model/riscv_vmem_pte.sail
+++ b/model/riscv_vmem_pte.sail
@@ -128,7 +128,7 @@ function update_PTE_Bits(sv_params : SV_Params,
     let pte_flags = [pte_flags with
                       A = 0b1,
                       D = (if update_d then 0b1 else pte_flags[D])];
-    Some(pte[63 .. 8] @ pte_flags.bits())
+    Some(pte[63 .. 8] @ pte_flags.bits)
   }
   else
     None()
-- 
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