From 93eb67eebdb100b4f5d1e5ceab64ba194030d9f8 Mon Sep 17 00:00:00 2001 From: Prashanth Mundkur Date: Thu, 18 Jul 2019 13:27:57 -0700 Subject: Add info about the C emulator to the reading guide. --- doc/ReadingGuide.md | 29 +++++++++++++++ doc/figs/Makefile | 11 +++--- doc/figs/riscvcsimdeps.svg | 91 ++++++++++++++++++++++++++++++++++++++++++++++ doc/figs/riscvcsimdeps.tex | 61 +++++++++++++++++++++++++++++++ 4 files changed, 186 insertions(+), 6 deletions(-) create mode 100644 doc/figs/riscvcsimdeps.svg create mode 100644 doc/figs/riscvcsimdeps.tex diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md index 46d9f65..152267f 100644 --- a/doc/ReadingGuide.md +++ b/doc/ReadingGuide.md @@ -118,3 +118,32 @@ such as the platform memory map. Note that the files above are listed in dependency order, i.e. files earlier in the order do not depend on later files. + +Structure of the C emulator +---------------------------- + +The diagram below illustrates how the C emulator is built from the +Sail model. The OCaml emulator follows the same approach. + + + +The nodes that are not colored are the handwritten C files for the C +emulator. + +`riscv_sim` is the top level file for the C emulator: it processes +command line options, initializes the platform model with any ISA +implementation choices if specified, and loads the ELF program or OS +image into raw memory, including any ROM firmware such as the Berkeley +boot loader and DeviceTree binary blobs, and initializes the memory +map. + +The generated C model `riscv_model_$ARCH` is built from the Sail +sources by the Sail compiler. It contains calls to the platform +interface `riscv_platform` for platform-specific information; the +latter is typically defined as externally specified in the Sail file +`riscv_platform.sail`. + +The Sail system provides a C library for use with its C backend, which +provides the low-level details of the implementation of raw memory and +bitvectors (typically optimized to use the native machine word +representation). diff --git a/doc/figs/Makefile b/doc/figs/Makefile index 80cdbdc..59fe6cb 100644 --- a/doc/figs/Makefile +++ b/doc/figs/Makefile @@ -1,12 +1,11 @@ -FIG=riscvspecdeps +all: riscvspecdeps.svg riscvcsimdeps.svg -all: $(FIG).svg - -$(FIG).pdf: $(FIG).tex +%.pdf: %.tex pdflatex $< -$(FIG).svg: $(FIG).pdf $(FIG).tex +%.svg: %.pdf %.tex dvisvgm -Z 1.5 --pdf $< clean: - rm $(FIG).pdf $(FIG).aux $(FIG).log + rm riscvspecdeps.pdf riscvspecdeps.aux riscvspecdeps.log + rm riscvcsimdeps.pdf riscvcsimdeps.aux riscvcsimdeps.log diff --git a/doc/figs/riscvcsimdeps.svg b/doc/figs/riscvcsimdeps.svg new file mode 100644 index 0000000..f2ac160 --- /dev/null +++ b/doc/figs/riscvcsimdeps.svg @@ -0,0 +1,91 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/doc/figs/riscvcsimdeps.tex b/doc/figs/riscvcsimdeps.tex new file mode 100644 index 0000000..b78c70f --- /dev/null +++ b/doc/figs/riscvcsimdeps.tex @@ -0,0 +1,61 @@ +\documentclass[tikz]{standalone} + +\usepackage{tikz} +\usetikzlibrary{calc,positioning} + +\begin{document} +\begin{tikzpicture}[ + node distance=5mm, + align=center, + base/.style={rectangle, rounded corners=3mm, minimum size=10mm, thick, draw=black}, + cmodel/.style={base, fill=yellow!50}, + sail/.style={base, fill=red!30}, + c/.style={base}, + csail/.style={base,fill=red!10}, + dep/.style={black, very thick}, + gen/.style={red, very thick} + ] + + \node (cmodel) [cmodel] {\textbf{C translation}\\ + \texttt{riscv\_model\_\$ARCH}}; + + + \node (sailmodel) [sail, above right=of cmodel] {\textbf{Sail model}\\ + \texttt{*.sail}}; + + \node (plat) [c, below right=of cmodel] {\textbf{C platform interface}\\ + \texttt{riscv\_platform}\\ + ISA options\\ + memory map\\ + \textsc{lr/sc} reservation}; + + \node (platimpl) [c, below=of plat] {\textbf{C platform implementation}\\ + \texttt{riscv\_platform\_impl}}; + + \node (csim) [c, above left=of cmodel] {\textbf{C Simulator}\\ + \texttt{riscv\_sim}\\ + command line options\\ + initialization\\ + exit code}; + + \coordinate (clib) at ($(cmodel)!1.5!(cmodel |- platimpl)$); + + \node (csail) [csail] at (clib) {\textbf{C Sail library}\\ + \texttt{sail,rts,elf}\\ + Sail values\\ + raw memory\\ + ELF loading}; + + \draw[->,gen] (sailmodel) edge (cmodel); + + \draw[->,dep] (cmodel) edge (plat); + + \draw[->,dep] (plat) edge (platimpl); + + \draw[->,dep] (csim) edge (cmodel) + edge [out=-90,in=180] (platimpl) + edge [out=-90,in=135] (csail); + + \draw[->,dep] (platimpl) edge (csail); +\end{tikzpicture} +\end{document} -- cgit v1.1