From 66095cacc025de50eddeccb5d0f166846df1a717 Mon Sep 17 00:00:00 2001 From: Martin Berger Date: Tue, 30 Apr 2024 00:09:59 +0100 Subject: fixup! Add Svinval extension. --- c_emulator/riscv_platform.c | 6 ++++++ c_emulator/riscv_platform.h | 1 + c_emulator/riscv_platform_impl.c | 1 + c_emulator/riscv_platform_impl.h | 1 + c_emulator/riscv_sim.c | 2 ++ model/riscv_sys_regs.sail | 4 ++++ ocaml_emulator/platform.ml | 2 ++ ocaml_emulator/riscv_ocaml_sim.ml | 3 +++ 8 files changed, 20 insertions(+) diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c index 6544de6..2bd5c63 100644 --- a/c_emulator/riscv_platform.c +++ b/c_emulator/riscv_platform.c @@ -32,6 +32,12 @@ bool sys_enable_fdext(unit u) return rv_enable_fdext; } +bool sys_enable_svinval(unit u) +{ + return rv_enable_svinval; +} + + bool sys_enable_zcb(unit u) { return rv_enable_zcb; diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h index 4a53d12..3cc6f02 100644 --- a/c_emulator/riscv_platform.h +++ b/c_emulator/riscv_platform.h @@ -4,6 +4,7 @@ bool sys_enable_rvc(unit); bool sys_enable_next(unit); bool sys_enable_fdext(unit); +bool sys_enable_svinval(unit); bool sys_enable_zcb(unit); bool sys_enable_zfinx(unit); bool sys_enable_writable_misa(unit); diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c index 449bb1d..077fc50 100644 --- a/c_emulator/riscv_platform_impl.c +++ b/c_emulator/riscv_platform_impl.c @@ -6,6 +6,7 @@ uint64_t rv_pmp_count = 0; uint64_t rv_pmp_grain = 0; +bool rv_enable_svinval = false; bool rv_enable_zcb = false; bool rv_enable_zfinx = false; bool rv_enable_rvc = true; diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h index d377c9c..c4289e6 100644 --- a/c_emulator/riscv_platform_impl.h +++ b/c_emulator/riscv_platform_impl.h @@ -11,6 +11,7 @@ extern uint64_t rv_pmp_count; extern uint64_t rv_pmp_grain; +extern bool rv_enable_svinval; extern bool rv_enable_zcb; extern bool rv_enable_zfinx; extern bool rv_enable_rvc; diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index bf68da2..ee90b92 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -53,6 +53,7 @@ const char *RV32ISA = "RV32IMAC"; #define OPT_ENABLE_WRITABLE_FIOM 1001 #define OPT_PMP_COUNT 1002 #define OPT_PMP_GRAIN 1003 +#define OPT_ENABLE_SVINVAL 10017 #define OPT_ENABLE_ZCB 10014 static bool do_dump_dts = false; @@ -146,6 +147,7 @@ static struct option options[] = { {"inst-limit", required_argument, 0, 'l' }, {"enable-zfinx", no_argument, 0, 'x' }, {"enable-writable-fiom", no_argument, 0, OPT_ENABLE_WRITABLE_FIOM}, + {"enable-svinval", no_argument, 0, OPT_ENABLE_SVINVAL }, {"enable-zcb", no_argument, 0, OPT_ENABLE_ZCB }, #ifdef SAILCOV {"sailcov-file", required_argument, 0, 'c' }, diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index f3cd7e3..6c66492 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -84,6 +84,8 @@ val sys_enable_writable_misa = {c: "sys_enable_writable_misa", ocaml: "Platform. val sys_enable_rvc = {c: "sys_enable_rvc", ocaml: "Platform.enable_rvc", _: "sys_enable_rvc"} : unit -> bool /* whether misa.{f,d} were enabled at boot */ val sys_enable_fdext = {c: "sys_enable_fdext", ocaml: "Platform.enable_fdext", _: "sys_enable_fdext"} : unit -> bool +/* whether Svinval was enabled at boot */ +val sys_enable_svinval = {c: "sys_enable_svinval", ocaml: "Platform.enable_svinval", _: "sys_enable_svinval"} : unit -> bool /* whether Zcb was enabled at boot */ val sys_enable_zcb = {c: "sys_enable_zcb", ocaml: "Platform.enable_zcb", _: "sys_enable_zcb"} : unit -> bool /* whether zfinx was enabled at boot */ @@ -311,6 +313,8 @@ function haveZfh() -> bool = (misa[F] == 0b1) & (mstatus[FS] != 0b00) /* V extension has to enable both via misa.V as well as mstatus.VS */ function haveVExt() -> bool = (misa[V] == 0b1) & (mstatus[VS] != 0b00) +function haveSvinval() -> bool = sys_enable_svinval() + /* Zcb has simple code-size saving instructions. (The Zcb extension depends on the Zca extension.) */ function haveZcb() -> bool = sys_enable_zcb() diff --git a/ocaml_emulator/platform.ml b/ocaml_emulator/platform.ml index 2f0aaaf..1d2f3de 100644 --- a/ocaml_emulator/platform.ml +++ b/ocaml_emulator/platform.ml @@ -10,6 +10,7 @@ let config_enable_writable_misa = ref true let config_enable_dirty_update = ref false let config_enable_misaligned_access = ref false let config_mtval_has_illegal_inst_bits = ref false +let config_enable_svinval = ref false let config_enable_zcb = ref false let config_enable_writable_fiom = ref true let config_enable_vext = ref true @@ -89,6 +90,7 @@ let enable_vext () = !config_enable_vext let enable_dirty_update () = !config_enable_dirty_update let enable_misaligned_access () = !config_enable_misaligned_access let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits +let enable_svinval () = !config_enable_svinval let enable_zcb () = !config_enable_zcb let enable_zfinx () = false let enable_writable_fiom () = !config_enable_writable_fiom diff --git a/ocaml_emulator/riscv_ocaml_sim.ml b/ocaml_emulator/riscv_ocaml_sim.ml index 8dad8a4..56be8d8 100644 --- a/ocaml_emulator/riscv_ocaml_sim.ml +++ b/ocaml_emulator/riscv_ocaml_sim.ml @@ -53,6 +53,9 @@ let options = Arg.align ([("-dump-dts", ("-mtval-has-illegal-inst-bits", Arg.Set P.config_mtval_has_illegal_inst_bits, " mtval stores instruction bits on an illegal instruction exception"); + ("-enable-svinval", + Arg.Set P.config_enable_svinval, + " enable Svinval extension"); ("-enable-zcb", Arg.Set P.config_enable_zcb, " enable Zcb (simple code size) extension"); -- cgit v1.1