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AgeCommit message (Expand)AuthorFilesLines
2018-11-08RISC-V: fix a typo-induced bug in updating the PTE.Prashanth Mundkur1-1/+1
2018-07-20Add assorted comments, consistency fixes and cleanup.Prashanth Mundkur1-18/+19
2018-07-10Turn off some riscv debug tracing.Prashanth Mundkur1-3/+8
2018-07-10RISCV load-acquire in Lem (-> rmem)Jon French1-1/+1
2018-07-07Add some tracing to riscv address translation.Prashanth Mundkur1-11/+39
2018-06-22Make riscv pte dirty-bit update handling configurable via a platform cli option.Prashanth Mundkur1-4/+2
2018-06-07Update physical memory and address translation for MMIO.Prashanth Mundkur1-1/+2
2018-05-11Work around Lem generation problem in RISC-VThomas Bauereiss1-12/+12
2018-05-07Fix another mask computation bug.Prashanth Mundkur1-1/+2
2018-05-07Adjust default pte update setting to match spike's default.Prashanth Mundkur1-1/+1
2018-05-04Fix two bugs in the page-table walker, and add some comments.Prashanth Mundkur1-15/+32
2018-05-02Finish up Sv39 address translation.Prashanth Mundkur1-2/+200
2018-05-02Fix typo in riscv model.Prashanth Mundkur1-1/+1
2018-04-26Add riscv SV39 page-table walk.Prashanth Mundkur1-3/+54
2018-04-23Add riscv PTE definitions and access control checks.Prashanth Mundkur1-0/+106
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