| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-11-29 | RISC-V: factor the execution trace. | Prashanth Mundkur | 1 | -1/+1 |
| 2018-11-12 | Add RVFI DII version of the RISC-V simulator for TestRIG | Brian Campbell | 1 | -0/+12 |
| 2018-10-23 | RISC-V: Add a platform knob to control mtval contents on illegal instruction ... | Prashanth Mundkur | 1 | -2/+5 |
| 2018-10-05 | RISC-V: encode/decode and assembly mappings for compressed instructions | Jon French | 1 | -0/+11 |
| 2018-07-27 | Add some missing rv64i instructions, discovered when annotating the riscv isa... | Prashanth Mundkur | 1 | -0/+2 |
| 2018-07-20 | Add assorted comments, consistency fixes and cleanup. | Prashanth Mundkur | 1 | -118/+142 |
| 2018-07-07 | Add some tracing to riscv address translation. | Prashanth Mundkur | 1 | -1/+1 |
| 2018-07-05 | restore missing RISC-V fence types in sail2; ignore io bits in fences more cl... | Jon French | 1 | -1/+1 |
| 2018-06-21 | changes to riscv model to support rmem | Jon French | 1 | -4/+105 |
| 2018-06-11 | Merge branch 'sail2' into mappings | Jon French | 1 | -24/+29 |
| 2018-06-11 | change double-caret for string-append-pattern to single caret, since that wou... | Jon French | 1 | -1/+1 |
| 2018-06-08 | Add mem and mmio access tracing. | Prashanth Mundkur | 1 | -24/+29 |
| 2018-05-23 | riscv decode now uses mapping-decode and passes tests | Jon French | 1 | -3/+3 |
| 2018-05-21 | further RISCV mapping: all extant non-compressed instructions done | Jon French | 1 | -1/+7 |
| 2018-05-18 | more riscv mapping | Jon French | 1 | -0/+19 |
| 2018-05-15 | Merge branch 'sail2' into mappings | Jon French | 1 | -1/+0 |
| 2018-05-15 | Fix the ebreak instruction to trap, and remove the now obsolete internal exce... | Prashanth Mundkur | 1 | -1/+0 |
| 2018-05-10 | move common mappings to riscv_types.sail | Jon French | 1 | -0/+43 |
| 2018-05-09 | Remove unused definitions. | Prashanth Mundkur | 1 | -1/+0 |
| 2018-05-03 | Fix a bug in privilege transition, add better transition logging. | Prashanth Mundkur | 1 | -0/+22 |
| 2018-05-03 | Implement fetch to properly handle RVC and address translation, and add a ste... | Prashanth Mundkur | 1 | -0/+3 |
| 2018-04-20 | Add a riscv instruction printer for the execution log. | Prashanth Mundkur | 1 | -1/+42 |
| 2018-04-18 | Use the generated num_of_E function for enum E instead of defining one by hand. | Prashanth Mundkur | 1 | -22/+0 |
| 2018-04-17 | Add platform initialization for the new bits of machine state. | Prashanth Mundkur | 1 | -0/+7 |
| 2018-04-17 | Define exception handler delegation. | Prashanth Mundkur | 1 | -0/+22 |
| 2018-04-16 | Add the satp legalizer. | Prashanth Mundkur | 1 | -0/+9 |
| 2018-04-13 | Add some checks of current state, and use for the xepc write legalizer. | Prashanth Mundkur | 1 | -0/+9 |
| 2018-04-13 | Move riscv memory definitions into a separate file. | Prashanth Mundkur | 1 | -106/+0 |
| 2018-04-13 | Fix access checks to riscv CSRs. | Prashanth Mundkur | 1 | -1/+7 |
| 2018-04-11 | More structured riscv trap vector handling. | Prashanth Mundkur | 1 | -1/+32 |
| 2018-04-09 | Update riscv to use the new system definitions, remove duplicates. | Prashanth Mundkur | 1 | -0/+31 |
| 2018-04-09 | Add some riscv arch definitions: privilege levels, exceptions, interrupts, ex... | Prashanth Mundkur | 1 | -5/+98 |
| 2018-04-09 | Slightly re-org defs to move related things closer together. | Prashanth Mundkur | 1 | -16/+24 |
| 2018-04-09 | Better separate riscv-independent and riscv-specific parts between prelude an... | Prashanth Mundkur | 1 | -10/+7 |
| 2018-03-07 | Make union types consistent in the AST | Alasdair Armstrong | 1 | -2/+2 |
| 2018-02-06 | Fixed some bugs in the RVC spec; the rvc test now passes. | Prashanth Mundkur | 1 | -1/+1 |
| 2018-02-06 | some prettyfying of riscv: replace regbits/bits(64) with xlenbits and use ove... | Robert Norton | 1 | -78/+41 |
| 2018-02-05 | riscv: slightly prettier register trace output | Robert Norton | 1 | -2/+1 |
| 2018-02-02 | Add some more compressed instruction specs, and slightly clean up previous ones. | Prashanth Mundkur | 1 | -1/+8 |
| 2018-02-01 | Add c.addi4spn. | Prashanth Mundkur | 1 | -0/+2 |
| 2018-01-29 | riscv: fix warnings about incomplete patterns. Add a check target in Makefile... | Robert Norton | 1 | -0/+6 |
| 2018-01-29 | riscv: add tracing of register writes. | Robert Norton | 1 | -2/+6 |
| 2018-01-25 | work in progress riscv CSR implementation. | Robert Norton | 1 | -1/+1 |
| 2018-01-24 | Fixed riscv ocaml compilation | Alasdair Armstrong | 1 | -6/+6 |
| 2018-01-22 | Update Lem shallow embedding to Sail2 | Thomas Bauereiss | 1 | -22/+19 |
| 2018-01-22 | Update and fix test suite | Alasdair Armstrong | 1 | -24/+47 |
| 2018-01-19 | Added C-style single line comments | Alasdair Armstrong | 1 | -6/+4 |
| 2018-01-19 | Got riscv spec to typecheck with sail2 | Alasdair Armstrong | 1 | -10/+8 |
| 2018-01-19 | riscv sail2 wip. | Robert Norton | 1 | -4/+8 |
| 2018-01-19 | Start translating riscv to sail2 | Alasdair Armstrong | 1 | -0/+174 |
