sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-11-30	Make rvfi-dii sessions end cleanly	Brian Campbell	1	-4/+12
2018-11-30	Fix memory leaks in rvfi-dii mode	Brian Campbell	1	-0/+2
2018-11-29	RISC-V: more tidying up of the Spike interface.	Prashanth Mundkur	1	-11/+10
2018-11-29	RISC-V: factor the execution trace.	Prashanth Mundkur	1	-0/+5
2018-11-29	RISC-V: minor cleanup of the spike interface.	Prashanth Mundkur	1	-40/+45
2018-11-29	Merge branch 'rvfi-dii' into sail2	Brian Campbell	1	-2/+155
2018-11-27	Fix memory leak in string_of_bits	Alasdair Armstrong	1	-0/+1
2018-11-21	RISC-V: allow platform ram size to be configurable.	Prashanth Mundkur	1	-5/+21
2018-11-14	Add option to turn off RISC-V compressed instruction support	Brian Campbell	1	-2/+10
2018-11-14	Fix memory map in RVFI-DII mode	Brian Campbell	1	-5/+9
2018-11-12	rvfi_dii: take port number with option	Brian Campbell	1	-4/+6
2018-11-12	Add RVFI DII version of the RISC-V simulator for TestRIG	Brian Campbell	1	-2/+141
2018-11-07	RISC-V: add some consistency checks when run with spike.	Prashanth Mundkur	1	-2/+17
2018-10-23	RISC-V: Allow the C platform to get the DTB from a file, so that OS boot is p...	Prashanth Mundkur	1	-22/+100
2018-10-23	RISC-V: add cli option to dump the platform device-tree.	Prashanth Mundkur	1	-7/+35
2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ...	Prashanth Mundkur	1	-5/+6
2018-10-23	RISC-V: various fixes	Prashanth Mundkur	1	-0/+1
2018-10-23	RISC-V: adjust main loop for the non-spike case.	Prashanth Mundkur	1	-10/+11
2018-10-23	RISC-V: implement terminal output for C platform.	Prashanth Mundkur	1	-5/+34
2018-10-23	RISC-V: tick the clock in the C platform.	Prashanth Mundkur	1	-2/+16
2018-10-23	RISC-V: Add device tree blob into rom, currently only when linked against spike.	Prashanth Mundkur	1	-3/+17
2018-10-23	RISC-V: add default reset vector.	Prashanth Mundkur	1	-4/+35
2018-10-23	RISC-V: set htif tohost port address using ELF symbol.	Prashanth Mundkur	1	-0/+6
2018-10-23	RISC-V: Allow Spike linkage to be conditionally enabled.	Prashanth Mundkur	1	-4/+21
2018-10-23	RISC-V: flush logs at each step.	Prashanth Mundkur	1	-0/+10
2018-10-23	RISC-V: Flesh out more of the tandem checks in the C platform simulator.	Prashanth Mundkur	1	-3/+107
2018-10-23	RISC-V: An initial C Sail model linked against Spike for testing.	Prashanth Mundkur	1	-0/+152