sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-12-20	Address the fixme for rmem integration of LR as suggested by Shaked.	Prashanth Mundkur	1	-0/+2
2018-11-29	RISC-V: factor the execution trace.	Prashanth Mundkur	1	-8/+35
2018-11-21	RISC-V: allow platform ram size to be configurable.	Prashanth Mundkur	1	-2/+2
2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ...	Prashanth Mundkur	1	-0/+2
2018-07-07	Cancel riscv reservation before i/o scheduling, tweak reservation tracing.	Prashanth Mundkur	1	-1/+1
2018-07-07	An initial fix to riscv lr/sc, needs a review.	Prashanth Mundkur	1	-0/+17
2018-06-25	Add a riscv platform parameter to control trapping to M-mode on misaligned ac...	Prashanth Mundkur	1	-0/+3
2018-06-22	Make riscv pte dirty-bit update handling configurable via a platform cli option.	Prashanth Mundkur	1	-0/+5
2018-06-22	Add cli options to riscv simulator to dump platform device-tree info.	Prashanth Mundkur	1	-0/+7
2018-06-11	Use riscv platform insns_per_tick to tick the clock.	Prashanth Mundkur	1	-0/+2
2018-06-11	Put the riscv model's output on stderr, leaving stdout for the platform termi...	Prashanth Mundkur	1	-2/+2
2018-06-08	Make the simulation loop use the platform interface to detect exits via htif.	Prashanth Mundkur	1	-0/+4
2018-06-07	More definitions for the physical memory map.	Prashanth Mundkur	1	-0/+6
2018-06-07	Add terminal output to riscv platform, with incomplete handling of input.	Prashanth Mundkur	1	-0/+9
2018-05-21	Add in the platform files and update the ocaml build. Disable the isabelle b...	Prashanth Mundkur	1	-0/+90