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2019-03-06Fix U-mode checks in check_Counteren()Xi Wang1-3/+3
Access to a counter in U-mode should cause an illegal instruction exception if the corresponding bit is clear in either mcounteren or scounteren. The current code checks scounteren only.
2019-03-05Fix a typo.Prashanth Mundkur1-1/+1
2019-03-05Correct capitalisation of Sv39/48 in pattern matchesBrian Campbell2-3/+3
2019-03-04Minor edit for consistency.Prashanth Mundkur1-5/+5
2019-03-04Fix missed RV32 check for shamt in sll/srl.Prashanth Mundkur1-5/+13
2019-03-04Enable pmpaddr0.Prashanth Mundkur1-2/+1
2019-02-27Initial attempt to separate generated files by ARCH. Some ↵Prashanth Mundkur3-1/+3
backends/rvfi/rmem still to be tested.
2019-02-26Merge branch 'master' into rv32Prashanth Mundkur1-0/+8
2019-02-26Initial cleanup of the prelude, using standard prelude instead when possible.Prashanth Mundkur3-244/+48
2019-02-22Fix address translation bug in ordering of width-extension and shift in pte. ↵Prashanth Mundkur4-10/+10
This showed up in RV32, but not in RV64, presumably because the highest address bits are not typically exercised typical physical memory maps.
2019-02-21Fix the ocaml platform to respect the architectural width.Prashanth Mundkur1-8/+17
2019-02-20Some changes for arch-specific initialization.Prashanth Mundkur1-2/+1
2019-02-20Add ELF architecture checks to the loaders in the OCaml and C emulators.Prashanth Mundkur3-2/+5
2019-02-19Use sizeof xlen instead of the value definitions of xlen.Prashanth Mundkur14-143/+135
2019-02-19Adjust Makefile to use an ARCH argument. Undo xlen guards in ↵Prashanth Mundkur3-3/+13
riscv_analysis, instead conditionally include it in sources, depending on the ARCH.
2019-02-15Fix riscv_analysis to use xlen.Prashanth Mundkur1-3/+3
2019-02-15More RV32 fixes.Prashanth Mundkur3-10/+8
2019-02-15Define counter CSRs, and guard accesses from RV32.Prashanth Mundkur2-87/+113
2019-02-15Add xlen guards on double-word operations to make them RV64-only.Prashanth Mundkur3-42/+43
2019-02-14Handle shamt being 5 bits in RV32 instead of 6; also fix a missed case of ↵Prashanth Mundkur1-8/+14
disabling the TLB in sfence.vma.
2019-02-14Fix typo in earlier commit.Prashanth Mundkur1-1/+1
2019-02-13Add Sv32 and Sv48 by essentially copying Sv39.Prashanth Mundkur7-3/+277
Being first-order prevents straight-forward abstraction over the PTE operations, but perhaps there is another way to generalize and unify.
2019-02-13Remove the use of the TLB until it is more generic across the various ↵Prashanth Mundkur1-56/+24
architectures and modes.
2019-02-13Pull out the Sv39 and its TLB into separate files.Prashanth Mundkur4-215/+225
2019-02-13Make more address translation types reusable.Prashanth Mundkur2-35/+24
2019-02-13Fix a bug introduced in changing sxl/uxl handling; fix comment.Prashanth Mundkur1-2/+2
2019-02-13Attempt to reuse types for Sv39 and Sv48 to the extent possible for ↵Prashanth Mundkur2-70/+96
simplicity. This might need revisiting for Sv59 and Sv64.
2019-02-12Start extracting bits of vmem that should be common to RV32, and add some ↵Prashanth Mundkur5-238/+332
definitions for Sv32 and Sv48.
2019-02-12Compatability fixes from Sail 0.7.1 to Sail 0.8Alasdair Armstrong1-0/+8
Two small compatability fixes: Small change to the prelude to make sure we are forwards compatable with the next release of Sail, which has slightly different syntax for implicit arguments. Due to changes in the monad embedding in the latest git version of Sail, we disable generating Lem by default when we detect we are on that version. It's a small one line fix to correct, but we want to keep the Lem definitions in this repository compatible with the opam release 0.7.1 for now.
2019-02-11Handle 32-bit accesses to the mmio regions and device registers of the clint ↵Prashanth Mundkur1-23/+68
and htif.
2019-02-11Fix xlen variable name.Prashanth Mundkur12-113/+113
2019-02-11Handle SXL/UXL not being present in mstatus in RV32 by using explicit ↵Prashanth Mundkur4-12/+57
getters/setters.
2019-02-11Fix 64-bit constants.Prashanth Mundkur1-3/+3
2019-02-11Fix mvendorid width.Prashanth Mundkur2-2/+2
2019-02-11More refactoring for RV32Prashanth Mundkur6-87/+91
- split out memory access definitions in prelude that depend on xlen - make riscv_xlen now part of the prelude set, so that riscv_duopod can use the definition - update xlen use in riscv_duopod so that it can now support rv32
2019-02-11Parameterize CSR fields for xlen, and fix definitions for CSRs which are ↵Prashanth Mundkur2-15/+15
always 64-bit for RV32/RV64.
2019-02-08Add xlen guards on encdec and assembly guards, and encdec for c.jal.Prashanth Mundkur3-27/+111
2019-02-08Start parameterizing definitions by xlen, which is currently still 64.Prashanth Mundkur8-29/+34
2019-02-08Change implicits on monad branchAlasdair Armstrong1-4/+4
2019-02-08Adapt to changes in Sail's Lem shallow embeddingThomas Bauereiss3-52/+36
In the monads branch of Sail, writing a memory value now requires address and write_kind (instead of relying on parameters announced earlier).
2019-02-08Split out the mapping prelude into its own file.Prashanth Mundkur2-690/+690
2019-02-06Fix register rs2 read in AMO.Prashanth Mundkur1-1/+1
2019-01-30Comment out asserts.Prashanth Mundkur1-5/+5
2019-01-30Add some missed checks for 'N' to delegation logic.Prashanth Mundkur1-7/+13
2019-01-29Update docs, and fix file names.Prashanth Mundkur3-0/+0
2019-01-29Add more of the 'N' standard extension.Prashanth Mundkur5-59/+147
- add URET and handle its trap - simplify interrupt delegation for 'N', and also make it handle M-only operation
2019-01-29Add CSRs for the 'N' extension arch state and expose to CSR read/write.Prashanth Mundkur5-186/+322
2019-01-29Factor the _sys functionality into separate files for architectural state ↵Prashanth Mundkur2-527/+566
and processing logic. Also check misa.N() when lifting and lowering {ms}i{pe}, and misa.S() when accessing S-mode CSRs.
2019-01-28Comment on handling mstatus.FS, and update to match Spike.Prashanth Mundkur1-4/+6
2019-01-25Tweaks to reservation handling.Prashanth Mundkur1-1/+1
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