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path: root/model/riscv_vmem_sv48.sail
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2019-06-24Add PMP checks to physical memory accesses.Prashanth Mundkur1-1/+1
- unify AccessType and ReadType since they were essentially redundant, making it easier to implement PMP checks for ReadWrite/atomic accesses. - add command line options to enable PMP in the platform - also fix the matching for the case when all entries are off
2019-06-24Narrow the external interface to riscv_mem to mem_{read,write,write_ea}.Prashanth Mundkur1-2/+2
2019-06-24Starting cleaning up physical memory bits for pmp integration.Prashanth Mundkur1-3/+2
. convert duopod to directly use Sail lib/regfp functions . put lib/regfp wrappers in prelude, and avoid calling them directly in riscv_mem . remove mmio assumption in page-table walks, making read/write calls symmetric . prune obsolete functions from prelude_mem
2019-04-24Add extended model from cheri-merge.Prashanth Mundkur1-2/+2
2019-03-12Fix missed tlb updates.Prashanth Mundkur1-2/+2
2019-03-11Add tlbs for Sv32 and Sv48, and some fixes to sfence.vma.Prashanth Mundkur1-0/+38
- handle sfence.vma in machine-mode - flush both tlb39 and tlb48 in 64-bit mode
2019-02-22Fix address translation bug in ordering of width-extension and shift in pte. ↵Prashanth Mundkur1-1/+1
This showed up in RV32, but not in RV64, presumably because the highest address bits are not typically exercised typical physical memory maps.
2019-02-13Add Sv32 and Sv48 by essentially copying Sv39.Prashanth Mundkur1-0/+106
Being first-order prevents straight-forward abstraction over the PTE operations, but perhaps there is another way to generalize and unify.