sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2020-06-30	Split ext_ptw into pieces and add documentation	Nathaniel Wesley Filardo	1	-2/+2
	It was somewhat annoying that CHERI would have had to track both successful and erroneous occurrences within the same type. Break the failures out to their own form and, while here, attempt to write down my understanding of the extension's information flow through vmem.
2020-06-20	Allow extensions to override page fault causes	Jessica Clarke	1	-1/+1
	Otherwise there's no use for PTW_Ext_Error. This is required for sail-cheri-riscv to be able to make use of its own page table exceptions. The alternative to this is to pass the ext_ptw to translationException, but given PTW_Ext_Error exists it seems this was the intended way, and aligns with how access faults vs page faults are distinguished.
2019-11-26	Tweak base case of PTW functions	Thomas Bauereiss	1	-4/+4
	Make termination of the page table walk functions provable unconditionally in Isabelle by catching the case when "level" becomes negative. On the Sail level, this case cannot occur, because "level" has type "nat", but we currently don't automatically carry over the non-negativity constraint of the Sail type "nat" into Isabelle.
2019-10-09	Read/write memory values and metadata together atomically	Thomas Bauereiss	1	-2/+2
	For Lem, bypass the Sail implementation of {read,write}_ram and map to atomic primitives directly. We might want to make these functions primitive for other backends as well.
2019-09-04	Merge remote-tracking branch 'origin/master' into vmem_ext.vmem_ext	Robert Norton	1	-1/+1

2019-08-19	RISC-V spec, without implicit casts	Alasdair Armstrong	1	-1/+1

2019-08-09	Allow accumulation of information during page-table-walk for extensions.	Prashanth Mundkur	1	-25/+23

2019-07-22	Make a custom exception code available for extensions, and remove the ↵	Prashanth Mundkur	1	-27/+32
	E_CHERI code. Enable extensions for PTE checks and PTW errors, and propagate those into exception codes.
2019-07-16	Use reserved bits in PTEs for vmem extensions on RV64, as allowed by the ↵	Prashanth Mundkur	1	-5/+7
	spec. This is not possible for RV32, so pass zeros there.
2019-07-15	Allow extensions to types of memory access, and factor out PTE and PTW ↵	Prashanth Mundkur	1	-2/+2
	definitions.
2019-06-24	Add PMP checks to physical memory accesses.	Prashanth Mundkur	1	-1/+1
	- unify AccessType and ReadType since they were essentially redundant, making it easier to implement PMP checks for ReadWrite/atomic accesses. - add command line options to enable PMP in the platform - also fix the matching for the case when all entries are off
2019-06-24	Narrow the external interface to riscv_mem to mem_{read,write,write_ea}.	Prashanth Mundkur	1	-2/+2

2019-06-24	Starting cleaning up physical memory bits for pmp integration.	Prashanth Mundkur	1	-3/+2
	. convert duopod to directly use Sail lib/regfp functions . put lib/regfp wrappers in prelude, and avoid calling them directly in riscv_mem . remove mmio assumption in page-table walks, making read/write calls symmetric . prune obsolete functions from prelude_mem
2019-04-24	Add extended model from cheri-merge.	Prashanth Mundkur	1	-2/+2

2019-03-12	Fix missed tlb updates.	Prashanth Mundkur	1	-2/+2

2019-03-11	Add tlbs for Sv32 and Sv48, and some fixes to sfence.vma.	Prashanth Mundkur	1	-0/+38
	- handle sfence.vma in machine-mode - flush both tlb39 and tlb48 in 64-bit mode
2019-02-22	Fix address translation bug in ordering of width-extension and shift in pte. ↵	Prashanth Mundkur	1	-1/+1
	This showed up in RV32, but not in RV64, presumably because the highest address bits are not typically exercised typical physical memory maps.
2019-02-13	Add Sv32 and Sv48 by essentially copying Sv39.	Prashanth Mundkur	1	-0/+106
	Being first-order prevents straight-forward abstraction over the PTE operations, but perhaps there is another way to generalize and unify.