aboutsummaryrefslogtreecommitdiff
path: root/model/riscv_vmem_rv32.sail
AgeCommit message (Collapse)AuthorFilesLines
2023-09-12Remove effectsTim Hutt1-4/+4
Since Sail 0.15 (released Nov 2022), effects have had no effect. They now generate a deprecation warning. This commit removes all the effect annotations from the model, thus fixing the compiler warnings.
2023-05-29apply_headers: regenerate copyright headersupdate-copyright-headersPhilipp Tomsich1-1/+3
2023-03-06Add wildcard cases to matches to suppress Sail warnings. (#197)Robert Norton1-2/+2
Sail tries to check for pattern match completeness and issues warnings but this often gives false positives: see discussion at https://github.com/rems-project/sail/issues/191 . To suppress these we add a wildcard case that raises an internal error. There is effectively no behaviour change as these would previously have resulted in a match error at runtime and they should be unreachable anyway. At the same time we change the DOUBLE case in memory access paths to allow for xlen > 64. Following discussion on the PR I also changed internal_error to take a file and line number as an argument to aid with debugging. Fixes: https://github.com/riscv/sail-riscv/issues/194
2021-07-29Use headache to apply copyright header at request of Peter Sewell.Robert Norton1-0/+68
2021-06-29vmem_rvNN: allow shimming underneath effectivePrivilegeNathaniel Wesley Filardo1-3/+6
It's possible that we might want to do page table walks at Privilege levels other than the default value (e.g., under the explicit direction of the instruction stream). Split translateAddr into a thin wrapper of the same name and a new translateAddr_priv that takes the Privilege as an argument.
2020-04-21Fix mstatus.MPRV fetches (#48)Scott Johnson1-4/+1
* Add {} so I can add a new variable here next * Create new variable which I will soon reuse * Plumb in the access type to effectivePrivilege So I can use it to fix #47 next. * Instruction fetches should not be affected by mstatus.MPRV Fixes #47. * Remove now-redundant privilege calculation
2019-11-25Fix RV32 Lem buildThomas Bauereiss1-1/+1
2019-09-04Merge remote-tracking branch 'origin/master' into vmem_ext.vmem_extRobert Norton1-3/+3
2019-08-20Whitespace fixes to nuke tabs.no_castsPrashanth Mundkur1-1/+1
2019-08-19RISC-V spec, without implicit castsAlasdair Armstrong1-3/+3
2019-08-09Allow accumulation of information during page-table-walk for extensions.Prashanth Mundkur1-4/+7
2019-07-16Use reserved bits in PTEs for vmem extensions on RV64, as allowed by the ↵Prashanth Mundkur1-3/+3
spec. This is not possible for RV32, so pass zeros there.
2019-06-24Add PMP checks to physical memory accesses.Prashanth Mundkur1-5/+5
- unify AccessType and ReadType since they were essentially redundant, making it easier to implement PMP checks for ReadWrite/atomic accesses. - add command line options to enable PMP in the platform - also fix the matching for the case when all entries are off
2019-06-19Factor out mstatus.mprv checks for effective privilege for reuse in PMP.Prashanth Mundkur1-3/+1
2019-04-24Add extended model from cheri-merge.Prashanth Mundkur1-1/+1
2019-03-11Add tlbs for Sv32 and Sv48, and some fixes to sfence.vma.Prashanth Mundkur1-4/+9
- handle sfence.vma in machine-mode - flush both tlb39 and tlb48 in 64-bit mode
2019-03-11Fixes for Sv39 TLB.Prashanth Mundkur1-0/+9
- fix and simplify model initialization, to enable generic TLB initialization - re-enable sfence.vma
2019-03-05Fix a typo.Prashanth Mundkur1-1/+1
2019-03-05Correct capitalisation of Sv39/48 in pattern matchesBrian Campbell1-1/+1
2019-02-13Add Sv32 and Sv48 by essentially copying Sv39.Prashanth Mundkur1-0/+52
Being first-order prevents straight-forward abstraction over the PTE operations, but perhaps there is another way to generalize and unify.