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path: root/model/riscv_sys_control.sail
AgeCommit message (Expand)AuthorFilesLines
2019-08-19RISC-V spec, without implicit castsAlasdair Armstrong1-45/+45
2019-07-09Add some missed logging guards.Prashanth Mundkur1-16/+28
2019-06-28Avoid implicit casts to stringAlasdair1-6/+8
2019-06-25Add PMP regs to the is-defined predicate.Prashanth Mundkur1-1/+20
2019-06-24Add PMP checks to physical memory accesses.Prashanth Mundkur1-0/+2
2019-05-24Make xret hooks differentiate between just reading xret target values and get...Prashanth Mundkur1-3/+3
2019-05-14Improve the interface to access CSRs in extensions.Prashanth Mundkur1-2/+2
2019-05-06Factor out sync_exception to fix dependencies in cheri, and similarly split o...Prashanth Mundkur1-7/+1
2019-05-03Enable some asserts.Prashanth Mundkur1-4/+4
2019-05-03Fix inconsistency in accessing PC/nextPC, which also clarifies which handlers...Prashanth Mundkur1-7/+7
2019-04-24Add extended model from cheri-merge.Prashanth Mundkur1-31/+30
2019-04-12Merge branch 'master' into rmem_interpreterrmem_interpreterJon French1-6/+7
2019-03-29Generalize the previous commit to handle hardwired misa.c.Prashanth Mundkur1-6/+7
2019-03-14Merge branch 'master' into rmem_interpreterJon French1-11/+25
2019-03-12riscv_platform.sail: use externs for platform values even in interpreterJon French1-6/+4
2019-03-06Fix U-mode checks in check_Counteren()Xi Wang1-3/+3
2019-03-04Enable pmpaddr0.Prashanth Mundkur1-2/+1
2019-02-20Some changes for arch-specific initialization.Prashanth Mundkur1-2/+1
2019-02-19Use sizeof xlen instead of the value definitions of xlen.Prashanth Mundkur1-5/+5
2019-02-15Define counter CSRs, and guard accesses from RV32.Prashanth Mundkur1-2/+18
2019-02-11Handle SXL/UXL not being present in mstatus in RV32 by using explicit getters...Prashanth Mundkur1-2/+2
2019-01-30Comment out asserts.Prashanth Mundkur1-5/+5
2019-01-30Add some missed checks for 'N' to delegation logic.Prashanth Mundkur1-7/+13
2019-01-29Update docs, and fix file names.Prashanth Mundkur1-0/+444
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