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2021-06-25Add a github action to check simulators build.Robert Norton1-0/+24
2021-06-25Merge pull request #88 from jrtc27/pkg-configRobert Norton1-6/+7
2021-06-25Update MakefileRobert Norton1-1/+1
2021-06-25Merge pull request #76 from arichardson/rvfi-newRobert Norton9-91/+442
2021-06-21Merge pull request #85 from ybc-alkaid/pmpRobert Norton1-1/+1
2021-06-18Merge pull request #89 from rems-project/amo_fixRobert Norton1-20/+47
2021-05-27Fix Error_not_implemented exception on lr.rl or sc.aq.Robert Norton1-12/+12
2021-05-21Extend LR / SC / AMO execute for unused widths.Robert Norton1-9/+23
2021-05-21Fix internal error caused by invalid LR / SC / AMO widths.Robert Norton1-6/+19
2021-05-04c_emulator: Fix incorrect format stringJessica Clarke1-1/+1
2021-05-04Makefile: Generalise build to fix Arm-based MacsJessica Clarke1-6/+7
2021-03-19pmp: pmp address match misses some corner casesBicheng Yang1-1/+1
2021-03-16Check for overly large RVFI packetsAlex Richardson1-0/+5
2021-03-16Also set the IXL field in the RVFI traceAlex Richardson1-0/+1
2021-03-16Reduce debug spam in RVFI trace outputAlex Richardson1-1/+0
2021-03-16Fix sending version2 trace optional dataAlex Richardson3-16/+30
2021-03-16Update Makefile for the new trace formatAlex Richardson1-1/+15
2021-03-16Report the current privilege level via RVFIAlex Richardson1-0/+1
2021-03-16Improvements to the version 2 RVFI trace formatAlex Richardson3-71/+87
2021-03-16Fix missing rvfi_halt field when converting v2 to v1 RVFI trace formatAlex Richardson1-0/+1
2021-03-16Add a -v rvfi flag to add RVFI debug loggingAlex Richardson3-10/+49
2021-03-16Add missing newlines to error message and print the listen portAlex Richardson1-8/+13
2021-03-16Ensure that the RVFI socket is open in blocking modeAlex Richardson1-0/+14
2021-03-16Initial implementation of new RVFI_DII socket formatAlex Richardson8-65/+307
2021-02-11Remove unused register files.Prashanth Mundkur2-4/+0
2021-02-11Fix up some missed and wrong cli options in C emulator.Prashanth Mundkur1-2/+3
2021-02-11Make N extension configurable.Prashanth Mundkur14-1/+37
2021-02-11Merge pull request #81 from scottj97/sstatus-fixPrashanth Mundkur1-1/+1
2021-02-11Merge pull request #82 from scottj97/mret-minstretPrashanth Mundkur1-8/+12
2021-02-02Reformat excessively-long linesScott Johnson1-2/+8
2021-01-27MRET and SRET should increment minstret when successfulScott Johnson1-8/+6
2021-01-26Prevent CSRW to sstatus from modifying uie & upie if N-ext not presentScott Johnson1-1/+1
2020-11-30Merge pull request #78 from arichardson/mstatus-ignore-undefined-bitsPrashanth Mundkur1-1/+6
2020-11-30Ignore undefined bits in mstatus on writeAlex Richardson1-1/+6
2020-11-19Merge pull request #77 from scottj97/fix-ssipPrashanth Mundkur1-1/+1
2020-11-17Bug fix: when writing CSR sip, ignore attempt to change undelegated SSIPScott Johnson1-1/+1
2020-11-10Merge pull request #74 from PeterRugg/dii-fetch-ptePrashanth Mundkur1-16/+23
2020-11-09Perform PTE checks on DII fetch (with jrtc27)Peter Rugg1-16/+23
2020-10-15Store PC in mtval on EBREAK to match a spec update.Prashanth Mundkur1-1/+1
2020-10-15Handle non-atomic but aligned writes to the 64-bit HTIF i/o port on RV32.Prashanth Mundkur1-28/+65
2020-09-22Handle empty predecessor or successor RW sets in FENCE as no-ops, as IO concu...Prashanth Mundkur1-2/+4
2020-09-05Update status and docs for hints.Prashanth Mundkur2-4/+2
2020-09-04Handle hints explicitly in order to not trap on them.Prashanth Mundkur2-1/+159
2020-09-03Add the mstatush CSR for RV32, and hardwire the MBE and SBE fields to 0.Prashanth Mundkur3-0/+26
2020-08-27Merge pull request #66 from scottj97/mcountinhibitPrashanth Mundkur3-1/+4
2020-08-25Implement mcountinhibit IR bit to squash minstret incrementScott Johnson1-1/+2
2020-08-25Allow CSR read/write to mcountinhibitScott Johnson1-0/+1
2020-08-25Add missing disassembler mapping for mcountinhibit CSRScott Johnson1-0/+1
2020-08-20Fix conditions CSR definedness. Fixes #65.Prashanth Mundkur1-11/+11
2020-08-04Add a line pointing to the instructions for latex inclusion in the prose spec...Prashanth Mundkur1-0/+1
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