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2023-06-16missed a filehpm_events_billmcspaddenWilliam McSpaddden1-1/+0
2023-06-16intermediate commit for support of hpm_events.William McSpaddden5-8/+158
2023-06-12fixed instruction count. test now appears to run correctlyWilliam McSpaddden3-1/+3
2023-06-12more re-factoring. code compilesWilliam McSpaddden4-844/+35
2023-06-12re-structuring HPM event code. re-writing C code in Sail. code compiles. ↵William McSpaddden8-0/+559
intermediate checkin.
2023-06-12re-structuring HPM event code. re-writing C code in Sail. code compiles. ↵William McSpaddden6-8/+1304
intermediate checkin.
2023-04-29added hpm CSRs. compiles. but no significant functionality at this pointWilliam McSpaddden4-14/+541
2023-04-04fixed an issue with the -g switch which requires an argument. missing colon ↵William McSpaddden1-1/+1
in string arg to getopt_long()
2023-03-14Add a new recipe to run the Sail tests manually via GH Actions (#229)billmcspadden-riscvRafael Sene1-1/+1
Signed-off-by: Rafael Sene <rafael@riscv.org>
2023-03-14Use not() instead of ~() for boolean negation (#210)Alexander Richardson18-51/+53
This may be more readable and also matches the sail-cheri-riscv model. For now this keeps ~ overloaded to accept bool, but in the future we may want to consider removing it (which is what I did to find all uses modified in this patch)
2023-03-14Move ILLEGAL/C_ILLEGAL ast declaration to riscv_insts_begin.sail (#223)Alexander Richardson2-4/+9
This is useful for the sail-cheri-riscv model, where we would like to reuse C_ILLEGAL, but can't right now since it is current defined too late. It is needed for https://github.com/CTSRD-CHERI/sail-cheri-riscv/pull/69
2023-03-07Bump CI to Ubuntu 22.04 (#228)Jessica Clarke1-3/+1
Ubuntu 18.04 is being sunset.
2023-03-06Add wildcard cases to matches to suppress Sail warnings. (#197)Robert Norton16-85/+127
Sail tries to check for pattern match completeness and issues warnings but this often gives false positives: see discussion at https://github.com/rems-project/sail/issues/191 . To suppress these we add a wildcard case that raises an internal error. There is effectively no behaviour change as these would previously have resulted in a match error at runtime and they should be unreachable anyway. At the same time we change the DOUBLE case in memory access paths to allow for xlen > 64. Following discussion on the PR I also changed internal_error to take a file and line number as an argument to aid with debugging. Fixes: https://github.com/riscv/sail-riscv/issues/194
2023-02-23Remove duopodBrian Campbell5-244/+1
This can now be found in the Sail repository. Includes an update to sail-riscv.install
2023-02-14Revert "added 3 new command line switches (plus functionality): ↵Jessica Clarke7-70/+1
-X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)" (#220) Reverts #219. Merged without code review and with many issues. This reverts commit 43b81eafc660ab584e1684668995957764a5e684.
2023-02-13added 3 new command line switches (plus functionality): ↵Bill McSpadden7-1/+70
-X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219) * added 3 command-line switches: -X/--enable-experimental-extensions, --enable-Smepmp, --enable-Zicond * example commit * fixed some type warnings/errors (between int/bool)
2023-01-25Increase flexibility of the decode hook (and simplify it) (#205)Alexander Richardson3-14/+11
Previously the decoding hook (`ext_post_decode_hook`) allowed models to override the decoded `ast`. However, this is not sufficient if model extension changes interpretation of fields. Additionally, the assembly printing would always print assembly for the "baseline decode" which resulted in incorrect trace output in the sail-cheri-riscv model. With the new hook models can implement ext_decode()/ext_decode_compressed() to return an `ast` and for encodings that are not adjusted fall back to the default `encdec`/`encdec_compressed`.
2023-01-20Add include required on FreeBSD.Robert Norton1-0/+1
2023-01-16Fix packw sign-extension (#185)Jan Henrik Weinstock1-1/+1
Signed-off-by: Jan Henrik Weinstock <jan@mwa.re> Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>
2023-01-16Fix xperm4 index calculation (#186)Jan Henrik Weinstock1-2/+2
Signed-off-by: Jan Henrik Weinstock <jan@mwa.re> Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>
2022-11-01riscv_step: Fix -i/--mtval-has-illegal-inst-bits option (#174)cookbook_brJessica Clarke1-0/+2
This option causes handle_illegal to pass instbits as the value to set for xtval, but instbits is never set so it ends up being 0 just as if the option was never enabled. Fix this by initialising instbits during fetch; we could make this conditional on whether the option is enabled but that seems unnecessary and introduces tighter coupling. Note that this option appears to have always been broken; when it was originally added, instbits was only written two in two cases which were both dead code and later removed in eb176111887b. Closes: #173
2022-08-24Revert "c emulator makefile tweak, as suggested by Thibaut"Alex Richardson1-1/+1
After the last commit -fcommon is no longer required. This reverts commit ffea7a39c32a210a446379aeda0eabcec4918ed6.
2022-08-24Allow building without -fcommonAlex Richardson1-2/+2
The sail C code generator will emit definions for these structs. The duplicate definition linker error were worked around by adding -fcommon in ffea7a39c32a210a446379aeda0eabcec4918ed6. This commit fixes the underlying issue by declaring the variables as `extern`.
2022-08-09Minimal updates for Coq proof assistant outputBrian Campbell2-3/+5
2022-07-13Add support for Zhinx extension (#153)Bilal Sakhawat3-155/+180
Merged after code review. Thanks everybody for helping.
2022-02-16Run ISA tests in CI (#134)Jessica Clarke5-28/+130
* test: Ignore generated XML output * run_tests: Build RVFI emulators too Can't run tests with them though as they're built for direct instruction injection (RVFI-DII) via an instruction stream over a network socket, not fetching instructions from memory, so this remains just a build test. * run_tests/run_fp_tests: Print summary and give meaningful exit code * run_tests/run_fp_tests: Include tests and failures in top-level XML entity * run_tests/run_fp_tests: Use failure not error for XML output The former is the standard tag for normal test failures, the latter is for catastrophic things like test harness errors. * Run ISA tests in CI
2022-02-03Added notes about copyright headers in code, and a reminder that (#146)Martin Berger2-0/+9
pull-requests ideally come with an explanation how the correctness of the PR was established.
2022-01-31Add initial contributing and code style guides (#131)Jessica Clarke2-0/+110
These are intended to deal with much of the low-hanging fruit; plenty of room for improvement exists.
2022-01-21Add support for Scalar Cryptography Zbkb, Zbkc and Zbkx Extensions (#135)Bilal Sakhawat8-27/+196
2022-01-19Configurable word size for test signature file output (#136)Bilal Sakhawat2-10/+24
2022-01-19Add support for Zfh extension (#129)Bilal Sakhawat21-13/+3067
2022-01-19Add support for Zmmul (#122)Bilal Sakhawat2-2/+4
2022-01-19sail-riscv.install: RegenerateJessica Clarke1-1/+1
2022-01-19Makefile: Sort files when generating sail-riscv.installJessica Clarke1-1/+1
The order used for wildcard is not deterministic and varies between systems. Sorting ensures the diffs are easy to inspect going forwards.
2022-01-19sail-riscv.install: Remove no longer present riscv_iris.sailJessica Clarke1-1/+1
Closes: #142
2021-12-05Support BitManip Zba, Zbb, Zbc and Zbs extensions (#116)Bilal Sakhawat7-0/+574
2021-11-22Implement support for Zfinx (#130)Jessica Clarke17-334/+452
NB: Smstateen support is missing in the model so enabling the Zfinx extension provides an architectural covert channel via FCSR if privileged software is not aware of Zfinx's existence. Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Co-authored-by: Ibrahim Abu Kharmeh <abukharmeh@gmail.com>
2021-11-21run_tests: Remove stray */ causing "Is a directory" spewJessica Clarke1-1/+1
2021-11-17Revert "Initial introduction of zfinx (#75)"Jessica Clarke17-397/+287
This reverts commit c5e62ea4b3d481fcd491b22b317cc319b089f05d.
2021-11-17Initial introduction of zfinx (#75)Ibrahim Abu Kharmeh17-287/+397
* Adds Zfinx enable flag * Hardwire misa.{f,d} and mstats.FS to 0 * Moving nan boxing functions to fdext_reg * Swaps register names for floating point instructions Adds new mapping to swap register names, and use it in all assembly clauses * Disable Floating point loads, stores and moves * Add X_or_F_s and X_or_F_d functions, and use them to access all registers for floating points Changes register accessed for floating point instructions and modify nan boxing functions for zfinx * Formatting Remove couple of misplaced whitespace, unnecessary parens * Fix inconsistent indentation in insts_dext file * Fix spacing in fdext_regs * Remove redundant comparasion with true/ false * Constistant tuples spacing and removes couple of unnecessary parens. * Consistent functions declaration & calls spacing and removes couple of unnecessary parens. * Consistent spacing and removes couple of unnecessary comparasion with true/false * Make spacing consistent * Remove checks from execution stage * Add checks to encdec stage
2021-11-10scalar-crypto: aesks1i clarificationsBen Marshall2-16/+20
Trying to make the behavior of aesks1i easier to understand, and more obviously correspond to the specification. - Ensure that the aes_decode_rcon function only accepts valid values, plus add comments. - Re-name operands to aesks1i rcon -> rnum to be in line with the specification - Re-structure the Sail code for clarity based on jrtc27's suggestion.
2021-11-10scalar-crypto: whitespace consistency for SHA* instructionsBen Marshall1-6/+6
Remove weird whitespace " );" -> ");" at end of expressions to be consistent with the rest of the code base. On branch scalar-crypto-tidy Changes to be committed: modified: model/riscv_insts_zkn.sail
2021-11-10scalar-crypto: Consistent whitespace for ==Ben Marshall1-10/+10
Add spaces pre/post used of "==" operator to be consistent with the rest of the code.
2021-11-05Delete riscv_iris.sailMartin Berger1-1244/+0
File is no longer needed, as per this discussion: https://github.com/riscv/sail-riscv/issues/119
2021-10-26Makefile: Remove stale commentJessica Clarke1-1/+0
2021-10-22Recent rustc requires -lm for linking against the Sail coverage library (#118)Brian Campbell1-1/+1
Fixes rems-project/sail#152
2021-10-22Support D extension on RV32 (#108)Jessica Clarke7-118/+94
* Use bool for floating point comparison result Using bits_WU (bits(32)) or bits_LU (bits(64)) makes no sense, these are just boolean values, and having fixed-width types is a pain for suporting RV32D (since RV32D would need to truncate, but RV128D would need to extend). Instead represent these as an actual bool to match what the values really are. This could be done with bits(1) but the value is logically a boolean (like the built-in integer comparison operators) not a bit vector of length one so we convert to bool and back for a cleaner interface. * Support compiling RV32F with flen == 64 The code conflated flen and xlen; deconflating them and adding suitable assertions (rather than silently retiring as a no-op that doesn't bump instret) ensures that it can be compiled for RV32 with flen set to 64. Whilst here, add the extensions and truncations that would be needed for RV128F. Note that there are already suitable guards on the decode clauses to ensure these instructions are illegal on RV32. * Support compiling RV32D This copies various bits of XLEN generality from the F code. * Support RV32D loads/stores * Correctly initialise misa.D based on flen not xlen * Makefile: Enable D extension for RV32 This now works so can be enabled. * test: Enable RV32D tests
2021-10-18scalar-crypto: Initial commit of 1.0.0-rc2 spec work. (#99)Ben Marshall16-2/+997
Merged scalar-crypto pull request #99 of 1.0.0-rc2 spec work from Ben Marshall. See https://github.com/riscv/sail-riscv/pull/99.
2021-09-09Merge pull request #103 from PeterRugg/fix-rounding-modesJessica Clarke2-177/+284
Fix crash when fcsr.frm is invalid
2021-09-09Merge pull request #105 from dylux/masterJessica Clarke1-1/+1
Fix incorrect SV48_Vaddr bitfield
generated by cgit v1.1 at 2024-09-18 05:16:54 +0000