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2020-06-16Use an output file for generated branch information in the coverage build.Prashanth Mundkur1-2/+3
2020-06-15Remove obsolete Coq axiomBrian Campbell1-2/+0
2020-06-15Update handwritten Coq support files to match current Sail.Brian Campbell2-10/+4
2020-06-15Update Coq part of the Makefile to use opam packages by defaultBrian Campbell1-5/+28
2020-06-15Release version 0.50.5Thibaut Pérami1-1/+1
2020-06-15c emulator makefile tweak, as suggested by ThibautChristopher Pulte1-1/+1
2020-06-10Enable sailcov support in c_emulator if SAILCOV is set in the environment.Prashanth Mundkur2-1/+19
2020-06-09Properly handle invalid virtual addresses in address translation.Prashanth Mundkur2-6/+28
Fixes #58.
2020-06-05Avoid relying on ext_access_type values in PMP, to be compatible with ↵Prashanth Mundkur1-8/+8
extensions.
2020-06-04- upgrade to opam 2 packageChristopher Pulte4-6/+10
- make opam package include files required for building rmem
2020-05-28Remove effects on assembly introduced in 1bb74ef9, fix effects on ↵Prashanth Mundkur4-18/+18
encdec_compressed.
2020-05-28Merge pull request #54 from scottj97/fix-mtvalPrashanth Mundkur1-18/+18
Fix mtval when store gets bad PMP
2020-05-27Fix bug: mtval (and [su]tval) should get vaddr, not paddrScott Johnson1-2/+2
2020-05-27Rename var to distinguish vaddr from paddrScott Johnson1-16/+16
2020-05-27Rename param to distinguish vaddr from paddrScott Johnson1-2/+2
2020-05-26Fix FMIN/FMAX when QNaN+SNaN (#53)Scott Johnson2-40/+33
* New functions to simplify float NaN detection * Remove unnecessary intermediate values Now that we have simpler function f_is_NaN * FMIN/FMAX should return canonical NaN if both operands are NaN Fixes #52. * Simplify logic for FMIN/FMAX Spec says "If only one operand is a NaN, the result is the non-NaN operand." So no need to distinguish SNaN from QNaN here.
2020-05-22Add compressed F,D instructions.Prashanth Mundkur4-4/+166
Fixes #51.
2020-05-22Prevent access to N-mode registers and mstatus/mip/mie bits when N-mode is ↵Prashanth Mundkur2-12/+16
disabled. Fixes #50.
2020-05-22Add a Makefile target for new Sail->C backendAlasdair2-0/+35
2020-04-28Update status doc to mention xlen handling limitations.Prashanth Mundkur1-0/+4
2020-04-27Clear mstatus.mprv on mret and sret, and hardwire it to 0 when user-mode is ↵Prashanth Mundkur2-2/+6
not supported.
2020-04-27Add the mcountinhibit register.Prashanth Mundkur3-1/+19
2020-04-27Handle writes to misa.{F,D}.Prashanth Mundkur1-3/+8
2020-04-21Fix mstatus.MPRV fetches (#48)Scott Johnson4-14/+11
* Add {} so I can add a new variable here next * Create new variable which I will soon reuse * Plumb in the access type to effectivePrivilege So I can use it to fix #47 next. * Instruction fetches should not be affected by mstatus.MPRV Fixes #47. * Remove now-redundant privilege calculation
2020-04-14Update pointers to the Sail-annotated specifications, and update model ↵Prashanth Mundkur2-5/+6
status for F/D.
2020-04-07Switch floating-point comparisons to using softfloat to avoid missed ↵Prashanth Mundkur8-55/+199
corner-cases in hand-rolled helpers.
2020-04-06Fix fcsr exception accrual for non-softfloat paths.Prashanth Mundkur3-103/+92
2020-04-02Fix a bug in the softfloat interface that caused exception flags not to get ↵Prashanth Mundkur5-17/+19
accrued into fcsr.
2020-04-01Set mtval to 0 on ebreak. Fixes #44.Prashanth Mundkur2-1/+8
2020-04-01Add a clarifying comment.Prashanth Mundkur1-1/+2
2020-04-01Add clarifying comment.Prashanth Mundkur1-1/+1
2020-04-01Merge pull request #45 from scottj97/pmpcfgPrashanth Mundkur2-9/+9
Fix several pmpcfg issues. This is the simplest way to mask, the alternative is to create a custom function to set each field. I'll add a comment for that magic value.
2020-03-29Mask pmpXcfg bits as required by specScott Johnson1-1/+1
See "Figure 3.28: PMP configuration register format." in RISC-V Privileged Spec. Bits 6 and 5 are required to be 0.
2020-03-29Read pmpcfg* value back out when reporting its valueScott Johnson1-4/+4
So that the reported value will see the masked bits that I am going to add next.
2020-03-29Fix typos that made pmp8cfg and pmp9cfg unwritableScott Johnson1-4/+4
I'm not sure why this didn't cause a Sail compile error.
2020-03-03Add bit negation to preludeThomas Bauereiss1-1/+5
For bounds calculation in sail-cheri-riscv.
2020-02-28Make types of min/max more preciseThomas Bauereiss1-8/+6
Might help typechecking sail-cheri-riscv code.
2020-02-26Add convenience 'osim' target for ocaml emulator.Robert Norton1-0/+2
2020-02-25Change operand order for csr instructions assembly to match spec. Fixes #34.Robert Norton1-2/+2
2020-02-25Re-instate csr names in assembly with an alternative workaround for sail bug ↵Robert Norton2-1/+6
https://github.com/rems-project/sail/issues/62 . This reverts 82c7152b7374d9c24b2464a055aa4cd140048717. Fixes #35.
2020-02-25Revert "Further workaround for Sail mapping bug."Robert Norton1-2/+2
This reverts commit 82c7152b7374d9c24b2464a055aa4cd140048717.
2020-02-19Merge pull request #42 from arichardson/loopbackPrashanth Mundkur1-1/+1
Only listen for RVFI-DII messages on 127.0.0.1
2020-02-19Only listen for RVFI-DII messages on 127.0.0.1Alex Richardson1-1/+1
2020-02-14Change RVFI ram size to 8MB as requested by Jon Woodruff. TODO: should make ↵Robert Norton1-1/+1
it possible to override this using the -z option.
2020-02-13Merge pull request #41 from scottj97/fcsr-fixPrashanth Mundkur2-5/+4
Report correct value in trace for CSR writes to frm and fflags
2020-02-13Report correct value in trace for CSR writes to frm and fflagsScott Johnson2-5/+4
Previously it was always reporting the entire fcsr value as the new value of fflags/frm. Fixes #40.
2020-02-06Update mstatus.SD bit as well when dirtying the floating-point status.Prashanth Mundkur1-5/+9
2020-02-06Handle locked TOR entries when writing PMP addresses.Prashanth Mundkur3-22/+28
Fixes #36.
2020-02-06Initialize fdregs for rvfi.Prashanth Mundkur1-0/+1
2020-02-06Improve handling of fcsr by making it a bitfield.Prashanth Mundkur4-55/+75
Also properly dirty the FS bit in mstatus when writing to floating-point state. Fixes #38.
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