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-rw-r--r--model/riscv_jalr_seq.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_jalr_seq.sail b/model/riscv_jalr_seq.sail
index d4982c6..3dcae61 100644
--- a/model/riscv_jalr_seq.sail
+++ b/model/riscv_jalr_seq.sail
@@ -7,7 +7,7 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
some manner, but for now, we just keep a reordered definition to improve simulator
performance.
*/
- let newPC : xlenbits = (X(rs1) + EXTS(imm))[(xlen_val) - 1 .. 1] @ 0b0;
+ let newPC : xlenbits = (X(rs1) + EXTS(imm))[(xlen - 1) .. 1] @ 0b0;
if newPC[1] & (~ (haveRVC())) then {
handle_mem_exception(newPC, E_Fetch_Addr_Align);
false;