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-rw-r--r--model/riscv_insts_end.sail24
1 files changed, 24 insertions, 0 deletions
diff --git a/model/riscv_insts_end.sail b/model/riscv_insts_end.sail
index 144f06e..f52b6dc 100644
--- a/model/riscv_insts_end.sail
+++ b/model/riscv_insts_end.sail
@@ -1,3 +1,27 @@
+/* Put the illegal instructions last to use their wildcard match. */
+
+/* ****************************************************************** */
+
+union clause ast = ILLEGAL : word
+
+mapping clause encdec = ILLEGAL(s) <-> s
+
+function clause execute (ILLEGAL(s)) = { handle_illegal(); false }
+
+mapping clause assembly = ILLEGAL(s) <-> "illegal" ^ spc() ^ hex_bits_32(s)
+
+/* ****************************************************************** */
+
+union clause ast = C_ILLEGAL : half
+
+mapping clause encdec_compressed = C_ILLEGAL(s) <-> s
+
+function clause execute C_ILLEGAL(s) = { handle_illegal(); false }
+
+mapping clause assembly = C_ILLEGAL(s) <-> "c.illegal" ^ spc() ^ hex_bits_16(s)
+
+/* ****************************************************************** */
+
/* End definitions */
end ast
end execute