diff options
Diffstat (limited to 'doc')
-rw-r--r-- | doc/ExtendingGuide.md | 16 | ||||
-rw-r--r-- | doc/ReadingGuide.md | 10 |
2 files changed, 25 insertions, 1 deletions
diff --git a/doc/ExtendingGuide.md b/doc/ExtendingGuide.md index 4533b8b..82a418d 100644 --- a/doc/ExtendingGuide.md +++ b/doc/ExtendingGuide.md @@ -33,6 +33,15 @@ existing definitions for privilege levels and exceptions in `riscv_types.sail`, and modifying the exception handling and privilege transition functions in `riscv_sys_control.sail`. +Modifying exception handling +---------------------------- + +An extension that needs to interact closely with exception handling +may need to capture additional information at the time of an +exception. This is supported using the `ext` field in the +`sync_exception` type in `riscv_sync_exception.sail`, which is where +the extension can store this information. + Adding low-level platform functionality --------------------------------------- @@ -91,6 +100,13 @@ The handling of the memory addresses involved during exception handling can be extending using the interface defined in `riscv_sys_exceptions.sail`. +Checking and transforming the program counter +--------------------------------------------- + +An extension might want to similarly check and transform accesses to +the program counter. This is supported by supplying implementations +of the functions defined in `riscv_pc_access.sail`. + Adding new instructions ----------------------- diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md index 5c7e656..ad09cf0 100644 --- a/doc/ReadingGuide.md +++ b/doc/ReadingGuide.md @@ -25,13 +25,21 @@ The model contains the following Sail modules in the `model` directory: register type is separately defined in `riscv_reg_type.sail` so that extensions of the model can redefine it if required. +- `riscv_regs.sail` contains the base register file, where each + register is defined as having the `regtype` type defined in + `riscv_reg_type.sail`. + +- `riscv_pc_access.sail` defines functions to access and modify the + program counter. + - `riscv_sys_regs.sail` describes the privileged architectural state, viz. M-mode and S-mode CSRs, and contains helpers to interpret their content, such as WLRL and WARL fields. `riscv_sys_control.sail` describes interrupt and exception delegation and dispatch, and the handling of privilege transitions. `riscv_sys_exceptions.sail` defines the handling of the addresses involved in exception - handling. + handling. `riscv_sync_exception.sail` describes the structure used + to capture the architectural information for an exception. Since WLRL and WARL fields are intended to capture platform-specific functionality, future versions of the model might separate their |