diff options
| -rw-r--r-- | model/riscv_ext_regs.sail | 2 | ||||
| -rw-r--r-- | model/riscv_insts_zicsr.sail | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_ext_regs.sail b/model/riscv_ext_regs.sail index 28ed111..efe9bae 100644 --- a/model/riscv_ext_regs.sail +++ b/model/riscv_ext_regs.sail @@ -28,7 +28,7 @@ function ext_rvfi_init () = { THIS(csrno, priv, isWrite) allows an extension to block access to csrno, at Privilege level priv. It should return true if the access is allowed. */ -val ext_check_CSR : (bits(12), Privilege, bool) -> bool +val ext_check_CSR : (csreg, Privilege, bool) -> bool function ext_check_CSR (csrno, p, isWrite) = true /*! diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index 7c52abd..f2980fb 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -10,7 +10,7 @@ /* This file specifies the instructions in the 'Zicsr' extension. */ /* ****************************************************************** */ -union clause ast = CSR : (bits(12), regidx, regidx, bool, csrop) +union clause ast = CSR : (csreg, regidx, regidx, bool, csrop) mapping encdec_csrop : csrop <-> bits(2) = { CSRRW <-> 0b01, |