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author | Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> | 2019-06-27 12:12:26 +0100 |
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committer | Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> | 2019-06-27 12:12:26 +0100 |
commit | f690484f56e41605a46c173c3c11a7c25485cf55 (patch) | |
tree | bcea7dda8cf20f4689bdd79c2e2fcfb66dc6d7e9 /os-boot | |
parent | 5dc38f37b871af7d6d1af9dfbbb203fb92d99d6a (diff) | |
download | sail-riscv-f690484f56e41605a46c173c3c11a7c25485cf55.zip sail-riscv-f690484f56e41605a46c173c3c11a7c25485cf55.tar.gz sail-riscv-f690484f56e41605a46c173c3c11a7c25485cf55.tar.bz2 |
os-boot: Add a Spike-derivative DTS with chosen node for Hafnium
Diffstat (limited to 'os-boot')
-rw-r--r-- | os-boot/rv64-2gb-hafnium.dts | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/os-boot/rv64-2gb-hafnium.dts b/os-boot/rv64-2gb-hafnium.dts new file mode 100644 index 0000000..d67bfb2 --- /dev/null +++ b/os-boot/rv64-2gb-hafnium.dts @@ -0,0 +1,53 @@ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "ucbbar,spike-bare-dev"; + model = "ucbbar,spike-bare"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imac"; + mmu-type = "riscv,sv39"; + clock-frequency = <1000000000>; + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "ucbbar,spike-bare-soc", "simple-bus"; + ranges; + clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >; + reg = <0x0 0x2000000 0x0 0xc0000>; + }; + }; + htif { + compatible = "ucb,htif0"; + }; + chosen { + #address-cells = <2>; + #size-cells = <2>; + linux,initrd-end = <0 0>; + linux,initrd-start = <0 0>; + bootargs = "rdinit=/sbin/init"; + stdout-path = ""; + }; +}; |