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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-29 10:49:09 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-29 10:49:09 -0700 |
| commit | ec7d9a39e8d1fb70a7f3ca83980d9e906ca49472 (patch) | |
| tree | 7e0cf12092247f3f3b8f1a40eef86553c22c5778 /ocaml_emulator | |
| parent | fe2b7a1cabe6c3dbc9d6573217173d2b428d81eb (diff) | |
| download | sail-riscv-ec7d9a39e8d1fb70a7f3ca83980d9e906ca49472.zip sail-riscv-ec7d9a39e8d1fb70a7f3ca83980d9e906ca49472.tar.gz sail-riscv-ec7d9a39e8d1fb70a7f3ca83980d9e906ca49472.tar.bz2 | |
Generalize the previous commit to handle hardwired misa.c.
Diffstat (limited to 'ocaml_emulator')
| -rw-r--r-- | ocaml_emulator/platform.ml | 29 | ||||
| -rw-r--r-- | ocaml_emulator/riscv_ocaml_sim.ml | 6 |
2 files changed, 23 insertions, 12 deletions
diff --git a/ocaml_emulator/platform.ml b/ocaml_emulator/platform.ml index 0cf4861..2c0125b 100644 --- a/ocaml_emulator/platform.ml +++ b/ocaml_emulator/platform.ml @@ -4,8 +4,10 @@ module Elf = Elf_loader;; (* Platform configuration *) -let config_enable_dirty_update = ref false -let config_enable_misaligned_access = ref false +let config_enable_rvc = ref true +let config_enable_writable_misa = ref true +let config_enable_dirty_update = ref false +let config_enable_misaligned_access = ref false let config_mtval_has_illegal_inst_bits = ref false let platform_arch = ref P.RV64 @@ -65,24 +67,27 @@ let make_rom arch start_pc = *) rom ) -let enable_dirty_update () = !config_enable_dirty_update -let enable_misaligned_access () = !config_enable_misaligned_access -let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits +let enable_writable_misa () = !config_enable_writable_misa +let enable_rvc () = !config_enable_rvc +let enable_dirty_update () = !config_enable_dirty_update +let enable_misaligned_access () = !config_enable_misaligned_access +let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits -let rom_base () = arch_bits_of_int64 P.rom_base -let rom_size () = arch_bits_of_int !rom_size_ref +let rom_base () = arch_bits_of_int64 P.rom_base +let rom_size () = arch_bits_of_int !rom_size_ref -let dram_base () = arch_bits_of_int64 P.dram_base -let dram_size () = arch_bits_of_int64 !P.dram_size_ref - -let htif_tohost () = - arch_bits_of_int64 (Big_int.to_int64 (Elf.elf_tohost ())) +let dram_base () = arch_bits_of_int64 P.dram_base +let dram_size () = arch_bits_of_int64 !P.dram_size_ref let clint_base () = arch_bits_of_int64 P.clint_base let clint_size () = arch_bits_of_int64 P.clint_size let insns_per_tick () = Big_int.of_int P.insns_per_tick +let htif_tohost () = + arch_bits_of_int64 (Big_int.to_int64 (Elf.elf_tohost ())) + + (* load reservation *) let speculate_conditional () = true diff --git a/ocaml_emulator/riscv_ocaml_sim.ml b/ocaml_emulator/riscv_ocaml_sim.ml index 9046a2f..5f5c716 100644 --- a/ocaml_emulator/riscv_ocaml_sim.ml +++ b/ocaml_emulator/riscv_ocaml_sim.ml @@ -40,6 +40,12 @@ let options = Arg.align ([("-dump-dts", ("-mtval-has-illegal-inst-bits", Arg.Set P.config_mtval_has_illegal_inst_bits, " mtval stores instruction bits on an illegal instruction exception"); + ("-disable-rvc", + Arg.Clear P.config_enable_rvc, + " disable the RVC extension on boot"); + ("-disable-writable-misa-c", + Arg.Clear P.config_enable_writable_misa, + " leave misa hardwired to its initial value"); ("-ram-size", Arg.Int PI.set_dram_size, " size of physical ram memory to use (in MB)"); |