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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-20 13:32:59 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-20 13:32:59 -0800 |
| commit | 31c55d5e0b10a53699de2b5712fbeb4350aa20b5 (patch) | |
| tree | 1965502d52ef63b45f97ab776f70eda936e4f931 /ocaml_emulator | |
| parent | 5cb13966646d6d09f2589cd0992f1771cffc72ca (diff) | |
| download | sail-riscv-31c55d5e0b10a53699de2b5712fbeb4350aa20b5.zip sail-riscv-31c55d5e0b10a53699de2b5712fbeb4350aa20b5.tar.gz sail-riscv-31c55d5e0b10a53699de2b5712fbeb4350aa20b5.tar.bz2 | |
Add an option to report the model architecture to the emulators.
Diffstat (limited to 'ocaml_emulator')
| -rw-r--r-- | ocaml_emulator/riscv_ocaml_sim.ml | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/ocaml_emulator/riscv_ocaml_sim.ml b/ocaml_emulator/riscv_ocaml_sim.ml index e1acc08..05912f5 100644 --- a/ocaml_emulator/riscv_ocaml_sim.ml +++ b/ocaml_emulator/riscv_ocaml_sim.ml @@ -61,6 +61,10 @@ let opt_file_arguments = ref ([] : string list) let opt_dump_dts = ref false let opt_dump_dtb = ref false +let report_arch () = + Printf.printf "RV%d\n" (Big_int.to_int Riscv.zxlen_val); + exit 0 + let options = Arg.align ([("-dump-dts", Arg.Set opt_dump_dts, " dump the platform device-tree source to stdout"); @@ -79,6 +83,9 @@ let options = Arg.align ([("-dump-dts", ("-ram-size", Arg.Int PI.set_dram_size, " size of physical ram memory to use (in MB)"); + ("-report-arch", + Arg.Unit report_arch, + " report model architecture (RV32 or RV64)"); ("-with-dtc", Arg.String PI.set_dtc, " full path to dtc to use") |