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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-02-12 09:24:11 -0800 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-02-12 09:24:11 -0800 |
commit | 83df28ae4128babc55157756b63f8684e94e55ca (patch) | |
tree | d8e92236c389bb0c26576a1865ba3997babd5016 /ocaml_emulator | |
parent | c34a5ce3e05624eff9daa89770e5d6be627393a4 (diff) | |
parent | ca57c1be19447a5ec831292f0ca4081ffc13b436 (diff) | |
download | sail-riscv-83df28ae4128babc55157756b63f8684e94e55ca.zip sail-riscv-83df28ae4128babc55157756b63f8684e94e55ca.tar.gz sail-riscv-83df28ae4128babc55157756b63f8684e94e55ca.tar.bz2 |
Merge branch 'master' into gdbgdb
Diffstat (limited to 'ocaml_emulator')
-rw-r--r-- | ocaml_emulator/platform.ml | 1 | ||||
-rw-r--r-- | ocaml_emulator/softfloat.ml | 91 |
2 files changed, 92 insertions, 0 deletions
diff --git a/ocaml_emulator/platform.ml b/ocaml_emulator/platform.ml index b2a19fe..9996268 100644 --- a/ocaml_emulator/platform.ml +++ b/ocaml_emulator/platform.ml @@ -75,6 +75,7 @@ let make_rom arch start_pc = let enable_writable_misa () = !config_enable_writable_misa let enable_rvc () = !config_enable_rvc +let enable_fdext () = false let enable_dirty_update () = !config_enable_dirty_update let enable_misaligned_access () = !config_enable_misaligned_access let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits diff --git a/ocaml_emulator/softfloat.ml b/ocaml_emulator/softfloat.ml new file mode 100644 index 0000000..ef84185 --- /dev/null +++ b/ocaml_emulator/softfloat.ml @@ -0,0 +1,91 @@ + +let f32_add rm v1 v2 = + () + +let f32_sub rm v1 v2 = + () + +let f32_mul rm v1 v2 = + () + +let f32_div rm v1 v2 = + () + +let f64_add rm v1 v2 = + () + +let f64_sub rm v1 v2 = + () + +let f64_mul rm v1 v2 = + () + +let f64_div rm v1 v2 = + () + +let f32_muladd rm v1 v2 v3 = + () + +let f64_muladd rm v1 v2 v3 = + () + +let f32_sqrt rm v = + () + +let f64_sqrt rm v = + () + +let f32_to_i32 rm v = + () + +let f32_to_ui32 rm v = + () + +let i32_to_f32 rm v = + () + +let ui32_to_f32 rm v = + () + +let f32_to_i64 rm v = + () + +let f32_to_ui64 rm v = + () + +let i64_to_f32 rm v = + () + +let ui64_to_f32 rm v = + () + +let f64_to_i32 rm v = + () + +let f64_to_ui32 rm v = + () + +let i32_to_f64 rm v = + () + +let ui32_to_f64 rm v = + () + +let f64_to_i64 rm v = + () + +let f64_to_ui64 rm v = + () + +let i64_to_f64 rm v = + () + +let ui64_to_f64 rm v = + () + +let f32_to_f64 rm v = + () + +let f64_to_f32 rm v = + () + |