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author | Ved Shanbhogue <ved@rivosinc.com> | 2024-02-25 10:15:12 -0600 |
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committer | Bill McSpadden <bill@riscv.org> | 2024-03-24 20:31:57 -0500 |
commit | 51b9732fe7cc85c0895039e181e522f4d846d3cd (patch) | |
tree | 6ff0f82ec31f6c56fd4873e1ccc9e101453d5970 /model | |
parent | 4a7c815ee29d29c5b80c7d5335d75a8624380eb1 (diff) | |
download | sail-riscv-51b9732fe7cc85c0895039e181e522f4d846d3cd.zip sail-riscv-51b9732fe7cc85c0895039e181e522f4d846d3cd.tar.gz sail-riscv-51b9732fe7cc85c0895039e181e522f4d846d3cd.tar.bz2 |
Fix error in senvcfg definition
Diffstat (limited to 'model')
-rw-r--r-- | model/riscv_insts_zicsr.sail | 8 | ||||
-rw-r--r-- | model/riscv_sys_regs.sail | 32 |
2 files changed, 29 insertions, 11 deletions
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index ef9e73e..d106ad2 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -122,10 +122,10 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = { (0x304, _) => { mie = legalize_mie(mie, value); Some(mie.bits) }, (0x305, _) => { Some(set_mtvec(value)) }, (0x306, _) => { mcounteren = legalize_mcounteren(mcounteren, value); Some(zero_extend(mcounteren.bits)) }, - (0x30A, 32) => { menvcfg = legalize_envcfg(menvcfg, menvcfg.bits[63 .. 32] @ value); Some(menvcfg.bits[31 .. 0]) }, - (0x30A, 64) => { menvcfg = legalize_envcfg(menvcfg, value); Some(menvcfg.bits) }, + (0x30A, 32) => { menvcfg = legalize_menvcfg(menvcfg, menvcfg.bits[63 .. 32] @ value); Some(menvcfg.bits[31 .. 0]) }, + (0x30A, 64) => { menvcfg = legalize_menvcfg(menvcfg, value); Some(menvcfg.bits) }, (0x310, 32) => { Some(mstatush.bits) }, // ignore writes for now - (0x31A, 32) => { menvcfg = legalize_envcfg(menvcfg, value @ menvcfg.bits[31 .. 0]); Some(menvcfg.bits[63 .. 32]) }, + (0x31A, 32) => { menvcfg = legalize_menvcfg(menvcfg, value @ menvcfg.bits[31 .. 0]); Some(menvcfg.bits[63 .. 32]) }, (0x320, _) => { mcountinhibit = legalize_mcountinhibit(mcountinhibit, value); Some(zero_extend(mcountinhibit.bits)) }, (0x340, _) => { mscratch = value; Some(mscratch) }, (0x341, _) => { Some(set_xret_target(Machine, value)) }, @@ -161,7 +161,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = { (0x104, _) => { mie = legalize_sie(mie, mideleg, value); Some(mie.bits) }, (0x105, _) => { Some(set_stvec(value)) }, (0x106, _) => { scounteren = legalize_scounteren(scounteren, value); Some(zero_extend(scounteren.bits)) }, - (0x10A, _) => { senvcfg = legalize_envcfg(senvcfg, zero_extend(value)); Some(senvcfg.bits[sizeof(xlen) - 1 .. 0]) }, + (0x10A, _) => { senvcfg = legalize_senvcfg(senvcfg, zero_extend(value)); Some(senvcfg.bits[sizeof(xlen) - 1 .. 0]) }, (0x140, _) => { sscratch = value; Some(sscratch) }, (0x141, _) => { Some(set_xret_target(Supervisor, value)) }, (0x142, _) => { scause.bits = value; Some(scause.bits) }, diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index fc20e4a..2ab1771 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -766,9 +766,7 @@ function read_seed_csr() -> xlenbits = { /* Writes to the seed CSR are ignored */ function write_seed_csr () -> option(xlenbits) = None() -// menvcfg is 64 bits. senvcfg is SXLEN bits and does not have the two -// upper fields so for simplicity we can use the same type. -bitfield Envcfg : bits(64) = { +bitfield MEnvcfg : bits(64) = { // Supervisor TimeCmp Extension STCE : 63, // Page Based Memory Types Extension @@ -787,11 +785,31 @@ bitfield Envcfg : bits(64) = { FIOM : 0, } -register menvcfg : Envcfg -register senvcfg : Envcfg +bitfield SEnvcfg : xlenbits = { + // Cache Block Zero instruction Enable + CBZE : 7, + // Cache Block Clean and Flush instruction Enable + CBCFE : 6, + // Cache Block Invalidate instruction Enable + CBIE : 5 .. 4, + // Reserved WPRI bits. + wpri_0 : 3 .. 1, + // Fence of I/O implies Memory + FIOM : 0, +} + +register menvcfg : MEnvcfg +register senvcfg : SEnvcfg + +function legalize_menvcfg(o : MEnvcfg, v : bits(64)) -> MEnvcfg = { + let v = Mk_MEnvcfg(v); + let o = [o with FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0]; + // Other extensions are not implemented yet so all other fields are read only zero. + o +} -function legalize_envcfg(o : Envcfg, v : bits(64)) -> Envcfg = { - let v = Mk_Envcfg(v); +function legalize_senvcfg(o : SEnvcfg, v : xlenbits) -> SEnvcfg = { + let v = Mk_SEnvcfg(v); let o = [o with FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0]; // Other extensions are not implemented yet so all other fields are read only zero. o |