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| author | Robert Norton <rmn30@cam.ac.uk> | 2019-02-15 11:53:41 +0000 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-29 09:31:53 -0700 |
| commit | fe2b7a1cabe6c3dbc9d6573217173d2b428d81eb (patch) | |
| tree | 2a9e62b0645fa1345a4465e2b78a56376547c2ee /model | |
| parent | b8add6318e6d8edbd120b41d2b58c8b07cb89715 (diff) | |
| download | sail-riscv-fe2b7a1cabe6c3dbc9d6573217173d2b428d81eb.zip sail-riscv-fe2b7a1cabe6c3dbc9d6573217173d2b428d81eb.tar.gz sail-riscv-fe2b7a1cabe6c3dbc9d6573217173d2b428d81eb.tar.bz2 | |
Tweak legalize_xepc according to spec: xepc[1] should always be writeable.
Diffstat (limited to 'model')
| -rw-r--r-- | model/riscv_sys_regs.sail | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 439d12d..caec739 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -319,10 +319,11 @@ function tvec_addr(m : Mtvec, c : Mcause) -> option(xlenbits) = { register mepc : xlenbits -// legalizing writes to xepc -function legalize_xepc(v : xlenbits) -> xlenbits = { - v & EXTS(if haveRVC() then 0b110 else 0b100) -} +/* Legalize writes to xepc -- just clear bit zero. + Spec says that mepc[1] is writable even if IALIGN=32 */ +function legalize_xepc(v : xlenbits) -> xlenbits = + [v with 0 = bitzero] + // masking for reads to xepc function pc_alignment_mask() -> xlenbits = |