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authorAlasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk>2019-08-19 18:49:23 +0100
committerAlasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk>2019-08-19 18:53:00 +0100
commita381a832bb39bb7571725f75c27dc257762cd693 (patch)
tree29c1d4210ffa91e372f94f2567e3f3275b466b4e /model/riscv_vmem_sv48.sail
parentc0c70effa02100c16870251b2a27b79a1cab7331 (diff)
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RISC-V spec, without implicit casts
Diffstat (limited to 'model/riscv_vmem_sv48.sail')
-rw-r--r--model/riscv_vmem_sv48.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_vmem_sv48.sail b/model/riscv_vmem_sv48.sail
index a898ac7..18abafd 100644
--- a/model/riscv_vmem_sv48.sail
+++ b/model/riscv_vmem_sv48.sail
@@ -19,7 +19,7 @@ function walk48(vaddr, ac, priv, mxr, do_sum, ptb, level, global) = {
let pte = Mk_SV48_PTE(v);
let pbits = pte.BITS();
let pattr = Mk_PTE_Bits(pbits);
- let is_global = global | (pattr.G() == true);
+ let is_global = global | (pattr.G() == 0b1);
/* print("walk48(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
^ " pt_base=" ^ BitStr(ptb)
^ " pt_ofs=" ^ BitStr(pt_ofs)