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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-24 16:55:18 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-24 18:11:18 -0700 |
| commit | bbb65b3c3422d02989015a6135cf36107f10ad95 (patch) | |
| tree | 98f7f7bc49e5a9779428eb6a38727e8913bb3b7b /model/riscv_vmem_rv32.sail | |
| parent | 295175dd4d510cb416bdc4ef17c2ca96d84ed04e (diff) | |
| download | sail-riscv-bbb65b3c3422d02989015a6135cf36107f10ad95.zip sail-riscv-bbb65b3c3422d02989015a6135cf36107f10ad95.tar.gz sail-riscv-bbb65b3c3422d02989015a6135cf36107f10ad95.tar.bz2 | |
Add PMP checks to physical memory accesses.
- unify AccessType and ReadType since they were essentially redundant,
making it easier to implement PMP checks for ReadWrite/atomic accesses.
- add command line options to enable PMP in the platform
- also fix the matching for the case when all entries are off
Diffstat (limited to 'model/riscv_vmem_rv32.sail')
| -rw-r--r-- | model/riscv_vmem_rv32.sail | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/model/riscv_vmem_rv32.sail b/model/riscv_vmem_rv32.sail index d0fac76..5b640b1 100644 --- a/model/riscv_vmem_rv32.sail +++ b/model/riscv_vmem_rv32.sail @@ -26,11 +26,11 @@ function translationMode(priv) = { /* Top-level address translation dispatcher */ -val translateAddr : (xlenbits, AccessType, ReadType) -> TR_Result(xlenbits, ExceptionType) effect {escape, rmem, rreg, wmv, wmvt, wreg} -function translateAddr(vAddr, ac, rt) = { - let effPriv : Privilege = match rt { - Instruction => cur_privilege, - Data => effectivePrivilege(mstatus, cur_privilege) +val translateAddr : (xlenbits, AccessType) -> TR_Result(xlenbits, ExceptionType) effect {escape, rmem, rreg, wmv, wmvt, wreg} +function translateAddr(vAddr, ac) = { + let effPriv : Privilege = match ac { + Execute => cur_privilege, + _ => effectivePrivilege(mstatus, cur_privilege) }; let mxr : bool = mstatus.MXR() == true; let do_sum : bool = mstatus.SUM() == true; |