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| author | Ibrahim Abu Kharmeh <abukharmeh@gmail.com> | 2021-11-17 15:41:15 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-11-17 15:41:15 +0000 |
| commit | c5e62ea4b3d481fcd491b22b317cc319b089f05d (patch) | |
| tree | 5ddc23d7d67d434cd54b59dd8e3ae207f10fb430 /model/riscv_sys_control.sail | |
| parent | 01720566318e292df12693bba1fe5f09ea0857df (diff) | |
| download | sail-riscv-c5e62ea4b3d481fcd491b22b317cc319b089f05d.zip sail-riscv-c5e62ea4b3d481fcd491b22b317cc319b089f05d.tar.gz sail-riscv-c5e62ea4b3d481fcd491b22b317cc319b089f05d.tar.bz2 | |
Initial introduction of zfinx (#75)
* Adds Zfinx enable flag
* Hardwire misa.{f,d} and mstats.FS to 0
* Moving nan boxing functions to fdext_reg
* Swaps register names for floating point instructions
Adds new mapping to swap register names, and use it in all assembly clauses
* Disable Floating point loads, stores and moves
* Add X_or_F_s and X_or_F_d functions, and use them to access all registers for floating points
Changes register accessed for floating point instructions and modify nan boxing functions for zfinx
* Formatting
Remove couple of misplaced whitespace, unnecessary parens
* Fix inconsistent indentation in insts_dext file
* Fix spacing in fdext_regs
* Remove redundant comparasion with true/ false
* Constistant tuples spacing and removes couple of unnecessary parens.
* Consistent functions declaration & calls spacing and removes couple of unnecessary parens.
* Consistent spacing and removes couple of unnecessary comparasion with true/false
* Make spacing consistent
* Remove checks from execution stage
* Add checks to encdec stage
Diffstat (limited to 'model/riscv_sys_control.sail')
| -rw-r--r-- | model/riscv_sys_control.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index f5ee261..06be736 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -560,9 +560,9 @@ function init_sys() -> unit = { misa->S() = 0b1; /* supervisor-mode */ /* We currently support both F and D */ - misa->F() = bool_to_bits(sys_enable_fdext()); /* single-precision */ - misa->D() = if sizeof(flen) >= 64 - then bool_to_bits(sys_enable_fdext()) /* double-precision */ + misa->F() = bool_to_bits(sys_enable_fdext() & ~ (sys_enable_zfinx())); /* single-precision */ + misa->D() = if sizeof(flen) >= 64 & ~ (sys_enable_zfinx()) + then bool_to_bits(sys_enable_fdext()) /* double-precision */ else 0b0; mstatus = set_mstatus_SXL(mstatus, misa.MXL()); |