diff options
author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-24 16:55:18 -0700 |
---|---|---|
committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-24 18:11:18 -0700 |
commit | bbb65b3c3422d02989015a6135cf36107f10ad95 (patch) | |
tree | 98f7f7bc49e5a9779428eb6a38727e8913bb3b7b /model/riscv_sys_control.sail | |
parent | 295175dd4d510cb416bdc4ef17c2ca96d84ed04e (diff) | |
download | sail-riscv-bbb65b3c3422d02989015a6135cf36107f10ad95.zip sail-riscv-bbb65b3c3422d02989015a6135cf36107f10ad95.tar.gz sail-riscv-bbb65b3c3422d02989015a6135cf36107f10ad95.tar.bz2 |
Add PMP checks to physical memory accesses.
- unify AccessType and ReadType since they were essentially redundant,
making it easier to implement PMP checks for ReadWrite/atomic accesses.
- add command line options to enable PMP in the platform
- also fix the matching for the case when all entries are off
Diffstat (limited to 'model/riscv_sys_control.sail')
-rw-r--r-- | model/riscv_sys_control.sail | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index e866986..27c2566 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -444,6 +444,8 @@ function init_sys() -> unit = { minstret = EXTZ(0b0); minstret_written = false; + init_pmp(); + // log compatibility with spike print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(EXTZ(0b0) : xlenbits) ^ ")") } |