aboutsummaryrefslogtreecommitdiff
path: root/model/riscv_sys_control.sail
diff options
context:
space:
mode:
authorThomas Bauereiss <tb592@cl.cam.ac.uk>2019-10-04 17:08:25 +0100
committerPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-10-09 21:40:05 -0700
commita13c0a435804a9a8250054c2e9af2eacfa883164 (patch)
tree213a030c3ca2b950f3d691c2932185fea48ee92d /model/riscv_sys_control.sail
parentba18f0f59cee8e3c32cfaa980c0d109399284844 (diff)
downloadsail-riscv-a13c0a435804a9a8250054c2e9af2eacfa883164.zip
sail-riscv-a13c0a435804a9a8250054c2e9af2eacfa883164.tar.gz
sail-riscv-a13c0a435804a9a8250054c2e9af2eacfa883164.tar.bz2
Read/write memory values and metadata together atomically
For Lem, bypass the Sail implementation of {read,write}_ram and map to atomic primitives directly. We might want to make these functions primitive for other backends as well.
Diffstat (limited to 'model/riscv_sys_control.sail')
-rw-r--r--model/riscv_sys_control.sail12
1 files changed, 12 insertions, 0 deletions
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 8162cb8..3db3bbf 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -489,3 +489,15 @@ union MemoryOpResult ('a : Type) = {
MemValue : 'a,
MemException : ExceptionType
}
+
+val MemoryOpResult_add_meta : forall ('t : Type). (MemoryOpResult('t), mem_meta) -> MemoryOpResult(('t, mem_meta))
+function MemoryOpResult_add_meta(r, m) = match r {
+ MemValue(v) => MemValue(v, m),
+ MemException(e) => MemException(e)
+}
+
+val MemoryOpResult_drop_meta : forall ('t : Type). MemoryOpResult(('t, mem_meta)) -> MemoryOpResult('t)
+function MemoryOpResult_drop_meta(r) = match r {
+ MemValue(v, m) => MemValue(v),
+ MemException(e) => MemException(e)
+}