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author | Jessica Clarke <jrtc27@jrtc27.com> | 2021-10-22 15:15:00 +0100 |
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committer | GitHub <noreply@github.com> | 2021-10-22 15:15:00 +0100 |
commit | 9b38e33c766c7c0397b9d51bf91544db391be670 (patch) | |
tree | aee1fe8abd89feb13d924f7f39f346478e0dfd24 /model/riscv_sys_control.sail | |
parent | 1c7584bb501bb6d4cbc3b95cb22e008220fb537a (diff) | |
download | sail-riscv-9b38e33c766c7c0397b9d51bf91544db391be670.zip sail-riscv-9b38e33c766c7c0397b9d51bf91544db391be670.tar.gz sail-riscv-9b38e33c766c7c0397b9d51bf91544db391be670.tar.bz2 |
Support D extension on RV32 (#108)
* Use bool for floating point comparison result
Using bits_WU (bits(32)) or bits_LU (bits(64)) makes no sense, these are
just boolean values, and having fixed-width types is a pain for
suporting RV32D (since RV32D would need to truncate, but RV128D would
need to extend). Instead represent these as an actual bool to match what
the values really are. This could be done with bits(1) but the value is
logically a boolean (like the built-in integer comparison operators) not
a bit vector of length one so we convert to bool and back for a cleaner
interface.
* Support compiling RV32F with flen == 64
The code conflated flen and xlen; deconflating them and adding suitable
assertions (rather than silently retiring as a no-op that doesn't bump
instret) ensures that it can be compiled for RV32 with flen set to 64.
Whilst here, add the extensions and truncations that would be needed for
RV128F.
Note that there are already suitable guards on the decode clauses to
ensure these instructions are illegal on RV32.
* Support compiling RV32D
This copies various bits of XLEN generality from the F code.
* Support RV32D loads/stores
* Correctly initialise misa.D based on flen not xlen
* Makefile: Enable D extension for RV32
This now works so can be enabled.
* test: Enable RV32D tests
Diffstat (limited to 'model/riscv_sys_control.sail')
-rw-r--r-- | model/riscv_sys_control.sail | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index a3859ff..f5ee261 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -559,11 +559,9 @@ function init_sys() -> unit = { misa->U() = 0b1; /* user-mode */ misa->S() = 0b1; /* supervisor-mode */ - /* On RV64, we currently support either both F and D, or neither. - * On RV32, we currently only support F. - */ + /* We currently support both F and D */ misa->F() = bool_to_bits(sys_enable_fdext()); /* single-precision */ - misa->D() = if sizeof(xlen) == 64 + misa->D() = if sizeof(flen) >= 64 then bool_to_bits(sys_enable_fdext()) /* double-precision */ else 0b0; |