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| author | Jon French <jf451@cam.ac.uk> | 2019-04-12 14:42:33 +0100 |
|---|---|---|
| committer | Jon French <jf451@cam.ac.uk> | 2019-04-12 14:42:33 +0100 |
| commit | 4ddeb44d2eed3f97ddb3739f1a44af8973936b89 (patch) | |
| tree | bf8af6ab037e98c9630e61abf25d81990a53b42b /model/riscv_sys_control.sail | |
| parent | d8cd74d5ea994957a607819267afc03f05f3566b (diff) | |
| parent | ca184a708aa5336efe573fed14d4dfcd9cb27dde (diff) | |
| download | sail-riscv-4ddeb44d2eed3f97ddb3739f1a44af8973936b89.zip sail-riscv-4ddeb44d2eed3f97ddb3739f1a44af8973936b89.tar.gz sail-riscv-4ddeb44d2eed3f97ddb3739f1a44af8973936b89.tar.bz2 | |
Merge branch 'master' into rmem_interpreterrmem_interpreter
Diffstat (limited to 'model/riscv_sys_control.sail')
| -rw-r--r-- | model/riscv_sys_control.sail | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index 2f02839..4155d66 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -415,18 +415,19 @@ function handle_interrupt(i : InterruptType, del_priv : Privilege) -> unit = /* state state initialization */ +val sys_enable_rvc = {c: "sys_enable_rvc", ocaml: "Platform.enable_rvc", _: "sys_enable_rvc"} : unit -> bool function init_sys() -> unit = { cur_privilege = Machine; mhartid = EXTZ(0b0); misa->MXL() = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64); - misa->A() = true; /* atomics */ - misa->C() = true; /* RVC */ - misa->I() = true; /* base integer ISA */ - misa->M() = true; /* integer multiply/divide */ - misa->U() = true; /* user-mode */ - misa->S() = true; /* supervisor-mode */ + misa->A() = true; /* atomics */ + misa->C() = sys_enable_rvc (); /* RVC */ + misa->I() = true; /* base integer ISA */ + misa->M() = true; /* integer multiply/divide */ + misa->U() = true; /* user-mode */ + misa->S() = true; /* supervisor-mode */ mstatus = set_mstatus_SXL(mstatus, misa.MXL()); mstatus = set_mstatus_UXL(mstatus, misa.MXL()); |