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| author | Tim Hutt <timothy.hutt@codasip.com> | 2023-03-22 16:07:40 +0000 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-05-29 20:54:22 +0200 |
| commit | 3d9db22c7a12e463cf55f68709d0c4bb9b1811f9 (patch) | |
| tree | c2e3e5d817836686a7115728982219b9e44e2460 /model/riscv_sys_control.sail | |
| parent | 98e8bf7a6d0e27683e3913e8ea55e0734ebb7d1c (diff) | |
| download | sail-riscv-3d9db22c7a12e463cf55f68709d0c4bb9b1811f9.zip sail-riscv-3d9db22c7a12e463cf55f68709d0c4bb9b1811f9.tar.gz sail-riscv-3d9db22c7a12e463cf55f68709d0c4bb9b1811f9.tar.bz2 | |
Fix minstret off-by-one when mcountinhibit is set
This fixes a small bug in `mcounthinhibit`. In the current code if you set `mcountinhibit=1` then it inhibits the count of that CSR write, whereas the spec says that it should only apply to future instructions:
> Any CSR write takes effect after the writing instruction has otherwise completed.
- From the priviledged spec, section 3.1.10 Hardware Performance Monitor.
Diffstat (limited to 'model/riscv_sys_control.sail')
| -rw-r--r-- | model/riscv_sys_control.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index 6681367..6ec39d1 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -594,7 +594,7 @@ function init_sys() -> unit = { mcounteren->bits() = EXTZ(0b0); minstret = EXTZ(0b0); - minstret_written = false; + minstret_increment = true; init_pmp(); |