diff options
| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 16:36:31 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-11 16:43:06 -0800 |
| commit | 1f476139d69d25800c26db8451e3a8af68606f66 (patch) | |
| tree | 7072f781affa46e5a766f8563f1cef123192222b /model/riscv_sys_control.sail | |
| parent | 3f7de72df81894456d47b3cff63103847d010059 (diff) | |
| download | sail-riscv-1f476139d69d25800c26db8451e3a8af68606f66.zip sail-riscv-1f476139d69d25800c26db8451e3a8af68606f66.tar.gz sail-riscv-1f476139d69d25800c26db8451e3a8af68606f66.tar.bz2 | |
Handle SXL/UXL not being present in mstatus in RV32 by using explicit getters/setters.
Diffstat (limited to 'model/riscv_sys_control.sail')
| -rw-r--r-- | model/riscv_sys_control.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index 3bdaadd..f2a88c5 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -416,8 +416,8 @@ function init_sys() -> unit = { misa->S() = true; /* supervisor-mode */ /* 64-bit only mode with no extensions */ - mstatus->SXL() = misa.MXL(); - mstatus->UXL() = misa.MXL(); + mstatus = set_mstatus_SXL(mstatus, misa.MXL()); + mstatus = set_mstatus_UXL(mstatus, misa.MXL()); mstatus->SD() = false; mip->bits() = EXTZ(0b0); |