RISC-V Vector Extension Supportvector-dev

This PR adds the following:

General Framework and Configurations:

* Introduced the V extension's general framework and configuration setting instructions.
* Updated model/riscv_insts_vext_vset.sail and effect matching functions in riscv_vlen.sail.
* Addressed code formatting issues and made revisions post the Nov 22 meeting.
* Co-authored by Nicolas Brunie and Jessica Clarke.

Vector Load/Store Instructions:

* Integrated vector load and store instructions.
* Enhanced the implementation of SEW, LMUL, VLEN and removed real numbers from the code.
* Updated vstart settings and removed unnecessary assert statements.
* Rectified bugs in vleff instructions and overhauled coding styles.
* Incorporated guards for vector encdec clauses and optimized memory access post vector load/store failures.

Vector Integer/Fixed-Point Instructions:

* Added vector integer/fixed-point arithmetic and mask instructions.
* Improved vector EEW and EMUL checking functions and introduced illegal instruction check functions.
* Fine-tuned code formatting for vector instruction checks.

Vector Floating-Point Instructions:

* Rolled out vector floating-point instructions and updated their conversion counterparts.
* Refreshed copyright headers specific to the vector extension code.

Vector Reduction and Mask Instructions:

* Integrated vector mask and reduction instructions.
* Addressed register overlap checks for vector mask instructions.

Miscellaneous Enhancements and Fixes:

* Updated vector CSR vtype.vill settings and judgements.
* Systematized patterns for vector illegal instruction checks.
* Rectified issues in vector load/store and reduction operations.
* Purged redundant elements from the V extension code and vector floating-point functions.
* Cleaned up softfloat makefiles and renamed EXTZ and EXTS within the V extension code.
* Addressed a clang-format check issue and NaN boxing anomalies. Provided annotations for pending RVV configurations.
* Initialized default VLEN value and set vlenb CSR.
* Set constraints for vector variable initialization and added mstatus.VS settings specific to the vector extension.

1 files changed, 26 insertions, 6 deletions

diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index cfac8bd..3830725 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -556,12 +556,13 @@ function init_sys() -> unit = {
   mhartid     = zero_extend(0b0);
 
   misa->MXL() = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);
-  misa->A()   = 0b1;                            /* atomics */
-  misa->C()   = bool_to_bits(sys_enable_rvc()); /* RVC */
-  misa->I()   = 0b1;                            /* base integer ISA */
-  misa->M()   = 0b1;                            /* integer multiply/divide */
-  misa->U()   = 0b1;                            /* user-mode */
-  misa->S()   = 0b1;                            /* supervisor-mode */
+  misa->A()   = 0b1;                             /* atomics */
+  misa->C()   = bool_to_bits(sys_enable_rvc());  /* RVC */
+  misa->I()   = 0b1;                             /* base integer ISA */
+  misa->M()   = 0b1;                             /* integer multiply/divide */
+  misa->U()   = 0b1;                             /* user-mode */
+  misa->S()   = 0b1;                             /* supervisor-mode */
+  misa->V()   = bool_to_bits(sys_enable_vext()); /* vector extension */
 
   if   sys_enable_fdext() & sys_enable_zfinx()
   then internal_error(__FILE__, __LINE__, "F and Zfinx cannot both be enabled!");
@@ -602,6 +603,25 @@ function init_sys() -> unit = {
 
   menvcfg->bits() = zero_extend(0b0);
   senvcfg->bits() = zero_extend(0b0);
+  /* initialize vector csrs */
+  elen               = 0b1; /* ELEN=64 as the common case */
+  vlen               = 0b0100; /* VLEN=512 as a default value */
+  vlenb              = to_bits(sizeof(xlen), 2 ^ (get_vlen_pow() - 3)); /* vlenb holds the constant value VLEN/8 */
+  /* VLEN value needs to be manually changed currently.
+   * See riscv_vlen.sail for details.
+   */
+  vstart             = zero_extend(0b0);
+  vxsat              = 0b0;
+  vxrm               = 0b00;
+  vcsr->vxrm()       = vxrm;
+  vcsr->vxsat()      = vxsat;
+  vl                 = zero_extend(0b0);
+  vtype->vill()      = 0b1;
+  vtype->reserved()  = zero_extend(0b0);
+  vtype->vma()       = 0b0;
+  vtype->vta()       = 0b0;
+  vtype->vsew()      = 0b000;
+  vtype->vlmul()     = 0b000;
 
   init_pmp();