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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-27 16:44:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-27 16:44:36 -0700 |
| commit | ee7e785e5da8c79376c716dc17a4d7f74e1d106f (patch) | |
| tree | 2bd0e34cef9eace74709ab4043e3b9aa8413ab05 /model/riscv_mem.sail | |
| parent | 83c3ec61ffb62d618cdf5c1682bb605c4887584b (diff) | |
| parent | 3a57475dfd443d94f631be887cbddae9ed93ede1 (diff) | |
| download | sail-riscv-ee7e785e5da8c79376c716dc17a4d7f74e1d106f.zip sail-riscv-ee7e785e5da8c79376c716dc17a4d7f74e1d106f.tar.gz sail-riscv-ee7e785e5da8c79376c716dc17a4d7f74e1d106f.tar.bz2 | |
Merge pull request #14 from gameboo/aj443-fixes
Zero extend rather than sign extend rvfi-dii reports (usefull for 32 …
Diffstat (limited to 'model/riscv_mem.sail')
| -rw-r--r-- | model/riscv_mem.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_mem.sail b/model/riscv_mem.sail index 256d6de..c44be53 100644 --- a/model/riscv_mem.sail +++ b/model/riscv_mem.sail @@ -65,7 +65,7 @@ function pmp_mem_read forall 'n, 'n > 0. (t : AccessType, addr : xlenbits, width $ifdef RVFI_DII val rvfi_read : forall 'n, 'n > 0. (xlenbits, atom('n), MemoryOpResult(bits(8 * 'n))) -> unit effect {wreg} function rvfi_read (addr, width, result) = { - rvfi_exec->rvfi_mem_addr() = EXTS(addr); + rvfi_exec->rvfi_mem_addr() = EXTZ(addr); match result { MemValue(v) => if width <= 8 then { rvfi_exec->rvfi_mem_rdata() = sail_zero_extend(v,64); @@ -119,7 +119,7 @@ function mem_write_ea (addr, width, aq, rl, con) = { $ifdef RVFI_DII val rvfi_write : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> unit effect {wreg} function rvfi_write (addr, width, value) = { - rvfi_exec->rvfi_mem_addr() = EXTS(addr); + rvfi_exec->rvfi_mem_addr() = EXTZ(addr); if width <= 8 then { rvfi_exec->rvfi_mem_wdata() = sail_zero_extend(value,64); rvfi_exec->rvfi_mem_wmask() = rvfi_encode_width_mask(width); |