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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-14 18:39:42 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-14 19:02:04 -0800 |
| commit | 3fdda1f2e054a01c95ff59593a8d67d85770609a (patch) | |
| tree | ce460b93f6240d98eaef659dbff2442402ee627d /model/riscv_jalr_rmem.sail | |
| parent | 3c0168526eb9895292a6f92b42f243fce4fd1a9d (diff) | |
| download | sail-riscv-3fdda1f2e054a01c95ff59593a8d67d85770609a.zip sail-riscv-3fdda1f2e054a01c95ff59593a8d67d85770609a.tar.gz sail-riscv-3fdda1f2e054a01c95ff59593a8d67d85770609a.tar.bz2 | |
Reorganize directory structure.
Diffstat (limited to 'model/riscv_jalr_rmem.sail')
| -rw-r--r-- | model/riscv_jalr_rmem.sail | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/model/riscv_jalr_rmem.sail b/model/riscv_jalr_rmem.sail new file mode 100644 index 0000000..daf4bb0 --- /dev/null +++ b/model/riscv_jalr_rmem.sail @@ -0,0 +1,10 @@ +/* The definition for the memory model. */ + +function clause execute (RISCV_JALR(imm, rs1, rd)) = { + /* FIXME: this does not check for a misaligned target address. See riscv_jalr_seq.sail. */ + /* write rd before anything else to prevent unintended strength */ + X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */ + let newPC : xlenbits = X(rs1) + EXTS(imm); + nextPC = newPC[63..1] @ 0b0; + true +} |